CN105336684A - Polysilicon array substrate manufacturing method, polysilicon array and display panel - Google Patents
Polysilicon array substrate manufacturing method, polysilicon array and display panel Download PDFInfo
- Publication number
- CN105336684A CN105336684A CN201510691223.1A CN201510691223A CN105336684A CN 105336684 A CN105336684 A CN 105336684A CN 201510691223 A CN201510691223 A CN 201510691223A CN 105336684 A CN105336684 A CN 105336684A
- Authority
- CN
- China
- Prior art keywords
- layer
- array substrate
- polysilicon array
- photoresist
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 114
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 103
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 103
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 49
- 239000010410 layer Substances 0.000 claims abstract description 220
- 238000000034 method Methods 0.000 claims abstract description 110
- 239000011347 resin Substances 0.000 claims abstract description 50
- 229920005989 resin Polymers 0.000 claims abstract description 50
- 239000011229 interlayer Substances 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 30
- 238000000059 patterning Methods 0.000 claims description 39
- 229920002120 photoresistant polymer Polymers 0.000 claims description 36
- 238000002161 passivation Methods 0.000 claims description 30
- 239000012212 insulator Substances 0.000 claims description 29
- 230000000873 masking effect Effects 0.000 claims description 21
- 230000015572 biosynthetic process Effects 0.000 claims description 18
- 239000011810 insulating material Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 14
- 239000011149 active material Substances 0.000 claims description 3
- 238000004380 ashing Methods 0.000 claims description 2
- 239000012774 insulation material Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 3
- 239000010408 film Substances 0.000 description 28
- 239000011248 coating agent Substances 0.000 description 11
- 238000000576 coating method Methods 0.000 description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000004026 adhesive bonding Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 208000035126 Facies Diseases 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a polysilicon array substrate manufacturing method, a polysilicon array and a display panel, relating to the display technology field. The invention solves the problem that the manufacture method for the polysilicon array substrate is complicated and is difficult. The polysilicon array substrate manufacturing method comprises steps of successively forming a grid material insulation layer, an interlayer insulation material layer and a resin material layer, forming the patterns of the grid insulation layer, the interlayer insulation layer and a resin flat layer through one-time technical drawing, and/or, successively forming a public electrode layer and a source/drain electrode layer, and forming the patterns of the public electrode, the source/drain electrode and the data line through one time technical drawing. The polysilicon array substrate is obtained through the polysilicon array substrate manufacturing method, and the display panel comprises the polysilicon array substrate provided by the technical scheme. The polysilicon array substrate manufacturing method is used for manufacturing the polysilicon array substrate.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of manufacture method of polysilicon array substrate, polysilicon array substrate and display floater.
Background technology
At present, along with developing rapidly of electronic equipment, display floater is more and more applied in electronic equipment, and display floater comprises array base palte and color membrane substrates, and array base palte is one of important composition of display floater.According to the material of the thin-film transistor in array base palte, array base palte can be divided into polysilicon array substrate and amorphous silicon array base palte, the electron mobility of polysilicon array substrate is far longer than amorphous silicon array base palte, therefore, polysilicon array substrate has larger advantage in application aspect, polysilicon array substrate is often obtained by low-temperature polysilicon silicon technology, low-temperature polysilicon silicon technology is in encapsulation process, utilize quasi-molecule radium-shine as thermal source, laser light is after projection system, the equally distributed radium-shine light beam of meeting produce power, laser beam projection is on the substrate of amorphous silicon structures, after amorphous silicon structures substrate absorbs the radium-shine energy of quasi-molecule, polysilicon structure can be transformed into.
But in the prior art, make the pattern that polysilicon array substrate forms light shield layer, active layer, grid (containing grid line), interlayer insulating film (containing gate insulator), source/drain (containing data wire), resin flatness layer, public electrode, passivation layer and pixel electrode, each needs patterning processes respectively, a masking process is carried out in a patterning processes, that is, make polysilicon array substrate at least to need to carry out nine masking process, make the manufacturing process of polysilicon array substrate comparatively complicated, make difficulty.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of polysilicon array substrate, polysilicon array substrate and display floater, for simplifying the manufacturing process of polysilicon array substrate, reducing the manufacture difficulty of polysilicon array substrate.
To achieve these goals, the invention provides following technical scheme:
First aspect, the invention provides a kind of manufacture method of polysilicon array substrate, comprising:
Form gate insulating material layer, interlayer dielectic layer and resin material layer successively, by the pattern of patterning processes formation gate insulator, interlayer insulating film and a resin flatness layer;
And/or, form common electrode layer and source/drain electrode layer successively, by the pattern of patterning processes formation public electrode, source/drain and a data wire.
Second aspect, the invention provides a kind of polysilicon array substrate, and described polysilicon array substrate adopts the manufacture method described in such scheme to make.
The third aspect, the invention provides another kind of display floater, and described display floater comprises the polysilicon array substrate described in such scheme.
The manufacture method of polysilicon array substrate provided by the invention, in polysilicon array substrate and display floater, gate insulator is formed by a patterning processes, the pattern of interlayer insulating film and resin flatness layer, and/or form public electrode by a patterning processes, the pattern of source/drain and data wire, owing to only needing in a patterning processes to carry out a masking process, with the interlayer insulating film made in prior art in polysilicon array substrate (containing gate insulator), source/drain (containing data wire), resin flatness layer, public electrode at least needs the manufacture method of carrying out four masking process to compare, the present invention is making the interlayer insulating film in polysilicon array substrate, containing gate insulator, source/drain and data wire, resin flatness layer, only need in the process of public electrode to carry out two to three masking process, make to decrease one to twice masking process in the process of polysilicon array substrate, simplify the manufacturing process of polysilicon array substrate, reduce the manufacture difficulty of polysilicon array substrate.
Accompanying drawing explanation
Accompanying drawing described herein is used to provide a further understanding of the present invention, forms a part of the present invention, and schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the flow chart of the manufacture method of polysilicon array substrate in the embodiment of the present invention one;
Fig. 2 is the structural representation one of the polysilicon array substrate in the embodiment of the present invention one;
Fig. 3 is the structural representation two of the polysilicon array substrate in the embodiment of the present invention one;
Fig. 4 is the structural representation three of the polysilicon array substrate in the embodiment of the present invention one;
Fig. 5 is the flow chart of the manufacture method of polysilicon array substrate in the embodiment of the present invention two;
Fig. 6 is the flow chart of the manufacture method of polysilicon array substrate in the embodiment of the present invention three;
Fig. 7 a-Fig. 7 g is the operation schematic diagram of the polysilicon array substrate in the embodiment of the present invention three.
Reference numeral:
10-underlay substrate, 11-light shield layer,
12-resilient coating, 13-active layer,
14-ohmic contact layer, 15-drains lightly-doped layer,
16-gate insulator, 17-grid and grid line,
18-interlayer insulating film, 19-resin flatness layer,
20-public electrode, 21-source/drain and data wire,
22-passivation layer, 23-pixel electrode.
Embodiment
In order to further illustrate the manufacture method of the polysilicon array substrate that the embodiment of the present invention provides, polysilicon array substrate and display floater, be described in detail below in conjunction with Figure of description.
Embodiment one
Refer to Fig. 1, the manufacture method of the polysilicon array substrate that the embodiment of the present invention provides, comprising:
Step 101, forms gate insulating material layer, interlayer dielectic layer and resin material layer successively, by the pattern of patterning processes formation gate insulator 16, interlayer insulating film 18 and a resin flatness layer 19; In this step, form one deck gate insulating material layer, insulation material layer between being formed above gate insulating material layer from level to level, interlayer dielectic layer is formed one deck resin material layer, utilizes the pattern of patterning processes formation gate insulator 16, interlayer insulating film 18 and a resin flatness layer 19.
Step 102, forms common electrode layer and source/drain electrode layer successively, by the pattern of patterning processes formation public electrode 20, source/drain and a data wire 21; In this step, form one deck common electrode layer, above common electrode layer, form one deck source/drain electrode layer, formed the pattern of public electrode 20, source/drain level and data wire 21 by patterning processes in common electrode layer and source/drain electrode layer.One time patterning processes can comprise the steps such as gluing, exposure, development, etching, does not limit at this.
It should be noted that, step 101 and step 102 be and/or relation, namely only can there is step 101, also only step 102 can be there is, or there are step 101 and 102, when step 101 and step 102 exist simultaneously, step 101 performs prior to step 102 simultaneously.
Refer to Fig. 2, Fig. 2 is the schematic cross-section of the polysilicon array substrate (performing the polysilicon array substrate of step 101 and step 102 making in the manufacture method of above-mentioned polysilicon array substrate) utilizing the manufacture method of above-mentioned polysilicon array substrate to make, wherein, this polysilicon array substrate comprises underlay substrate 10, underlay substrate 10 is provided with light shield layer 11, light shield layer 11 and underlay substrate 10 are provided with resilient coating 12, resilient coating 12 is provided with active layer 13, ohmic contact layer 14 and drain electrode lightly-doped layer 15, at active layer 13, ohmic contact layer 14, drain electrode lightly-doped layer 15 and resilient coating 12 are provided with gate insulator 16, gate insulator 16 is provided with grid and grid line 17, grid and grid line 17 and gate insulator 16 are provided with interlayer insulating film 18, interlayer insulating film 18 is provided with resin flatness layer 19, the first via hole and the second via hole is provided with at resin flatness layer 19, first via hole ends in ohmic contact layer 14, second via hole ends in grid and grid line 17, and grid and grid line 17 are arranged with layer, in the first via hole, the second via hole and on resin flatness layer 19, be provided with public electrode 20, source/drain and data wire 21, source/drain and data wire 21 are arranged with layer, and are positioned at above public electrode 20, resin flatness layer 19, public electrode 20, source/drain and data wire 21 are provided with passivation layer 22, and passivation layer 22 is provided with the 3rd via hole, pixel electrode 23 is provided with at the 3rd via hole.
Or, refer to Fig. 3, Fig. 3 is the schematic cross-section of the another kind of polysilicon array substrate (only performing the polysilicon array substrate that step 101 makes in the manufacture method of above-mentioned polysilicon array substrate) utilizing the manufacture method of above-mentioned polysilicon array substrate to make, wherein, this polysilicon array substrate comprises underlay substrate 10, underlay substrate 10 is provided with light shield layer 11, light shield layer 11 and underlay substrate 10 are provided with resilient coating 12, resilient coating 12 is provided with active layer 13, ohmic contact layer 14 and drain electrode lightly-doped layer 15, at active layer 13, ohmic contact layer 14, drain electrode lightly-doped layer 15 and resilient coating 12 are provided with gate insulator 16, gate insulator 16 is provided with grid and grid line 17, grid and grid line 17 and gate insulator 16 are provided with interlayer insulating film 18, interlayer insulating film 18 is provided with resin flatness layer 19, the first via hole and the second via hole is provided with at resin flatness layer 19, first via hole ends in ohmic contact layer 14, second via hole ends in grid and grid line 17, and grid and grid line 17 are arranged with layer, first via hole, the second via hole and resin flatness layer 19 are provided with source/drain and data wire 21, source/drain and data wire 21 are arranged with layer, source/drain in the second via hole and data wire 21 are provided with public electrode 20, resin flatness layer 19, public electrode 20, source/drain and data wire 21 are provided with passivation layer 22, and passivation layer 22 is provided with the 3rd via hole, pixel electrode 23 is provided with at the 3rd via hole.
Or, refer to Fig. 4, Fig. 4 is the schematic cross-section of another polysilicon array substrate (only performing the polysilicon array substrate that step 102 makes in the manufacture method of above-mentioned polysilicon array substrate) utilizing the manufacture method of above-mentioned polysilicon array substrate to make, wherein, this polysilicon array substrate comprises underlay substrate 10, underlay substrate 10 is provided with light shield layer 11, light shield layer 11 and underlay substrate 10 are provided with resilient coating 12, resilient coating 12 is provided with active layer 13, ohmic contact layer 14 and drain electrode lightly-doped layer 15, at active layer 13, ohmic contact layer 14, drain electrode lightly-doped layer 15 and resilient coating 12 are provided with gate insulator 16, gate insulator 16 is provided with grid and grid line 17, grid and grid line 17 and gate insulator 16 are provided with interlayer insulating film 18, interlayer insulating film 18 is provided with the 4th via hole and the 5th via hole, 4th via hole runs through interlayer insulating film 18 and gate insulator 16, end in ohmic contact layer 14, 5th via hole runs through interlayer insulating film 18, ends in grid and grid line 17, and grid and grid line 17 are arranged with layer, 4th via hole, the 5th via hole and interlayer insulating film 18 are provided with public electrode 20, source/drain and data wire 21, and source/drain and data wire 21 are arranged with layer, and are positioned at above public electrode 20, interlayer insulating film 18, public electrode 20, source/drain and data wire 21 are provided with resin flatness layer 19, and resin flatness layer 19 is provided with the 6th via hole, and the 6th via hole runs through resin flatness layer 19, 6th via hole is provided with pixel electrode 23.
The concrete manufacture method of active layer 13 in above-mentioned polysilicon array substrate, ohmic contact layer 14 and drain electrode lightly-doped layer 15 will be illustrated below: the process being formed with active layer 13 comprises, form one deck amorphous silicon (a-Si) film (i.e. active material), adopt quasi-molecule laser annealing technique, amorphous silicon membrane is converted into polysilicon (p-Si) film, and through patterning processes such as overexposure, development, etchings, be formed with the pattern of active layer 13; The process forming grid and grid line 17 comprises, active layer 13 and resilient coating 12 form gate insulator 16, gate insulator 16 is formed one deck grid electrode layer, grid electrode layer is carried out to the patterning processes such as gluing, exposure, development and etching, form the pattern of grid and grid line 17; The process forming ohmic contact layer 14 comprises, and carries out heavy doping to the region of the active layer 13 not corresponding with the pattern of grid and grid line 17, forms the pattern of ohmic contact layer 14; The process forming drain electrode lightly-doped layer 15 comprises, and carries out drain electrode light dope to partial polysilicon film, forms the pattern of drain electrode lightly-doped layer 15.
The structure of the polysilicon array substrate utilizing above-mentioned manufacture method to make in the embodiment of the present invention includes but not limited to said structure, and the polysilicon array substrate that in the use embodiment of the present invention, above-mentioned manufacture method can be produced is all in the protection range of the embodiment of the present invention.
In the manufacture method of polysilicon array substrate provided by the invention and polysilicon array substrate, gate insulator is formed by a patterning processes, the pattern of interlayer insulating film and resin flatness layer, and/or form public electrode by a patterning processes, the pattern of source/drain and data wire, owing to only needing in a patterning processes to carry out a masking process, with the interlayer insulating film made in prior art in polysilicon array substrate (containing gate insulator), source/drain (containing data wire), resin flatness layer, public electrode at least needs the manufacture method of carrying out four masking process to compare, the present invention is making the interlayer insulating film in polysilicon array substrate, containing gate insulator, source/drain and data wire, resin flatness layer, only need in the process of public electrode to carry out two to three masking process, make to decrease one to twice masking process in the process of polysilicon array substrate, simplify the manufacturing process of polysilicon array substrate, reduce the manufacture difficulty of polysilicon array substrate.
Embodiment two
Refer to Fig. 5, below by the specific implementation method of the step 101 that illustrates in embodiment one and step 102, wherein, step 101 specifically can be refined as step 1011 and step 1012, step 102 specifically can be refined as step 1021-step 1024, and particular content is as follows:
Step 1011, forms gate insulating material layer, interlayer dielectic layer and resin material layer successively.
Step 1012, utilize a masking process, etching technics is carried out to resin material layer, interlayer dielectic layer and gate insulating material layer, form the first via hole and the second via hole at resin material layer, interlayer dielectic layer and gate insulating material layer, obtain the pattern of resin flatness layer 19, interlayer insulating film 18 and gate insulator 16; Wherein, the first via hole runs through resin material layer, interlayer dielectic layer and gate insulating material layer, and the second via hole runs through resin material layer and interlayer dielectic layer, thus obtains the pattern of resin flatness layer 19, interlayer insulating film 18 and gate insulator 16.
Step 1021, forms common electrode layer and source/drain electrode layer successively, utilizes grayscale mask plate, forms photoresist remove district, the complete reserved area of photoresist and photoresist half reserved area completely by a masking process; Wherein, corresponding region except public electrode 20, source/drain and data wire 21, district removed completely by photoresist, the corresponding public electrode 20 in photoresist half reserved area, photoresist complete reserved area correspondence removes region corresponding to district and photoresist half reserved area completely except photoresist.
Step 1022, by etching technics, part photoresist being removed completely common electrode layer corresponding to district and source/drain electrode layer is removed; In step 1022, the first time etching technics in a patterning processes in carry out step 102.
Step 1023, carries out ashing process to the photoresist of the complete reserved area of photoresist and photoresist half reserved area, by thinning for the photoresist of complete for photoresist reserved area, is removed completely by the photoresist of photoresist half reserved area.
Step 1024, etches remaining source/drain electrode layer, and is removed completely by the photoresist of complete for photoresist reserved area, forms the pattern of public electrode 20, source/drain and data wire 21; Wherein, in step 1024, the second time etching technics in carry out step 102 in a patterning processes; Step 1021-step 1024, by the twice etching technique in a patterning processes, obtains the pattern of public electrode 20, source/drain and data wire 21.
It should be noted that, as shown in Figure 4, in polysilicon array substrate, passivation layer 22 can not also be set, when not arranging passivation layer 22 in polysilicon array substrate, form gate insulating material layer and interlayer dielectic layer successively, utilize a masking process, etching technics is carried out to gate insulating material layer and interlayer dielectic layer, gate insulating material layer and interlayer dielectic layer form the 4th via hole and the 5th via hole, thus form the pattern of gate insulator 16 and interlayer insulating film 18, wherein, 4th via hole runs through gate insulating material layer and interlayer dielectic layer, end in ohmic contact layer 14, insulation material layer between the 5th via hole extending through layer, end in grid and grid line 17.
The polysilicon array substrate utilizing the manufacture method of the polysilicon array substrate in the embodiment of the present invention to make can see the related description content in embodiment one.
Embodiment three
Refer to Fig. 6, in polysilicon array substrate, also comprise the structure such as underlay substrate 10, light shield layer 11, active layer 13, ohmic contact layer 14, drain electrode lightly-doped layer 15, grid and grid line 17, passivation layer 22 and pixel electrode 23, in order to make said structure, before step 101 in embodiment one, also comprise step 103-step 105, after step 102, also comprise step 106 and step 107, the particular content of step 103-step 107 is as follows:
Step 103, underlay substrate 10 forms light-shielding material layers, by the pattern of a patterning processes formation light shield layer 11.
Step 104, forms active material above light shield layer 11 and underlay substrate 10, is formed with the pattern of active layer 13 by patterning processes.
Step 105, active layer 13 forms grid electrode layer, is formed the pattern of grid and grid line 17 by patterning processes; Wherein, after completing steps 105, blocking of grid and grid line 17 can be utilized, heavy doping or drain electrode light dope are carried out to part active layer 13, be formed with the final pattern of active layer 13, ohmic contact layer 14 and drain electrode lightly-doped layer 15, the concrete forming process of active layer 13, ohmic contact layer 14 and drain electrode lightly-doped layer 15 is see embodiment one related description content.
Step 106, forms layer of passivation material above public electrode 20, source/drain and data wire 21, and passes through the pattern of a patterning processes formation passivation layer 22; Wherein, specifically can be refined as by the pattern of a patterning processes formation passivation layer 22 and utilize a masking process, etching technics is carried out to layer of passivation material, the 3rd via hole is formed in layer of passivation material, 3rd via hole runs through layer of passivation material, thus obtaining the pattern of passivation layer 22, the concrete structure of passivation layer 22 can consult Fig. 2 and Fig. 3.It should be noted that, as shown in Figure 4, in polysilicon array substrate, passivation layer 22 can not also be set, when not arranging passivation layer 22 in polysilicon array substrate, public electrode 20, source/drain and data wire 21 is positioned on interlayer insulating film 18, above public electrode 20, source/drain and data wire 21, form resin material layer, and pass through the pattern of a patterning processes formation resin flatness layer 19; Wherein, specifically can be refined as by the step of the pattern of a patterning processes formation resin flatness layer 19 and utilize a masking process, etching technics is carried out to resin material layer, the 6th via hole is formed at resin material layer, 6th via hole runs through resin material layer, thus obtains the pattern of resin flatness layer 19.
Step 107, forms pixel electrode layer above passivation layer 22, and passes through the pattern of a patterning processes formation pixel electrode 23; Concrete, pixel electrode 23 can be positioned at the 3rd via hole.It should be noted that, as shown in Figure 4, in polysilicon array substrate, passivation layer 22 can not also be set, when not arranging passivation layer 22 in polysilicon array substrate, pixel electrode layer is formed above resin flatness layer 19, by the pattern of a patterning processes formation pixel electrode 23, concrete, pixel electrode can be positioned at the 6th via hole.
One to embodiment three in conjunction with the embodiments, can learn, in the embodiment of the present invention, the manufacture method of polysilicon array substrate only needs to carry out seven to eight masking process, compared to existing technology, decrease one to twice masking process, simplify the manufacturing process of polysilicon array substrate.Such as: Fig. 7 a-Fig. 7 g is the operation schematic diagram of polysilicon array substrate, describe seven masking process in the manufacturing process of polysilicon array substrate, wherein, Fig. 7 a is corresponding with step 103, and Fig. 7 b is corresponding with step 104, Fig. 7 c is corresponding with step 105, Fig. 7 d is corresponding with step 101, and Fig. 7 e is corresponding with step 102, and Fig. 7 f is corresponding with step 106, Fig. 7 g is corresponding with step 107, and the polysilicon array substrate utilizing this manufacture method to make is see the related description content in embodiment one.
Embodiment four
The embodiment of the present invention provides a kind of display floater, this display floater comprises the polysilicon array substrate described in above-described embodiment, make in polysilicon array substrate in described display floater and above-described embodiment Dominant Facies that the polysilicon array substrate that obtains has with, repeat no more herein.Concrete, display floater can be any product or parts with Presentation Function such as display panels, Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator.
In the description of above-mentioned execution mode, specific features, structure or feature can combine in an appropriate manner in any one or more embodiment or example.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (8)
1. a manufacture method for polysilicon array substrate, is characterized in that, comprising:
Form gate insulating material layer, interlayer dielectic layer and resin material layer successively, by the pattern of patterning processes formation gate insulator, interlayer insulating film and a resin flatness layer;
And/or, form common electrode layer and source/drain electrode layer successively, by the pattern of patterning processes formation public electrode, source/drain and a data wire.
2. the manufacture method of polysilicon array substrate according to claim 1, is characterized in that, the step of the described pattern by patterning processes formation gate insulator, interlayer insulating film and a resin flatness layer specifically comprises:
Utilize a masking process, etching technics is carried out to described resin material layer, described interlayer dielectic layer and described gate insulating material layer, described resin material layer, described interlayer dielectic layer and described gate insulating material layer form the first via hole, the second via hole, obtain the pattern of described gate insulator, interlayer insulating film and resin flatness layer, described first via hole runs through described resin material layer, described interlayer dielectic layer and described gate insulating material layer, and described second via hole runs through described resin material layer and described interlayer dielectic layer.
3. the manufacture method of polysilicon array substrate according to claim 1, is characterized in that, the step of the described pattern by patterning processes formation public electrode, source/drain and a data wire specifically comprises:
Utilize grayscale mask plate, form photoresist by a masking process and remove district, the complete reserved area of photoresist and photoresist half reserved area completely, corresponding region except described public electrode, described source/drain and described data wire, district removed completely by described photoresist, the corresponding described public electrode in described photoresist half reserved area, described photoresist complete reserved area correspondence removes region corresponding to district and described photoresist half reserved area completely except described photoresist;
By etching technics, the part described photoresist being removed completely described common electrode layer corresponding to district and described source/drain electrode layer is removed;
Ashing process is carried out to the photoresist of the complete reserved area of described photoresist and described photoresist half reserved area, by thinning for the photoresist of complete for described photoresist reserved area, the photoresist of described photoresist half reserved area is removed completely;
Remaining described source/drain electrode layer is etched, and the photoresist of complete for described photoresist reserved area is removed completely, form the pattern of described public electrode, described source/drain and described data wire.
4. the manufacture method of polysilicon array substrate according to claim 1, is characterized in that, also comprises:
Underlay substrate forms light-shielding material layers, by the pattern of a patterning processes formation light shield layer;
Above described light shield layer and described underlay substrate, form active material, be formed with the pattern of active layer by patterning processes;
Above described active layer, form grid electrode layer, formed the pattern of grid and grid line by patterning processes.
5. the manufacture method of polysilicon array substrate according to claim 1, is characterized in that, also comprises:
Above described public electrode, described source/drain and described data wire, form layer of passivation material, formed the pattern of described passivation layer by patterning processes;
Pixel electrode layer is formed, by the pattern of a patterning processes formation pixel electrode above described passivation layer.
6. the manufacture method of polysilicon array substrate according to claim 5, is characterized in that, the described step forming the pattern of described passivation layer by patterning processes specifically comprises:
Utilize a masking process, carry out etching technics to described layer of passivation material, form the 3rd via hole in described layer of passivation material, obtain the pattern of described passivation layer, described 3rd via hole runs through described layer of passivation material.
7. a polysilicon array substrate, is characterized in that, described polysilicon array substrate adopts the manufacture method according to any one of claim 1-6 to make.
8. a display floater, is characterized in that, described display floater comprises polysilicon array substrate as claimed in claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510691223.1A CN105336684A (en) | 2015-10-22 | 2015-10-22 | Polysilicon array substrate manufacturing method, polysilicon array and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510691223.1A CN105336684A (en) | 2015-10-22 | 2015-10-22 | Polysilicon array substrate manufacturing method, polysilicon array and display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105336684A true CN105336684A (en) | 2016-02-17 |
Family
ID=55287123
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510691223.1A Pending CN105336684A (en) | 2015-10-22 | 2015-10-22 | Polysilicon array substrate manufacturing method, polysilicon array and display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105336684A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107481938A (en) * | 2017-09-26 | 2017-12-15 | 武汉华星光电技术有限公司 | The preparation method of display panel, display device and low-temperature polysilicon film transistor |
| CN108761887A (en) * | 2018-04-28 | 2018-11-06 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| WO2019205333A1 (en) * | 2018-04-28 | 2019-10-31 | 武汉华星光电技术有限公司 | Array substrate and manufacturing method therefor |
| CN111916464A (en) * | 2020-09-15 | 2020-11-10 | 武汉华星光电技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN113658912A (en) * | 2021-07-09 | 2021-11-16 | 深圳莱宝高科技股份有限公司 | Array substrate manufacturing method, array substrate, electronic paper device and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101479657A (en) * | 2006-09-27 | 2009-07-08 | 夏普株式会社 | Active matrix substrate and liquid crystal display device provided with same |
| US20140132872A1 (en) * | 2005-12-28 | 2014-05-15 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| CN104600030A (en) * | 2015-02-02 | 2015-05-06 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
-
2015
- 2015-10-22 CN CN201510691223.1A patent/CN105336684A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140132872A1 (en) * | 2005-12-28 | 2014-05-15 | Semiconductor Energy Laboratory Co., Ltd. | Display device and manufacturing method thereof |
| CN101479657A (en) * | 2006-09-27 | 2009-07-08 | 夏普株式会社 | Active matrix substrate and liquid crystal display device provided with same |
| CN104600030A (en) * | 2015-02-02 | 2015-05-06 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method of array substrate and display device |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107481938A (en) * | 2017-09-26 | 2017-12-15 | 武汉华星光电技术有限公司 | The preparation method of display panel, display device and low-temperature polysilicon film transistor |
| WO2019061586A1 (en) * | 2017-09-26 | 2019-04-04 | 武汉华星光电技术有限公司 | Display panel, display device and preparation method of low temperature poly-silicon thin film transistor |
| US10515984B1 (en) | 2017-09-26 | 2019-12-24 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Display panel, display device and method for preparing a low-temperature polysilicon thin film transistor |
| CN107481938B (en) * | 2017-09-26 | 2020-02-18 | 武汉华星光电技术有限公司 | Display panel, display device and preparation method of low-temperature polycrystalline silicon thin film transistor |
| CN108761887A (en) * | 2018-04-28 | 2018-11-06 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| WO2019205333A1 (en) * | 2018-04-28 | 2019-10-31 | 武汉华星光电技术有限公司 | Array substrate and manufacturing method therefor |
| CN111916464A (en) * | 2020-09-15 | 2020-11-10 | 武汉华星光电技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN111916464B (en) * | 2020-09-15 | 2023-12-01 | 武汉华星光电技术有限公司 | Array substrate, preparation method thereof and display panel |
| CN113658912A (en) * | 2021-07-09 | 2021-11-16 | 深圳莱宝高科技股份有限公司 | Array substrate manufacturing method, array substrate, electronic paper device and manufacturing method thereof |
| CN113658912B (en) * | 2021-07-09 | 2024-04-16 | 深圳莱宝高科技股份有限公司 | Array substrate manufacturing method, array substrate, electronic paper device and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103208491B (en) | Array base palte and manufacture method, display unit | |
| CN104022126B (en) | Array substrate and manufacturing method thereof, and display apparatus | |
| CN104617102B (en) | Array base palte and manufacturing method of array base plate | |
| CN105336684A (en) | Polysilicon array substrate manufacturing method, polysilicon array and display panel | |
| CN203871327U (en) | Array substrate and display device | |
| US9842935B2 (en) | Low temperature poly silicon (LTPS) thin film transistor (TFT) and the manufacturing method thereof | |
| CN103123910A (en) | Array substrate, manufacture method of array substrate and display device | |
| CN106098699A (en) | A kind of array base palte, its manufacture method, display floater and preparation method thereof | |
| JP2018503869A (en) | Array substrate, display panel, and method for preparing array substrate | |
| CN104600030A (en) | Array substrate, manufacturing method of array substrate and display device | |
| US11018165B2 (en) | Manufacturing method of array substrate and array substrate | |
| CN106449653B (en) | A kind of display base plate and preparation method thereof, display panel, display device | |
| CN107275340A (en) | Film crystal tube preparation method, array base palte, its preparation method and display device | |
| CN101236904A (en) | Making method for multi-crystal silicon film transistor with the slight adulterated leakage pole area | |
| CN109786324B (en) | Low-temperature polycrystalline silicon substrate, manufacturing method thereof and array substrate | |
| US10134765B2 (en) | Oxide semiconductor TFT array substrate and method for manufacturing the same | |
| CN101740524B (en) | Method for manufacturing thin film transistor array substrate | |
| US20190280016A1 (en) | Manufacturing method of array substrate and array substrate | |
| CN104538354B (en) | A kind of LTPS TFT pixel cells and its manufacture method | |
| CN108400139B (en) | Array substrate, manufacturing method thereof and display device | |
| US10347631B2 (en) | Thin film transistor and method of manufacturing the same, array substrate, and display device | |
| CN104952887A (en) | Array substrate and preparation method thereof as well as display device | |
| CN106128962B (en) | A kind of thin film transistor and its manufacturing method, array substrate, display device | |
| CN106129071A (en) | The manufacture method of a kind of array base palte and related device | |
| CN203085536U (en) | Array substrate and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160217 |
|
| RJ01 | Rejection of invention patent application after publication |