CN105321870A - Method for manufacturing embedded silicon germanium (SiGe) - Google Patents
Method for manufacturing embedded silicon germanium (SiGe) Download PDFInfo
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- CN105321870A CN105321870A CN201410374245.0A CN201410374245A CN105321870A CN 105321870 A CN105321870 A CN 105321870A CN 201410374245 A CN201410374245 A CN 201410374245A CN 105321870 A CN105321870 A CN 105321870A
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Abstract
The invention discloses a method for manufacturing embedded silicon germanium (SiGe). Through the method, the existing technology can be simplified, and a good and controllable stress layer can be obtained. The method comprises the steps of forming separating structures on a substrate; etching the substrate to remove substrate materials among the separating structures; forming an etching stop layer; forming a first semiconductor layer on the etching stop layer; forming a grid electrode and a side wall on the first semiconductor layer; selectively removing the first semiconductor layer, and only keeping the part, below the gird electrode and the side wall, of the first semiconductor layer to form a source region groove and a drain region groove; and performing wet etching with crystal orientation on the residual part of the first semiconductor layer to form a sigma shape on the side wall of the first semiconductor layer.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relating to a kind of method for making embedded germanium silicon.
Background technology
Along with developing rapidly of nanofabrication technique, the characteristic size of transistor enters nanoscale.The restriction of more and more physics, technique is subject to by the performance of the method raising current main-stream silicon CMOS device of scaled down.The development speed that can continue Moore's Law to make integrated circuit technique and disclose, must develop and the new material of silicon technology compatibility, new construction and new property.In recent years, strained silicon (StrainedSi) technology is owing to receiving much concern in the excellent performance improving cmos device aspect of performance.Such as, by introducing suitable compression in channels and tensile stress can improve the hole mobility of PMOS and the electron mobility of NMOS respectively.Typical PMOS strained silicon introduces raceway groove compression by epitaxy Si Ge source and drain, utilizes the lattice constant mismatch controlled strain size of source and drain and raceway groove, and then improves hole mobility; Then by deposit SiN film, raceway groove tensile stress is introduced for NMOS strained silicon, utilizes the high intrinsic controlled strain size of SiN film, and then improve electron mobility.Therefore, by the optimal design of technique, material, structural parameters, in research semiconductor nano device, the control of stress, strain has important scientific meaning and practical value.
For PMOS, embedded SiGe technology is the most effective method that stress suffered by raceway groove is promoted, and for volume production.Research finds that SiGe more more can apply large stress close to raceway groove, makes the performance of PMOS obtain larger lifting, and devises kinds of processes method and flow process.
At 28nm technology node, the pattern of the embedded SiGe of main flow is Σ shape, and object promotes the stress be applied on raceway groove, and formation process relies on wet etching to the selectivity of the different crystal face of Si.
Fig. 3 A illustrates the cross section of " ∑ " connected in star that expectation is formed in the substrate.In this sectional view, the extended line 360 (represented by dashed line) of the surface 330 of substrate 300, the first half 340 of recess sidewall and the latter half 350 and bottom portion of groove 380 forms " ∑ " shape.
" ∑ " connected in star shown by Fig. 3 A can by use have crystal orientation optionally wet etching formed.Such as, the crystal plane direction on the surface of substrate 300 can be selected for (001).As shown in Figure 3 B, first, such as, by dry etching, " U " connected in star 310 is formed in the substrate.Crystal plane direction bottom groove 310 is also (001), and the crystal plane direction of sidewall can be then (110).
Then, adopt and there is crystal orientation optionally Wet-etching agent, such as, comprise the etchant of Tetramethylammonium hydroxide (TMAH), etched by " U " connected in star 310 pairs of substrates 300.In this etching process, the etching speed on <111> crystal orientation is less than the etching speed on other crystal orientation.Thus, " U " connected in star 310 is become diamondoid groove 315 by etching, as shown in Figure 3 C.The position of original " U " connected in star 310 is show in phantom in Fig. 3 C.The sidewall of groove 315 has the first half 340 and the latter half 350.The crystal plane direction of the first half 340 and the latter half 350 be substantially respectively (111) and
But, because the etching speed on <100> crystal orientation and <110> crystal orientation is larger than the etching speed on <111> crystal orientation, so be easy to be etched excessively bottom groove 315, thus the latter half 350 of groove 315 both sides sidewall is intersected.So the result of this anisotropic etching often causes the bottom of groove 315 to be sharp, instead of flat.
And if the bottom of groove 315 is sharp, so when during epitaxial growth SiGe, high-quality SiGe not obtained in groove 315.
Therefore, need a kind of method for making embedded germanium silicon of improvement, thus avoid the problems referred to above.
Summary of the invention
The object of this invention is to provide a kind of manufacture method of semiconductor device, by the method, existing technique can be simplified, and good, controlled stressor layers can be obtained.
According to an aspect of the present invention, a kind of manufacture method of semiconductor device is provided, comprises: on substrate, form isolation structure; Etch described substrate, to remove the backing material between isolation structure; Form etching stop layer; Described etching stop layer is formed the first semiconductor layer; Described first semiconductor layer forms grid and side wall; First semiconductor layer described in selective removal, only retains the part of described first semiconductor layer below described grid and side wall, to form source region and drain recesses; To the remainder of described first semiconductor layer, there is crystal orientation optionally wet etching, to form Σ shape on the sidewall of described first semiconductor layer.
According to an aspect of the present invention, in preceding method, substrate is selected from any one in following material: the semiconductor on monocrystalline silicon, monocrystalline silicon through doping, polycrystalline or sandwich construction, insulator, Ge, GaAs or InP.
According to an aspect of the present invention, in preceding method, etching stop layer is SiGe.
According to an aspect of the present invention, in preceding method, etching stop layer is carborundum.
According to an aspect of the present invention, in preceding method, the thickness of etching stop layer is in the scope of 5 dust to 9 dusts.
According to an aspect of the present invention, in preceding method, the first semiconductor layer is the silicon epitaxial layers formed by epitaxial growth; The thickness of described silicon epitaxial layers is not less than 100 dusts.
According to an aspect of the present invention, in preceding method, the thickness of silicon epitaxial layers is in the scope of 300 dust to 800 dusts.
According to an aspect of the present invention, in preceding method, the end face of silicon epitaxial layers by family of crystal planes 100} is formed, and sidewall by family of crystal planes 110} is formed, and described in have crystal orientation optionally wet etching stop at family of crystal planes { 111}.
According to an aspect of the present invention, preceding method is also included in crystal orientation optionally after wet etching, in the source region and drain recesses of Σ shape, form SiGe.
According to an aspect of the present invention, preceding method is also included in crystal orientation optionally after wet etching, in the source region and drain recesses of Σ shape, form SiC.
According to an aspect of the present invention, preceding method is also included between described etching stop layer and described substrate and forms buffering area.
According to an aspect of the present invention, in preceding method, at least one step during the first semiconductor layer described in selective removal comprises the following steps: deposition mask layer; Mask layer on selective removal source region and drain region; Utilize mask layer, by dry etching, described first semiconductor layer is etched, until till described etching stop layer.
Compared with prior art, advantage of the present invention comprises:
According to the solution of the present invention, by before formation active area of semiconductor device, form etching stop layer (ESL), device active region and backing material are isolated, therefore can use various backing material in the present invention, and simplify existing technique; By forming the embedded SiGe of Σ shape on etching stop layer, good, controlled stressor layers can be obtained.In addition, active area, the channel region of PMOS and NMOS are formed by epitaxial growth technology, and compared with being directly formed with the technique in source region on a silicon substrate, the control of this technique to thickness is more accurate, thus improve integrated circuit dimensions precision, thus improve overall performance and stability.
Accompanying drawing explanation
In order to illustrate above and other advantage and the feature of various embodiments of the present invention further, present the description more specifically of various embodiments of the present invention with reference to accompanying drawing.Be appreciated that exemplary embodiments of the present invention only described by these accompanying drawings, therefore will not be considered to restriction on its scope.In the accompanying drawings, in order to cheer and bright, be exaggerated the thickness in layer and region.Identical or corresponding parts will represent with same or similar mark.
Figure 1A to Fig. 1 G illustrates the generalized section of the process forming the embedded SiGe of Σ shape according to one embodiment of present invention.
Fig. 2 illustrates the flow chart of the embedded SiGe of formation Σ shape according to an embodiment of the invention.
The generalized section that Fig. 3 A to Fig. 3 C illustrates " ∑ " connected in star that expectation is formed in the substrate respectively and the generalized section of " ∑ " connected in star formed according to prior art.
Embodiment
In the following description, with reference to each embodiment, present invention is described.But, person of skill in the art will appreciate that and can replace when neither one or multiple specific detail or with other and/or implement each embodiment together with addition method, material or assembly.In other situation, not shown or do not describe known structure, material or operation in detail in order to avoid make the aspects of various embodiments of the present invention obscure.Similarly, in order to the object explained, specific quantity, material and configuration are set forth, to provide the complete understanding to embodiments of the invention.But the present invention can implement when not having specific detail.In addition, each embodiment shown in accompanying drawing should be understood be illustrative expression and not necessarily draw in proportion.
According to one embodiment of present invention, the present invention proposes a kind of method that source-drain area at PMOS forms the embedded SiGe of Σ shape.Figure 1A to Fig. 1 G illustrates the generalized section of the process forming the embedded SiGe of Σ shape according to one embodiment of present invention.As shown in Figure 1A, first, form shallow-trench isolation groove (STI) structure 102 on the substrate 101, and remove the hard mask in active area, thus the first area 103 isolated for the formation of PMOS and second area 104.In one embodiment, second area 104 can be NMOS area, also can be other device area, the conventional transistors region such as being formed based on conventional crystalline pipe manufacturing method.
In the embodiment shown, this substrate 101 can be any material that can be used for producing the semiconductor devices.In certain embodiments, substrate 101 can be single crystal silicon material, single crystal silicon material through doping, Semiconductor substrate on polycrystalline or sandwich construction substrate or insulator.In certain embodiments, substrate 101 can not comprise silicon, alternatively comprises the backing material that such as Ge, GaAs or InP etc. are different.Substrate 101 can comprise one or more materials, device or layer, can be maybe the single material without multilayer.
Next, substrate 101 is etched, remove the backing material in first area 103 and second area 104, to form structure as shown in Figure 1B.According to the device property that will be formed, etching depth can be determined.In one embodiment, etching depth is not less than 100 dusts.In a preferred embodiment, etching depth is between 300 dust to 800 dusts.
Then, as shown in Figure 1 C, etching stop layer 105 and silicon epitaxial layers 106 is formed on the substrate 101.In one embodiment, etching stop layer 105 can be SiGe.In first area 103 and second area 104, SiGe is grown by growth technology.
Such as, the process gas for the formation of SiGe can comprise SiH
4; GeH
4; HCl; BH
6; And H
2, wherein H
2gas flow rate can be 0.1slm to 50slm, the flow velocity of other gas can be 1sccm to 1000sccm, and reaction temperature is at 500-800 DEG C, and pressure holds in the palm at 5-50.
But etching stop layer 105 is not limited to SiGe.Etching stop layer 105 can also be in follow-up any materials of silicon epitaxial layers 106 being carried out to be not etched in dry method and wet etching process or etch rate is very little, such as carborundum.
As required, the thickness of etching stop layer 105 can be determined.Such as, the thickness of etching stop layer 105 can be determined according to the material of selected etching stop layer 105 and the etch rate in follow-up dry method and wet etching process.In one embodiment, the thickness of etching stop layer 105 can be low to moderate 5 dusts.In a preferred embodiment, the thickness of etching stop layer 105 is in the scope of 5-9 dust.In other embodiments, the thickness of etching stop layer 105 can be greater than 9 dusts, such as, in the scope of 9-50 dust.
In one embodiment, the thickness of silicon epitaxial layers 106 is not less than 100 dusts.In a preferred embodiment, the thickness of silicon epitaxial layers 106 is in the scope of 300 dust to 800 dusts.
Then, as shown in figure ip, in first area 103 and second area 104, order forms grid (gate) 107 and side wall (spacer) 108.
Then, deposit hard mask 111, and optionally remove the hard mask of the source-drain area of the first area 103 for PMOS, then by dry etching, source-drain area is etched, till etching stop layer 105, to form the groove 109 and 110 of source-drain area as referring to figure 1e.In one embodiment, the degree of depth of this groove 109 and 110 depends on the thickness of silicon epitaxial layers 106.Such as, the degree of depth of groove 109 and 110 can be not less than 100 dusts.In a preferred embodiment, the degree of depth of this groove is in the scope of 300-800 dust.
Then, adopt the wet etching having high preferred orientation, the silicon epitaxial layers of grid 107 and side wall 108 bottom is etched, thus on the basis of groove 109 and 110, forms Σ shape groove, as shown in fig. 1f.To make in subsequent step epitaxially grown SiGe more close to raceway groove (channel).
Have crystal orientation optionally wet etching be well known in the art.For monocrystalline silicon, the etching speed on <111> crystal orientation is less than the etching speed on other crystal orientation.
Therefore, wet etching will stop at family of crystal planes { on 111}.
In an embodiment of the present invention, by family of crystal planes, { 100} is formed the end face of silicon epitaxial layers 106, and sidewall is by family of crystal planes, and { 110} is formed.
After wet etching, the sidewall of silicon epitaxial layers 106 is etched and forms Σ shape.Can select and variously to wafer, there is optionally wet etching solution.Such as, Tetramethylammonium hydroxide (TMAH) can be used.
Then, in Σ shaped recesses 109 and 110, form SiGe112 by epitaxial growth, finally remove hard mask, to form structure as shown in Figure 1 G.
Similar as the SiGe of etching stop layer 105 to aforementioned formation.In Σ shape groove 109 and 110, SiGe is grown by growth technology.Such as, process gas can comprise SiH
4; GeH
4; HCl; BH
6; And H
2, wherein H
2gas flow rate can be 0.1slm to 50slm, the flow velocity of other gas can be 1sccm to 1000sccm, and reaction temperature is at 500-800 DEG C, and pressure holds in the palm at 5-50, but the invention is not restricted to these listed process gass and technological parameter.These technological parameters can be changed, the Ge content in adjustment SiGe alloy, thus change the stress intensity in silicon epitaxial layers.
In the above-described embodiments, the PMOS device of first area and the structure of second area device are all formed on etching barrier layer 105, keep apart with backing material.Therefore the substrate used in the present invention can be any material that can be used for producing the semiconductor devices, instead of only utilizes monocrystalline substrate.In addition, in an embodiment of the present invention, active area, the channel region of device are formed by epitaxial growth technology, compared with the technique directly formed on a silicon substrate with routine, the control of this technique to thickness is more accurate, along with the continuous reduction of transistor feature size, process advan of the present invention in forming the device more meeting design size and require, thus improves integrated circuits integral performance and stability.
In addition, in order to reduce the various defects (such as, dislocation) because not mating between etching barrier layer 105 with substrate 101 causes, in one embodiment, buffering area can be formed between substrate 101 and etching barrier layer 105.
In certain embodiments, better PMOS transistor performance can be provided and regular transistor can provide better NMOS performance, so use the transistor of two types to provide on a single substrate and only the transistor of a type be used for NMOS and compare better integral device performance with both PMOS transistor owing to forming the embedded SiGe of Σ shape in source region and drain region.
In addition, according to another embodiment of the invention, the above-mentioned method for forming the embedded SiGe of Σ shape is in the pmos devices used in nmos device and forms the embedded SiC of Σ shape.Similar to preceding method, first form Σ shape source region as shown in Figure 1 F drain recesses 109 and 110, then in source region drain recesses 109 and 110, fill SiC.Due to the patterned features of SiC, in Σ shape source region drain recesses 109 and 110, fill SiC, will cause producing tension stress in Si channel region, thus better nmos pass transistor performance is provided.
Fig. 2 illustrates the flow chart of the embedded SiGe of formation Σ shape according to an embodiment of the invention.
First, in step 201, substrate forms isolation structure.In step 202, etch described substrate, to remove the backing material between isolation structure, to form first area for PMOS and second area.Optionally, in step 203, substrate forms buffering area.In step 204, form etching stop layer.On buffering area, SiGe is grown as etching stop layer by epitaxial growth technology.In step 205, etching stop layer forms the first semiconductor layer.This first semiconductor layer can be silicon epitaxial layers.In step 206, form grid and side wall on the first semiconductor layer.In step 207, in first area, selective removal first semiconductor layer, only retains the part of the first semiconductor layer below described grid and side wall, to form source region and drain recesses.In step 208, in first area, to the remainder of the first semiconductor layer, there is crystal orientation optionally wet etching, to form Σ shape on the sidewall of described first semiconductor layer, thus form source region and the drain recesses of Σ shape.In step 209, by epitaxial growth technology, in the source region and drain recesses of Σ shape, grow SiGe.
Abovementioned steps 201-209 describes to be formed has the manufacture method of embedded SiGe as the PMOS transistor in source region and drain region.When by said method for the manufacture of when also comprising the integrated circuit of nmos pass transistor, can in the selective etch process of step 207, mask is formed in the region of nmos pass transistor, be immune in subsequent technique to make nmos pass transistor, then after step 209 completes, form mask in PMOS transistor region, then pair nmos transistor processes.
The manufacture NMOS provided according to embodiments of the invention and the method for PMOS transistor, by increasing etching stop layer, simplify and form the embedded SiGe manufacturing step of Σ shape, and improve the accuracy of manufacture of transistor, make the performance of transistor obtain larger lifting.
Give the foregoing description of embodiments of the invention for the purpose of illustration and description.Do not intend exhaustive or limit the invention to disclosed precise forms.This specification and claims comprise such as left and right, top, the end ... on ... under, top, bottom, first, second etc. term, these only should not be construed as restriction for the object described.Such as, the device-side (or active surface) indicating the term of relative upright position to refer to substrate or integrated circuit is the situation in this substrate " top " face; In fact substrate can be in any direction, and " top " side of substrate in the referential of standard land still can be dropped in the implication on term " top " lower than " end " side.Term as used in this " ... on " (comprising in the claims) do not indicate the ground floor on the second layer directly on the second layer and directly contact with the second layer, unless expressly stated so; Third layer or other structure can be had between the second layer on ground floor and ground floor.Can manufacture, use or transport the embodiment of device as herein described or goods on multiple position and direction.Those skilled in the relevant art can understand a lot of amendment according to above teaching and distortion is possible.Person of skill in the art will appreciate that various equivalent combinations and the replacement of each assembly shown in accompanying drawing.Therefore scope of the present invention is not limited by this detail specifications but be defined by the following claims.
The foregoing describe some embodiments of the present invention.But the present invention can be embodied as other concrete form and not deviate from its spirit or substantive characteristics.Described embodiment all should be considered to be only illustrative and nonrestrictive in all respects.Therefore, scope of the present invention by appended claims but not aforementioned description limit.Fall in the implication of the equivalents of claims and scope to change contain by the scope of claims.
Claims (13)
1. a manufacture method for semiconductor device, comprising:
Substrate forms isolation structure;
Etch described substrate, to remove the backing material between isolation structure;
Form etching stop layer;
Described etching stop layer is formed the first semiconductor layer;
Described first semiconductor layer forms grid and side wall;
First semiconductor layer described in selective removal, only retains the part of described first semiconductor layer below described grid and side wall, to form source region and drain recesses;
To the remainder of described first semiconductor layer, there is crystal orientation optionally wet etching, to form Σ shape on the sidewall of described first semiconductor layer.
2. the method for claim 1, is characterized in that, described substrate is selected from any one in following material: the semiconductor on monocrystalline silicon, monocrystalline silicon through doping, polycrystalline or sandwich construction, insulator, Ge, GaAs or InP.
3. the method for claim 1, is characterized in that, described etching stop layer is SiGe.
4. the method for claim 1, is characterized in that, described etching stop layer is carborundum.
5. the method for claim 1, is characterized in that, the thickness of described etching stop layer is in the scope of 5 dust to 9 dusts.
6. the method for claim 1, is characterized in that, described first semiconductor layer is the silicon epitaxial layers formed by epitaxial growth; The thickness of described silicon epitaxial layers is not less than 100 dusts.
7. method as claimed in claim 6, it is characterized in that, the thickness of described silicon epitaxial layers is in the scope of 300 dust to 800 dusts.
8. method as claimed in claim 6, is characterized in that, the end face of described silicon epitaxial layers by family of crystal planes 100} is formed, and sidewall by family of crystal planes 110} is formed, and described in have crystal orientation optionally wet etching stop at family of crystal planes { 111}.
9. the method for claim 1, is characterized in that, is also included in crystal orientation optionally after wet etching, in the source region and drain recesses of Σ shape, forms SiGe.
10. the method for claim 1, is characterized in that, is also included in crystal orientation optionally after wet etching, in the source region and drain recesses of Σ shape, forms SiC.
11. the method for claim 1, is characterized in that, are also included between described etching stop layer and described substrate and form buffering area.
12. the method for claim 1, is characterized in that, at least one step during the first semiconductor layer described in described selective removal comprises the following steps:
Deposition mask layer;
Mask layer on selective removal source region and drain region;
Utilize mask layer, by dry etching, described first semiconductor layer is etched, until till described etching stop layer.
13. 1 kinds of semiconductor device, comprise the structure manufactured by the method described in any one in claim 1 to 12.
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| US20120319166A1 (en) * | 2011-06-16 | 2012-12-20 | International Business Machines Corporation | Transistor with buried silicon germanium for improved proximity control and optimized recess shape |
| CN102842504A (en) * | 2011-06-20 | 2012-12-26 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device and manufacturing method thereof |
| CN103377932A (en) * | 2012-04-23 | 2013-10-30 | 中芯国际集成电路制造(上海)有限公司 | Pmos transistor and manufacturing method thereof |
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2014
- 2014-07-31 CN CN201410374245.0A patent/CN105321870A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20080265281A1 (en) * | 2005-05-10 | 2008-10-30 | International Business Machines Corporation | Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer |
| US20120319166A1 (en) * | 2011-06-16 | 2012-12-20 | International Business Machines Corporation | Transistor with buried silicon germanium for improved proximity control and optimized recess shape |
| CN102842504A (en) * | 2011-06-20 | 2012-12-26 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device and manufacturing method thereof |
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Application publication date: 20160210 |