CN105306987A - Device for controlling output code rate of TS stream interface - Google Patents

Device for controlling output code rate of TS stream interface Download PDF

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Publication number
CN105306987A
CN105306987A CN201510692402.7A CN201510692402A CN105306987A CN 105306987 A CN105306987 A CN 105306987A CN 201510692402 A CN201510692402 A CN 201510692402A CN 105306987 A CN105306987 A CN 105306987A
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output
stream
clock
input
bit rate
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CN201510692402.7A
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CN105306987B (en
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潘武聪
邓峰
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Guowei group (Shenzhen) Co., Ltd.
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Shenzhen State Micro Technology Co Ltd
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/41Structure of client; Structure of client peripherals
    • H04N21/418External card to be used in combination with the client device, e.g. for conditional access
    • H04N21/4181External card to be used in combination with the client device, e.g. for conditional access for conditional access
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/438Interfacing the downstream path of the transmission network originating from a server, e.g. retrieving encoded video stream packets from an IP network
    • H04N21/4385Multiplex stream processing, e.g. multiplex stream decrypting
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/442Monitoring of processes or resources, e.g. detecting the failure of a recording device, monitoring the downstream bandwidth, the number of times a movie has been viewed, the storage space available from the internal hard disk
    • H04N21/4424Monitoring of the internal components or processes of the client device, e.g. CPU or memory load, processing speed, timer, counter or percentage of the hard disk space used

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Databases & Information Systems (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

The invention discloses a device for controlling an output code rate of a TS stream interface. The device is arranged between TS stream input and output interfaces and comprises a TS stream receiving module, an input TS stream code rate monitoring module, an output TS stream clock generation module and a TS stream output control module, and the device receives a TS packet output by the TS stream output interface, forms a new data format of the TS packet, buffers within a preset delay time and outputs TS stream to the TS stream input interface according to a new TS stream output clock generated in the device. By adopting the device disclosed by the invention, CAM can control the output code rate of the TS stream interface, STB and other devices do not need to be provided with a large number buffer areas, and such problems between the STB and the CAM as transmission interruption, transmission jitter and the like are fully solved.

Description

A kind of device of control TS stream interface bit rate output
Technical field
The present invention relates to the control technology adopting the TS of MPEG2 standard to flow (TransportStream) stable transfer, particularly relate to CAM in Conditional Access of Digital Television (CA) system to export TS and flow to STB(SetTopBox/ Set Top Box) bit rate output control, and CAM(ConditionAccessModule/ Conditional Access Module/CAM card) realize PVR(PersonalVideoRecorder) and Timeshift(time shifting broadcasting) TS stream bit rate output control in new application.
Background technology
In digital television system, the synchronization mechanism of audio frequency and video requires that the clock stringent synchronization of encoder, the temporal information needed for decoder system are encoded in PCR (ProgramClockReference) and SCR (SystemClockReference) and pass through TS flow transmission.
Decoder buffer overflow is avoided to be the key of decoder normal decoder, because overflow can cause TS loss of data, cause decoder intactly cannot receive audio frequency and video TS bag, comprise the TS bag of PCR and SCR temporal information, decoder is caused completely not decode, there is flating or Huaping phenomenon, affect the normal display of digital TV terminal.
In the system that digital television condition receiver and card is separated, " non-full " state of the TS packet receive buffer of STB decoder does not have physical interface to output to CAM, and CAM can not export STB to the condition control TS of " non-full " bag.CAM must wrap constant through the delay of CAM by control TS, just can avoid the risk of the reception buffer zone overflow of STB decoder.
Under conventional implementation of the prior art, CAM inputs TS stream clock and drives TS bag to export as the mode exporting TS stream clock, in the constant situation of TS flow transmission code check, reduces the risk of transmission jitter preferably.In TS flow transmission code check rate non-constant situation, there is the possibility of transmission jitter in conventional implementation, and namely in code check sudden period accelerated, if CAM deals with improperly, STB exists the risk receiving overflow.
Under conventional implementation, CAM inputs TS stream clock and drives TS bag to export as the mode exporting TS stream clock, due to the hysteresis quality that CAM process TS wraps, STB suspends TS and flows the possibility of input clock when there is no TS flow transmission task, exist TS bag remain in CAM cannot export, the problem of part TS bag transmission jitter.
In the new application that CAM realizes PVR and time shifting broadcasting, the key of realization is: how to produce suitable TS stream output clock and export STB to drive TS to wrap; How to ensure that the delay of TS stream transmission procedure is fixed, avoid transmission jitter and receive overflow risk.
Therefore, the how device of a kind of control TS of development and Design stream interface bit rate output, has become one of technical barrier needing at present to solve.
Summary of the invention
The present invention, in order to solve the problem of above-mentioned prior art, proposes a kind of device of control TS stream interface bit rate output, and described device is arranged between the input of TS stream, output interface, comprising:
TS flows receiver module, flowing the TS bag of output interface output, recording each TS and wrapping the temporal information be buffered to completely in described device for receiving TS;
Input TS stream bit rate monitoring module, monitors that TS flows the TS stream bit rate clock of output interface output, extracts the average divide coefficient of TS stream bit rate clock relative to the system clock of described device;
Export TS and flow clock generating module, comprising the highest predeterminable divide ratio lower limit of output TS stream bit rate and the divide ratio higher limit of minimum output TS code check, flowing the range of code rates of output clock (MOCLK) for defining the inner TS produced; The average divide coefficient generation TS that described output TS stream clock generating module is extracted according to the divide ratio lower limit of the highest output TS stream bit rate preset or input TS stream bit rate monitoring module flows output clock;
TS flows output control module, comprise predeterminable fixed delay time, described TS flows output control module and controls after each TS wraps in and cushion with the fixed delay time preset in described device, and 188 byte content of being wrapped by TS export TS to the code check that described TS flows output clock and flow input interface.
This device can also arrange an input TS stream bit rate logging modle further, for recording the average divide coefficient of the TS stream bit rate that input TS stream bit rate monitoring module is extracted, when current average divide coefficient is less than the average divide coefficient recording storage, current average divide coefficient is replaced the average divide coefficient stored.
When the average divide coefficient of input TS stream bit rate logging modle record is in the scope of described lower limit and higher limit, described outputs TS flows clock generating module and carries out frequency division with average divide coefficient to described system clock, produces TS stream output clock;
When the average divide coefficient of input TS stream bit rate logging modle record is outside the scope of described lower limit and higher limit, described output TS flows clock generating module and carries out frequency division with the lower limit preset to described system clock, produces TS and flows output clock.
The TS stream receiver module of this device comprises the reference time counter unit for calibrating described temporal information further, this reference time counter unit adopts many bit cycle counter, the counting clock of described counter is described system clock, and counting precision reaches nanosecond.Also comprise TS handbag tail monitor unit, for monitoring that TS wraps the rising edge that TS corresponding to the bag tail after from original position flows the TS stream bit rate clock of input interface input, and load the real-time counting value of reference time counter unit output in the bag tail moment, obtain the temporal information being buffered to described device completely of current input TS bag.TS flows receiver module and comprises TS bag data record unit, in the byte content that bag tail moment buffer-stored TS wraps.
TS stream output control module also comprises TS and flows output time comparing unit, according to the fixed delay time preset, calculates the output initial time that the TS after each buffering wraps, and exports enabling signal to described TS stream output control module transmission TS bag.
The frequency of the system clock that this device adopts reaches 100,000,000 levels per second, cushions the elapsed time clock of time information as TS bag, monitors the divided reference clock of the sampling clock inputting TS stream bit rate signal (MICLK), inner TS stream output clock (MOCLK) produced.
The input that the TS stream that this device is installed inputs, output interface can flow relative to CAM transmission TS for Set Top Box, ahb bus interface, USB interface, Internet interface, output interface.
Compared with prior art, the present invention has following beneficial effect:
1. the present invention has fully taken into account in digital television conditional access system, CAM and STB interface compatibility sex chromosome mosaicism.Because STB is in transmission TS packet procedures, STB does not temporarily need to transmit TS bag toward CAM for a certain reason, TS is flowed input clock simultaneously and stops.When CAM adopts TS stream input clock to flow the implementation of output clock as TS, in STB stopping time clock to the process of recovered clock, there is TS bag transmission jitter problem.The present invention adopts the inner TS of generation to flow the mode of output clock, making TS wrap output relies on the inner clock produced to drive completely, the TS not relying on outside STB flows input clock, thus avoids stopping inlet flow clock case lower part TS bag transmission jitter problem at STB.
2. the present invention considers in TS flow transmission between STB and CAM, if input TS bag adopts different scrambling type, the descrambling difference consuming time that CAM wraps different scrambling attribute TS, after CAM process, the TS bag of different attribute is not fixed from the delay be input between output, there is transmission jitter problem.The present invention supports that each input TS wraps the function of configurable fixed delay output, ensures that the TS being transferred to STB after each input TS wraps in the identical residence time flows input interface, ensures that each TS bag is fixed through the transmission delay of CAM.This implementation does not require that STB decoder offers jumbo buffering area, and CAM adopts " mode pushed away " to export the TS bag after process to STB, avoids STB reception buffer zone to occur the risk of overflow or underflow preferably.
3. the present invention considers that CAM is realizing PVR or Timeshift(time shifting broadcasting) function time, the determination of the initial time that each TS bag exports, TS flow the problem how output clock produces.Invention defines the data format (comprising " 188 byte content " and " corresponding TS bag cushions the temporal information in moment completely ") that a kind of new TS wraps.Realizing the broadcasting stage, extracting an average divide coefficient relative to system clock according to the difference cushioning the temporal information in moment completely that adjacent TS wraps, obtaining control TS after carrying out frequency division with system clock according to the divide ratio extracted and flow the clock exported; The temporal information cushioning the moment completely adopting each TS to wrap relatively determines its initial time exported.Based on above-mentioned TS bag data format, CAM supports the TS stream source of process: except supporting typical STB, and also expansion supports that the TS in the sources such as ahb bus interface, USB interface, Internet interface inputs data.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention.
Embodiment
Below in conjunction with drawings and Examples, describe in detail the present invention as a module of CAM, be arranged on STB10(Set Top Box) relative to CMA transmit TS stream input interface and output interface between operation principle and process.
As shown in Figure 1, the device 20 of control TS stream interface bit rate output of the present invention, monitor the TS stream bit rate clock (MICLK) that STB10 output interface exports, extract the minimum value of TS stream bit rate clock (MICLK) relative to the MICLK divide ratio of system clock (CLK_sys), produce inner TS after adopting the minimum value of MICLK average divide coefficient to carry out frequency division to system clock (CLK_sys) and flow output clock (MOCLK), export the input interface of STB after the TS controlling to cushion wraps in the fixed delay time that can pre-set to, make TS flow back into STB.
System clock (CLK_sys) in this device 20 is a high frequency clock, its frequency is that 100M/S(100,000,000 is per second) rank, wrap the elapsed time clock of buffer time information as record TS, monitor the divided reference clock of the sampling clock inputting TS stream bit rate signal (MICLK), the inner TS stream interface output clock (MOCLK) produced.
This device comprises 5 modules, is respectively TS and flows receiver module 201, and input TS stream bit rate monitoring module 202, TS flows output control module 203, inputs TS stream bit rate logging modle 204 and exports TS and flow clock generating module 205.
TS flows the TS stream that output interface that receiver module 201 is used for receiving STB exports, and each TS bag flowed by TS is buffered in this device, and is after the data format of new TS bag by each TS package definition, flows output control module 203 export by TS.
TS flows receiver module 201 and specifically contains again three submodules, is respectively reference time counter unit 2011, TS handbag tail monitor unit 2012, TS bag data record unit 2013.
Reference time counter unit 2011 is the cycle counters of bit more than, real-time counting value (Counter_reference) the linear expression temporal information of counter.The counting clock of this counter is the system clock (CLK_sys) of this device, and counting precision reaches ns(nanosecond) rank, the reference time of degree of precision is provided.
TS handbag tail monitor unit 2012 monitors the rising edge of STB input TS stream bit rate clock (MICLK) signal that TS handbag tail (the 188th byte) is corresponding.In effective (MIVAL=1) situation of the byte content of TS bag, TS handbag tail monitor unit 2012 adopts the synchronous TS stream bit rate clock MICLK of system clock (CLK_sys) to obtain internal signal MICLK_ff, namely adopt system clock (CLK_sys) to do the process of typical digital circuit cross clock domain to " MICLK " signal, extract the rising edge pulse (MICLK_ff_rise_edge_x) of each internal signal MICLK_ff.TS handbag tail monitor unit 2012 monitors that each TS wraps the rising edge pulse (MICLK_ff_rise_edge_188) of the 188th MICLK_ff signal after from original position (MISTART=1).TS handbag tail monitor unit 2012 loads the real-time counting value of reference time counter unit 2011 output in the TS bag tail moment (MICLK_ff_rise_edge_188=1), obtains the temporal information being buffered to this device completely of current input TS bag.
TS bag data record unit 2013 record enters this device TS and wraps 188 byte content.With TS handbag tail monitor unit 2012 to realize principle similar, TS bag data record unit 2013 wraps sampling instant (MICLK_ff_rise_edge_x=1 corresponding to 188 byte content at TS, x=[1:188]), the TS packet byte content (MDI [7:0]) of the TS of STB stream output interface is buffered to the memory space in TS bag data record unit 2013, stores TS in the bag tail moment and wrap the temporal information byte content cushioned completely.Two separate FIFO(FirstInputFirstOutput are adopted in TS bag data record unit 2013) memory stores the temporal information byte content cushioning the moment completely of TS bag and 188 byte content of TS bag respectively.
By above-mentioned three unit, TS flows receiver module 201 can wrap in this device the data format being defined as novel TS bag by the TS that STB exports, comprise in the data format of namely novel TS bag " 188 byte content " and " corresponding TS bag cushions the temporal information in moment completely ", and then flow according to new TS the TS content that output clock exports 188 bytes in novel TS bag, do not comprise the byte content such as temporal information.
Input TS stream bit rate monitoring module 202 comprises the divide ratio configuration register of input TS stream bit rate clock sampling, represents the number of the effective TS byte content of accumulative continuous adjacent for configuration parameter N, N.In the effective situation of index signal of the TS byte content of input, input TS stream bit rate monitoring module 202 monitors that the accumulative adjacent number of the TS stream output interface of STB is the span time of effective TS byte content of N, extract in this span time and comprise system clock (CLK_sys) number statistical value M, the result that M/N is divided exactly is the MICLK average divide coefficient of average bit rate relative to system clock (CLK_sys) of current input TS bag.Above-mentioned index signal comprises MICLK/MOSTRT/MOVAL etc.
With TS handbag tail monitor unit 2012 and TS bag data record unit 2013 to realize principle similar, the adjacent number of continuous superposition is N(N=2/4/8/16/32/64/128) corresponding MICLK_ff_rise_edge_x(x=[1:2]/[1:4]/[1:8]/[1:16]/[1:32]/[1:64]/[1:128] of effective TS byte content) span time (Delta_Tn), Delta_Tn correspondence system clock (CLK_sys) number aggregate-value is M, M/N divides exactly the MICLK average divide coefficient that operation obtains relative to system clock (CLK_sys).
The MICLK average divide coefficient of the current TS bag newly monitored compares with the historical record value in input TS stream bit rate logging modle 204 by input TS stream bit rate logging modle 204, if the MICLK average divide coefficient of the TS bag newly monitored is less than the historical record value in input TS stream bit rate logging modle 204, the MICLK average divide coefficient of the TS bag then newly monitored is updated to input TS stream bit rate logging modle 204, covers historical record value.
Export TS stream clock generating module 205 and comprise two divide ratio threshold values can carrying out arranging: the highest divide ratio lower limit of output TS code check and the divide ratio higher limit of minimum output TS code check.These two threshold value demand fulfillment " the corresponding divide ratio lower limit of the highest output frequency " are less than " the corresponding divide ratio higher limit of minimum output frequency ".Wherein the divide ratio lower limit of the highest output TS code check proposes for " the MICLK code check that certain type STB interface support is the highest " or " the MICLK maximum transmission bandwidth that certain standard criterion specifies ".Before exporting effective MICLK average divide coefficient for the input TS stream bit rate monitoring module 202 of this device, be supplied to and export TS and flow the initial divide ratio of clock generating module 205, produce initialized MOCLK clock.
Export TS flow clock generating module 205 according to the highest divide ratio lower limit of output TS code check, the divide ratio higher limit of minimum output TS code check and input TS stream bit rate logging modle 204 record the MICLK average divide coefficient TS that produces internal control flow output clock (MOCLK).If the MICLK average divide coefficient of input TS stream bit rate logging modle 204 is in the interval range of two threshold values, system clock (CLK_sys) frequency division parameter that then in TS code stream clock generating module 205, MOCLK is corresponding adopts " the MICLK average divide coefficient that input TS stream bit rate logging modle 204 records ", otherwise adopts the divide ratio lower limit of the highest output TS code check.
Export TS and flow the input TS code check rate monotonic incremental stages of clock generating module 205 at STB, it is monotone decreasing that input TS stream bit rate monitoring module 202 extracts MICLK average divide coefficient, the interval range that if the MICLK average divide coefficient of TS stream bit rate logging modle 204 record meets " two divide ratio threshold values (the highest divide ratio lower limit of output TS code check, the divide ratio higher limit of minimum output TS code check) ", then the TS stream interface output clock (MOCLK) using system clock (CLK_sys) frequency division to obtain is in monotonically increasing state.
The code check exporting the input TS stream clock of TS stream clock generating module 205 real time monitoring STB increases progressively state, upgrade in time divide ratio thus improve the code check of the inner TS stream interface output clock (MOCLK) produced, ensure that the code check that the inner output TS produced flows clock (MOCLK) is monotonic increase or hold mode (can not taper off state), avoid the TS stream through this device to export the risk of blocking.
TS flows output control module 203 and comprises configurable fixed delay parameter (Delay_cfg), wraps in the residence time of this device for controlling each TS.The base unit postponed is system clock (CLK_sys) cycle.Namely, after fixed delay parameter configuration, each TS residence time wrapped in this device is Delay_Time (Delay_Time=system clock CLK_sys cycle × Delay_cfg).
TS flows output control module 203 and comprises TS stream output time comparing unit 2031, for judging the output initial time of this device each buffering TS bag.The record value cushioning the moment completely that certain TS wraps in TS bag data record unit 2013 is Counter_a, TS flows the record value Counter_a cushioning the moment completely that output time comparing unit 2031 reads this TS bag from TS bag data record unit 2013, (Counter_b=Counter_a-Delay_cfg) formulae discovery is adopted to obtain the output initial time value Counter_b of this TS bag, if Counter_b equals current reference time counter unit 2011 real-time counting output valve (Counter_reference), i.e. equation (Counter_b=Counter_reference) moment of setting up, TS flows the output enabling signal that output time comparing unit (2031) produces corresponding TS bag.
The TS bag that TS stream output control module 203 controls to be buffered in this device exports STB to.The output enabling signal of each TS bag that output time comparing unit 2031 exports is flowed according to TS, to export the code check that TS flows the TS stream interface output clock (MOCLK) that clock generating module 205 produces, from TS bag data record unit 2013, read the 188 byte content information that corresponding TS wraps, the TS exporting STB successively to flows input interface.
Except the object lesson of above-mentioned STB, this device can also process the following mutual TS of TS flow data that carries out with CAM card and flow and originate, and specifically comprises and supports that the TS in the sources such as ahb bus interface, USB interface, Internet interface inputs data etc.
Should be understood that, the above-mentioned description for specific embodiment is comparatively detailed, and therefore can not think the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.

Claims (10)

1. a device for control TS stream interface bit rate output, is characterized in that, described device is arranged between the input of TS stream, output interface, comprising:
TS flows receiver module (201), flowing the TS bag of output interface output, recording each TS and wrapping the temporal information be buffered to completely in described device for receiving TS;
Input TS stream bit rate monitoring module (202), monitors that TS flows the TS stream bit rate clock of output interface output, extracts the average divide coefficient of TS stream bit rate clock relative to the system clock of described device;
Export TS and flow clock generating module (205), comprise the highest predeterminable divide ratio lower limit of output TS stream bit rate and the divide ratio higher limit of minimum output TS code check; The average divide coefficient generation TS that described output TS stream clock generating module is extracted according to the divide ratio lower limit of the highest output TS stream bit rate preset or input TS stream bit rate monitoring module flows output clock;
TS flows output control module (203), comprise predeterminable fixed delay time, described TS flows output control module and controls after each TS wraps in and cushion with the fixed delay time preset in described device, and the code check flowing output clock with described TS exports TS to and flows input interface.
2. device as claimed in claim 1, it is characterized in that, described device also comprises input TS stream bit rate logging modle (204), for recording the average divide coefficient of the TS stream bit rate that input TS stream bit rate monitoring module (202) is extracted, when current average divide coefficient is less than the average divide coefficient recording storage, current average divide coefficient is replaced the average divide coefficient stored.
3. device as claimed in claim 2, it is characterized in that, when input TS stream bit rate logging modle (204) the average divide coefficient that records is in the scope of described lower limit and higher limit, described output TS flows clock generating module and carries out frequency division with average divide coefficient to described system clock, produces TS and flows output clock;
When input TS stream bit rate logging modle (204) the average divide coefficient that records is outside the scope of described lower limit and higher limit, described output TS flows clock generating module and carries out frequency division with the lower limit preset to described system clock, produces TS and flows output clock.
4. device as claimed in claim 1, it is characterized in that, the frequency of described system clock reaches 100,000,000 levels per second.
5. device as claimed in claim 3, is characterized in that, described TS stream receiver module (201) comprises the reference time counter unit (2011) for calibrating described temporal information.
6. device as claimed in claim 5, it is characterized in that, described reference time counter unit adopts many bit cycle counter, and the counting clock of described counter is described system clock, and counting precision reaches nanosecond.
7. device as claimed in claim 5, it is characterized in that, described TS flows receiver module (201) and comprises TS handbag tail monitor unit (2012), for monitoring that TS wraps the rising edge that TS corresponding to the bag tail after from original position flows the TS stream bit rate clock of input interface input, and in the real-time counting value that bag tail moment loading reference time counter unit (2011) exports, obtain the temporal information being buffered to described device completely of current input TS bag.
8. device as claimed in claim 1, it is characterized in that, described TS flows receiver module (201) and comprises TS bag data record unit (2013), between packet header to bag tail moment, 188 byte content of buffer-stored TS bag, store described TS in the bag tail moment and wrap the temporal information byte content cushioned completely.
9. device as claimed in claim 1, it is characterized in that, described TS flows output control module (203) and comprises TS stream output time comparing unit (2031), according to the fixed delay time preset, calculate the output initial time that the TS after each buffering wraps, and flow output control module (203) transmission TS bag output enabling signal to described TS.
10. the device as described in claim 1 to 9 any one, is characterized in that, the input of described TS stream, output interface are Set Top Box, ahb bus interface, USB interface, Internet interface transmit TS stream relative to CAM input, output interface.
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