CN105306404A - Device and method for inhibiting signal peak-to-average ratio based on FPGA chip - Google Patents
Device and method for inhibiting signal peak-to-average ratio based on FPGA chip Download PDFInfo
- Publication number
- CN105306404A CN105306404A CN201510736843.2A CN201510736843A CN105306404A CN 105306404 A CN105306404 A CN 105306404A CN 201510736843 A CN201510736843 A CN 201510736843A CN 105306404 A CN105306404 A CN 105306404A
- Authority
- CN
- China
- Prior art keywords
- module
- peak
- rom
- slm
- sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2614—Peak power aspects
- H04L27/2623—Reduction thereof by clipping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
The invention belongs to the field of high-speed wireless communication, and discloses a device and a method for inhibiting a signal peak-to-average ratio based on an FPGA chip. The device and the method are used for reducing the problem of a relatively high peak-to-average ratio in a high-speed wireless communication system. The device comprises a clock module, an ROM module electrically connected with the clock module, a ROM control module electrically connected with the ROM module, a selective mapping SLM module electrically connected with the clock module and the ROM module respectively, and an amplitude limiting module electrically connected with the SLM module; the clock module is used for providing a working clock of the chip; the ROM module is used for storing OFDM data; the ROM control module is used for controlling a working time sequence of the ROM module and an address of the ROM module for outputting the OFDM data; the SLM module is used for carrying out selective mapping calculation on the OFDM data stored in the ROM module and outputting a calculation result sequence; and the amplitude limiting module is used for carrying out peak clipping operation on the calculation result sequence output by the SLM module.
Description
Technical field
The present invention relates to high-speed radiocommunication field, particularly relate to a kind of signal peak-to-average ratio restraining device based on fpga chip and method, for reducing the higher peak faced in high-speed radiocommunication system all than problem.
Background technology
Along with large scale integrated circuit develop rapidly, use the modulation /demodulation of hardware implementing OFDM (OrthogonalFrequencyDivisionMultiplexing) signal to become relatively easy, but high-speed radiocommunication system face higher peak all than problem also more and more outstanding.
Summary of the invention
For the problems referred to above, the object of the present invention is to provide a kind of signal peak-to-average ratio restraining device based on fpga chip and method, the peak-to-average force ratio rejection ability of high-speed radiocommunication system can be improved, reduce hard-wired complexity simultaneously.
For achieving the above object, embodiments of the invention adopt following technical scheme to be achieved.
Technical scheme one:
A kind of signal peak-to-average ratio restraining device based on fpga chip, for carrying out peak-to-average force ratio suppression to the OFDM data in wireless communication system, described device at least comprises: clock module, the ROM module be electrically connected with described clock module, the ROM control module be electrically connected with described ROM module, the selected mapping method SLM module be electrically connected respectively with described clock module and described ROM module and the clipping module be electrically connected with described SLM module;
Wherein, described clock module, for providing work clock;
Described ROM module, for storing described OFDM data;
Described ROM control module, for the address of the work schedule and described ROM module output OFDM data that control described ROM module;
Described SLM module, for carrying out selected mapping method calculating to the OFDM data stored in described ROM module and exporting result of calculation sequence;
Described clipping module, carries out peak clipping operation for the result of calculation sequence exported described SLM module.
The feature of technical scheme one and being further improved to:
(1) described clock module, for adopting phase-locked loop in fpga chip as independently clock, and the input clock of described clock module is provided by external crystal-controlled oscillation, and the output clock of described clock module is as work clock.
(2) described ROM module, for storing real part and the imaginary part of described OFDM data respectively.
(3) described SLM module, for described OFDM data is carried out base band mapping, obtains M discrete frequency domain data sequence;
Described SLM module, also for obtaining M random sequence, and carries out dot product operation by M discrete frequency domain data sequence described in M random sequence and a described M discrete frequency domain data sequence M random sequence, M the result sequence obtained;
Described SLM module, also for described M result sequence is carried out inverse Fourier transform, obtains M time domain sequences;
Described SLM module, also for calculating the peak-to-average force ratio of a described M time domain sequences respectively, selects the time domain sequences obtaining having minimum peak-to-average force ratio to export clipping module to.
(4) described SLM module comprises SLM_control submodule, SLM_ROM submodule, multiplier, calculating sub module;
Wherein, described SLM_control submodule, for the work schedule of control SLM module;
Described SLM_ROM submodule, for storing real part and the imaginary part of a described M random sequence;
Described calculating sub module, for described OFDM data is carried out base band mapping, obtains M discrete frequency domain data sequence;
Described multiplier, operates for described M discrete frequency domain data sequence and M random sequence are carried out dot product M the result sequence obtained;
Described calculating sub module, also for described M result sequence is carried out inverse Fourier transform, obtains M time domain sequences, calculates the peak-to-average force ratio of a described M time domain sequences respectively, selects to obtain the time domain sequences with minimum peak-to-average force ratio.
(5) work clock of described ROM module and ROM control module is provided by the phase-locked loop of fpga chip.
(6) described clipping module, carries out peak clipping operation for the result of calculation sequence exported described SLM module, specifically comprises:
Described clipping module, for setting peak clipping threshold value, and in the result of calculation sequence of described SLM module output, the amplitude modulus value of each discrete point exceedes described peak clipping threshold value, then the amplitude of described each discrete point is set to described peak clipping threshold value.
Technical scheme two:
Based on a signal peak-to-average ratio suppressing method for fpga chip, described method comprises:
Obtain OFDM data, and described OFDM data is stored;
Described OFDM data is carried out base band mapping, obtains M discrete frequency domain data sequence;
Produce M random sequence, a described M random sequence and described M discrete frequency domain data sequence are carried out dot product, obtains M result sequence;
Inverse Fourier transform is carried out to described M result sequence, obtains M time domain sequences;
Calculate the peak-to-average force ratio of a described M time domain sequences respectively, select the time domain sequences with minimum peak-to-average force ratio;
Peak clipping operation is carried out to the described time domain sequences with minimum peak-to-average force ratio, obtains the time domain sequences suppressed through peak-to-average force ratio.
The feature of technical scheme two and being further improved to:
(1) described peak clipping operation is carried out to the described time domain sequences with minimum peak-to-average force ratio, specifically comprises:
Setting peak clipping threshold value, and the amplitude modulus value described in working as with each discrete point in the time domain sequences of minimum peak-to-average force ratio exceedes described peak clipping threshold value, then the amplitude of described discrete point is set to described peak clipping threshold value.
A kind of signal peak-to-average ratio restraining device based on fpga chip disclosed by the invention, utilization amplitude limit, SLM (SelectiveMapping, selected mapping method) integrated processes carry out peak-to-average force ratio suppression; This chip design comprises clock module, ROM module and ROM control module, clipping module, SLM module.After have employed technical scheme disclosed in this invention, the signal of high-speed transfer carries out peak-to-average force ratio through this chip and suppresses process, obtains higher peak-to-average force ratio rejection ability, and reduces hard-wired complexity.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
The structural representation of a kind of signal peak-to-average ratio restraining device based on fpga chip that Fig. 1 provides for the embodiment of the present invention;
Amplitude limit, the SLM integrated processes schematic diagram of a kind of signal peak-to-average ratio restraining device based on fpga chip that Fig. 2 provides for the embodiment of the present invention;
The hardware implementing schematic diagram of a kind of signal peak-to-average ratio restraining device based on fpga chip that Fig. 3 provides for the embodiment of the present invention;
The clock module schematic diagram of a kind of signal peak-to-average ratio restraining device based on fpga chip that Fig. 4 provides for the embodiment of the present invention;
The ROM module of a kind of signal peak-to-average ratio restraining device based on fpga chip that Fig. 5 provides for the embodiment of the present invention and ROM control module schematic diagram;
The SLM module diagram of a kind of signal peak-to-average ratio restraining device based on fpga chip that Fig. 6 provides for the embodiment of the present invention;
The clipping module schematic diagram of a kind of signal peak-to-average ratio restraining device based on fpga chip that Fig. 7 provides for the embodiment of the present invention;
The schematic flow sheet of a kind of signal peak-to-average ratio suppressing method based on fpga chip that Fig. 8 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of signal peak-to-average ratio restraining device based on fpga chip, described device is used for carrying out peak-to-average force ratio suppression to the OFDM data in wireless communication system, as shown in Figure 1, described device at least comprises: clock module 1, the ROM module 2 be electrically connected with described clock module 1, the ROM control module 3 be electrically connected with described ROM module 2, the selected mapping method SLM module 4 be electrically connected respectively with described clock module 1 and described ROM module 2 and the clipping module 5 be electrically connected with described SLM module 4.
Wherein, described clock module 1, for providing work clock.
Described ROM module 2, for storing described OFDM data.
Described ROM control module 3, for the address of the work schedule and described ROM module output OFDM data that control described ROM module 2.
Described SLM module 4, for carrying out the calculating of selected mapping method to the OFDM data stored in described ROM module 2 and export result of calculation sequence.
Described clipping module 5, carries out peak clipping operation for the result of calculation sequence exported described SLM module 4.
Described clock module 1, for adopting phase-locked loop in FPGA as independently clock, and the input clock of described clock module 1 is provided by external crystal-controlled oscillation, and the output clock of described clock module 1 is as the work clock of described chip.
Described ROM module 2, for storing real part and the imaginary part of described OFDM data respectively.
Described SLM module 4, M discrete frequency domain data sequence is obtained for described OFDM data being carried out base band mapping, and described M discrete frequency domain data sequence and M random sequence are carried out dot product operate M the result sequence obtained, described M result sequence is carried out inverse Fourier transform and obtains M time domain sequences, calculate the peak-to-average force ratio of a described M time domain sequences respectively, select the time domain sequences obtaining having minimum peak-to-average force ratio to export clipping module to.
Concrete, described SLM module comprises SLM_control submodule, SLM_ROM submodule, multiplier, calculating sub module.
Wherein, described SLM_control submodule, for the work schedule of control SLM module.
Described SLM_ROM submodule, for storing real part and the imaginary part of a described M random sequence.
Described calculating sub module, obtains each discrete frequency domain data sequence of M for described OFDM data being carried out base band mapping.
Described multiplier, operates for described M discrete frequency domain data sequence and M random sequence are carried out dot product M the result sequence obtained.
Described calculating sub module, also obtains M time domain sequences for described M result sequence is carried out inverse Fourier transform, calculates the peak-to-average force ratio of a described M time domain sequences respectively, selects to obtain the time domain sequences with minimum peak-to-average force ratio.
The work clock of described ROM module and ROM control module is provided by the phase-locked loop of FPGA framework.
Described clipping module, result of calculation sequence for exporting described SLM module is carried out peak clipping operation and is specifically comprised: setting peak clipping threshold value, when in the result of calculation sequence that described SLM module exports, the amplitude modulus value of each discrete point exceedes described peak clipping threshold value, then the amplitude of described each discrete point is set to described peak clipping threshold value, ensures the phase invariant of each discrete point simultaneously.
Further, be illustrated in figure 2 a kind of signal peak-to-average ratio restraining device based on fpga chip that the embodiment of the present invention provides, employing amplitude limit, SLM integrated processes carry out the schematic flow sheet of peak-to-average force ratio suppression.
Concrete, the discrete frequency domain data sequence (F after first initial data base band maps by transmitting terminal
(1), F
(2)..., F
(M)) and random sequence (P
(1), P
(2)..., P
(M)) carry out dot product operation, wherein M is the number of random sequence, one group that dot product is obtained M sequence is carried out inverse Fourier transform IFFT and is transformed to time domain, and the peak-to-average force ratio of the random sequence finally obtained is calculated according to SLM method, then select and there is minimum peak-to-average force ratio sequence, then the sequence obtained is passed through clipping module.
Further, be illustrated in figure 3 the hardware implementing schematic diagram of a kind of signal peak-to-average ratio restraining device based on fpga chip that the embodiment of the present invention provides, the OFDM symbol of input is stored in ROM, obtains higher peak-to-average force ratio rejection ability through SLM module and clipping module process.
Further, be illustrated in figure 4 the schematic diagram of the clock module 1 that the embodiment of the present invention provides, phase-locked loop pll (PhaseLockedLoop) the conduct independently clock module of FPGA, input clock is provided by external crystal-controlled oscillation, and output clock is as the work clock of system.
Be illustrated in figure 5 the schematic diagram of ROM module 2 that the embodiment of the present invention provides and ROM control module 3, ROM module, as the data source of method for suppressing peak to average ratio, for depositing OFDM symbol, comprises real part and the imaginary part of OFDM symbol; ROM control module carries out work as the address of ROM module for control ROM module.Wherein, the work clock of ROM and ROM control module is provided by phase-locked loop.
Be illustrated in figure 6 the schematic diagram of the SLM module 4 that the embodiment of the present invention provides, wherein SLM_control is responsible for Control timing sequence; SLM_ROM is used for depositing real part and the imaginary part of random sequence; Multiplier is used for random sequence and is multiplied with the output data of ROM module; Computing module is responsible for the peak-to-average force ratio of computed information, and data are transformed into time domain by the IP kernel of intrinsic call IFFT, and calculate the modulus value of signal, the data selecting peak-to-average force ratio less carry out peak clipping operation.
Be illustrated in figure 7 the schematic diagram of the clipping module 5 that the embodiment of the present invention provides, comprise setting thresholding, and the data through SLM resume module are carried out interative computation, after signal peak clipping, calculate modulus value, complete peak-to-average force ratio and suppress operation.
A kind of signal peak-to-average ratio restraining device based on fpga chip disclosed by the invention, utilization amplitude limit, SLM (SelectiveMapping, selected mapping method) integrated processes carry out peak-to-average force ratio suppression; This chip design comprises clock module, ROM and ROM control module, clipping module, SLM module.After have employed technical scheme disclosed in this invention, the signal of high-speed transfer carries out peak-to-average force ratio through this chip and suppresses process, obtains higher peak-to-average force ratio rejection ability, and reduces hard-wired complexity.
The embodiment of the present invention also provides a kind of signal peak-to-average ratio suppressing method based on fpga chip, as shown in Figure 8, is the schematic flow sheet of the method, comprises:
Step 1, obtains OFDM data, and described OFDM data is stored.
Wherein said OFDM data is stored in ROM module.The work schedule of described ROM module and the address of described ROM module output OFDM data are controlled by described ROM control module.The work clock of described ROM module and ROM control module is provided by the phase-locked loop of fpga chip.
Step 2, carries out base band mapping by described OFDM data, obtains M discrete frequency domain data sequence.
Step 3, produces M random sequence, a described M random sequence and described M discrete frequency domain data sequence is carried out dot product, obtains M result sequence.
Step 4, carries out inverse Fourier transform to described M result sequence, obtains M time domain sequences.
Step 5, calculates the peak-to-average force ratio of a described M time domain sequences respectively, selects the time domain sequences with minimum peak-to-average force ratio.
Step 6, carries out peak clipping operation to the described time domain sequences with minimum peak-to-average force ratio, obtains the time domain sequences suppressed through peak-to-average force ratio.
Described peak clipping operation is carried out to the described time domain sequences with minimum peak-to-average force ratio, specifically comprises:
Setting peak clipping threshold value, and the amplitude modulus value described in working as with each discrete point in the time domain sequences of minimum peak-to-average force ratio exceedes described peak clipping threshold value, then the amplitude of described discrete point is set to described peak clipping threshold value.
One of ordinary skill in the art will appreciate that: all or part of step realizing said method embodiment can have been come by the hardware that program command is relevant, aforesaid program can be stored in a computer read/write memory medium, this program, when performing, performs the step comprising said method embodiment; And aforesaid storage medium comprises: ROM, RAM, magnetic disc or CD etc. various can be program code stored medium.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (9)
1. the signal peak-to-average ratio restraining device based on fpga chip, for carrying out peak-to-average force ratio suppression to the OFDM data in wireless communication system, it is characterized in that, described device at least comprises: clock module, the ROM module be electrically connected with described clock module, the ROM control module be electrically connected with described ROM module, the selected mapping method SLM module be electrically connected respectively with described clock module and described ROM module and the clipping module be electrically connected with described SLM module;
Wherein, described clock module, for providing work clock;
Described ROM module, for storing described OFDM data;
Described ROM control module, for the address of the work schedule and described ROM module output OFDM data that control described ROM module;
Described SLM module, for carrying out selected mapping method calculating to the OFDM data stored in described ROM module and exporting result of calculation sequence;
Described clipping module, carries out peak clipping operation for the result of calculation sequence exported described SLM module.
2. a kind of signal peak-to-average ratio restraining device based on fpga chip according to claim 1, is characterized in that,
Described clock module, for adopting phase-locked loop in fpga chip as independently clock, and the input clock of described clock module is provided by external crystal-controlled oscillation, and the output clock of described clock module is as work clock.
3. a kind of signal peak-to-average ratio restraining device based on fpga chip according to claim 1, is characterized in that,
Described ROM module, for storing real part and the imaginary part of described OFDM data respectively.
4. a kind of signal peak-to-average ratio restraining device based on fpga chip according to claim 1, is characterized in that,
Described SLM module, for described OFDM data is carried out base band mapping, obtains M discrete frequency domain data sequence;
Described SLM module, also for obtaining M random sequence, and carries out dot product operation by M random sequence and described M discrete frequency domain data sequence, M the result sequence obtained;
Described SLM module, also for described M result sequence is carried out inverse Fourier transform, obtains M time domain sequences;
Described SLM module, also for calculating the peak-to-average force ratio of a described M time domain sequences respectively, selects the time domain sequences obtaining having minimum peak-to-average force ratio to export clipping module to.
5. a kind of signal peak-to-average ratio restraining device based on fpga chip according to claim 4, it is characterized in that, described SLM module comprises SLM_control submodule, SLM_ROM submodule, multiplier, calculating sub module;
Wherein, described SLM_control submodule, for the work schedule of control SLM module;
Described SLM_ROM submodule, for storing real part and the imaginary part of a described M random sequence;
Described calculating sub module, for described OFDM data is carried out base band mapping, obtains M discrete frequency domain data sequence;
Described multiplier, operates for described M discrete frequency domain data sequence and M random sequence are carried out dot product M the result sequence obtained;
Described calculating sub module, also for described M result sequence is carried out inverse Fourier transform, obtains M time domain sequences, calculates the peak-to-average force ratio of a described M time domain sequences respectively, selects to obtain the time domain sequences with minimum peak-to-average force ratio.
6. a kind of signal peak-to-average ratio restraining device based on fpga chip according to claim 1, it is characterized in that, the work clock of described ROM module and ROM control module is provided by the phase-locked loop of fpga chip.
7. a kind of signal peak-to-average ratio restraining device based on fpga chip according to claim 1, is characterized in that, described clipping module, carries out peak clipping operation, specifically comprise for the result of calculation sequence exported described SLM module:
Described clipping module, for setting peak clipping threshold value, and when the amplitude modulus value with each discrete point in the time domain sequences of minimum peak-to-average force ratio of described SLM module output exceedes described peak clipping threshold value, then the amplitude of described each discrete point is set to described peak clipping threshold value.
8. based on a signal peak-to-average ratio suppressing method for fpga chip, for carrying out peak-to-average force ratio suppression to the OFDM data in wireless communication system, it is characterized in that, described method comprises:
Obtain OFDM data, and described OFDM data is stored;
Described OFDM data is carried out base band mapping, obtains M discrete frequency domain data sequence;
Produce M random sequence, a described M random sequence and described M discrete frequency domain data sequence are carried out dot product, obtains M result sequence;
Inverse Fourier transform is carried out to described M result sequence, obtains M time domain sequences;
Calculate the peak-to-average force ratio of a described M time domain sequences respectively, select the time domain sequences with minimum peak-to-average force ratio;
Peak clipping operation is carried out to the described time domain sequences with minimum peak-to-average force ratio, obtains the time domain sequences suppressed through peak-to-average force ratio.
9. a kind of signal peak-to-average ratio suppressing method based on fpga chip according to claim 8, is characterized in that, describedly carries out peak clipping operation to the described time domain sequences with minimum peak-to-average force ratio, specifically comprises:
Setting peak clipping threshold value, and the amplitude modulus value described in working as with each discrete point in the time domain sequences of minimum peak-to-average force ratio exceedes described peak clipping threshold value, then the amplitude of described discrete point is set to described peak clipping threshold value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510736843.2A CN105306404A (en) | 2015-11-03 | 2015-11-03 | Device and method for inhibiting signal peak-to-average ratio based on FPGA chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510736843.2A CN105306404A (en) | 2015-11-03 | 2015-11-03 | Device and method for inhibiting signal peak-to-average ratio based on FPGA chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105306404A true CN105306404A (en) | 2016-02-03 |
Family
ID=55203166
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510736843.2A Pending CN105306404A (en) | 2015-11-03 | 2015-11-03 | Device and method for inhibiting signal peak-to-average ratio based on FPGA chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105306404A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106230406A (en) * | 2016-07-15 | 2016-12-14 | 张升泽 | The signal modulating method of electronic chip and system |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1588938A (en) * | 2004-09-16 | 2005-03-02 | 西安电子科技大学 | OFDM communication system and method for reducing peak uniform power tatio |
| CN101227446A (en) * | 2008-02-01 | 2008-07-23 | 成都途筏达科技有限公司 | Method for reducing signal PAR based on self-adapting EVM |
| CN101789924A (en) * | 2009-12-31 | 2010-07-28 | 北京北方烽火科技有限公司 | Peak to average power ratio restraint method and system |
| CN101883064A (en) * | 2009-05-09 | 2010-11-10 | 电子科技大学中山学院 | Selective mapping and amplitude limiting filtering combined method and device for superimposed training sequence |
| CN102075483A (en) * | 2011-01-13 | 2011-05-25 | 东南大学 | Method for reducing peak to average power ratio of OFDM signal |
| US20120099580A1 (en) * | 1999-06-02 | 2012-04-26 | Cimini Jr Leonard Joseph | Method and system for reduction of peak-to-average power ratio of transmission signals comprising overlapping waveforms |
| CN103685130A (en) * | 2013-12-30 | 2014-03-26 | 北京科技大学 | Method based on iterative selective mapping for reducing Peak To Average Power Ratio (PAPR) of OFDM system |
-
2015
- 2015-11-03 CN CN201510736843.2A patent/CN105306404A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120099580A1 (en) * | 1999-06-02 | 2012-04-26 | Cimini Jr Leonard Joseph | Method and system for reduction of peak-to-average power ratio of transmission signals comprising overlapping waveforms |
| CN1588938A (en) * | 2004-09-16 | 2005-03-02 | 西安电子科技大学 | OFDM communication system and method for reducing peak uniform power tatio |
| CN101227446A (en) * | 2008-02-01 | 2008-07-23 | 成都途筏达科技有限公司 | Method for reducing signal PAR based on self-adapting EVM |
| CN101883064A (en) * | 2009-05-09 | 2010-11-10 | 电子科技大学中山学院 | Selective mapping and amplitude limiting filtering combined method and device for superimposed training sequence |
| CN101789924A (en) * | 2009-12-31 | 2010-07-28 | 北京北方烽火科技有限公司 | Peak to average power ratio restraint method and system |
| CN102075483A (en) * | 2011-01-13 | 2011-05-25 | 东南大学 | Method for reducing peak to average power ratio of OFDM signal |
| CN103685130A (en) * | 2013-12-30 | 2014-03-26 | 北京科技大学 | Method based on iterative selective mapping for reducing Peak To Average Power Ratio (PAPR) of OFDM system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106230406A (en) * | 2016-07-15 | 2016-12-14 | 张升泽 | The signal modulating method of electronic chip and system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8499110B2 (en) | Method of generating useful electromagnetic waves by controlling electromagnetic wave noise generated from bus within computer by means of software | |
| US10133298B2 (en) | Memory system with multiple channel interfaces and method of operating same | |
| CN103427835B (en) | Frequency modulator | |
| CN105659547B (en) | The method and apparatus reduced for Peak-Average-Power Ratio | |
| CN104955080A (en) | Mobile terminal work mode control method and device as well as mobile terminal | |
| CN106775491B (en) | Data processing method and storage equipment | |
| CN104142892A (en) | Data reading-writing method, data reading-writing device and data reading-writing system | |
| CN110347620A (en) | A kind of FPGA circuitry and system | |
| CN103955256A (en) | Clock frequency modulation method and clock frequency modulation device | |
| CN201360268Y (en) | Peak clipping device based on peak detection | |
| CN105306404A (en) | Device and method for inhibiting signal peak-to-average ratio based on FPGA chip | |
| CN102983838A (en) | Method for realizing digital logic circuit of Guassian filter based on FPGA (Field Programmable Gate Array) | |
| CN103179079A (en) | Method and device for generating quadrature amplitude modulation signals and digital signal generator | |
| CN104218919A (en) | Fractional-multiple interpolation shaping filter and implementation method thereof | |
| RU2308153C2 (en) | Frequency filter and method for filtration in frequency area | |
| CN105230088A (en) | asynchronous TDD system phase synchronization method and device | |
| CN103780531A (en) | Multi-carrier base band peak eliminating device and method | |
| CN103310836B (en) | Write processing method and device of phase change memorizer | |
| CN103178784A (en) | Oscillation keying modulation method and device and function signal generator | |
| CN112187682B (en) | Method and device for processing symbols | |
| CN107948108A (en) | A kind of DSP devices carrier synchronization method and system | |
| CN109714032A (en) | A kind of impulse wave FM circuit and frequency modulation method based on DDS | |
| CN102065529B (en) | Method and system for reducing multi-carrier peak average ratio | |
| CN204258746U (en) | A kind of point several times interpolation formed filter | |
| CN106796505A (en) | Instruct the method and processor for performing |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160203 |