CN105304722A - Thin-film transistor and preparation method thereof, display substrate and display device - Google Patents
Thin-film transistor and preparation method thereof, display substrate and display device Download PDFInfo
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- CN105304722A CN105304722A CN201510617921.7A CN201510617921A CN105304722A CN 105304722 A CN105304722 A CN 105304722A CN 201510617921 A CN201510617921 A CN 201510617921A CN 105304722 A CN105304722 A CN 105304722A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
Abstract
The invention provides a thin-film transistor and a preparation method thereof, a display substrate and a display device. The thin-film transistor comprises an active layer, wherein slots are formed in regions corresponding to contact holes in the active layer, first conductive metal is filled in the slots, first conductive metal is provided with an extension part, and the extension part covers the surface of the active layer around the slots; and a source electrode and a drain electrode which are formed above the active layer, wherein the source electrode and the drain electrode are respectively contacted with first conductive metal of the active layer via the respective contact holes. According to the thin-film transistor, problems in the prior art that great ohmic contact cannot be formed between the source electrode and the drain electrode and the active layer, and then performance of the thin-film transistor is reduced and display quality of the display device cannot be guaranteed can be solved.
Description
Technical field
The present invention relates to semiconductor display field, particularly relate to a kind of thin-film transistor and preparation method thereof, display base plate, display unit.
Background technology
Low-temperature polysilicon film transistor has the advantage such as higher electron mobility, faster response speed, good stability, at present, and conventional active type array liquid crystal display many employings low-temperature polysilicon film transistor.
Low-temperature polysilicon film transistor (the LowTemperaturePolySiliconThinFilmTransistor of prior art, being called for short LTPSTFT) preparation technology is simply described as follows, first, the substrate being formed with active layer 03 forms gate insulation layer, then, gate insulation layer forms grid; Then, grid forms interlayer insulating film; Again then, graphical interlayer insulating film, on interlayer insulating film, etching forms contact hole (02a and 02b as in Fig. 1), to make last source electrode 01a be contacted with active layer 03 by respective contact hole with drain electrode 01b, as shown in Figure 1.
But, in LTPSTFT preparation technology, due to the gate insulation layer of zones of different and the in uneven thickness of interlayer insulating film, therefore, low temperature polycrystalline silicon in the process of etching formation contact hole bottom contact hole and active layer 03 need to be etched away, but the source electrode 01a of follow-up formation or drain electrode 01b and active layer 03 loose contact will be caused like this, as shown in Figure 1, thus reduce the performance of low-temperature polysilicon film transistor.
In addition, for improving the problems referred to above, prior art also proposes a kind of LTPSTFT preparation technology, source electrode, between drain electrode and active layer be adopt sidewall contact (namely active layer carve wear, active layer sidewall is utilized to contact with source-drain electrode) mode, but this contact can not form good ohmic contact because its contact area is little, thus cause the display of display unit bad.
Summary of the invention
The invention provides a kind of thin-film transistor and preparation method thereof, display base plate, display unit, for solving source electrode in prior art, drain electrode can not form good ohmic contact with active layer, cause thin-film transistor performance to decline, the problem of the display quality of display unit cannot be ensured.
First aspect, the invention provides a kind of thin-film transistor, comprising:
Active layer, in described active layer, the region of corresponding contact hole is formed with groove;
Be filled with the first conducting metal in described groove, and the first conducting metal has extension, this extension is covered in the active layer surface of described groove vicinity;
Be formed at the source electrode above described active layer, drain electrode; Described source electrode, described drain electrode contact with the first conducting metal of described active layer respectively by respective contact hole.
Alternatively, described thin-film transistor also comprises:
Be positioned at the gate insulation layer above described active layer, be positioned at the grid above described gate insulation layer, and be positioned at the interlayer insulating film above grid;
The contact hole of described source electrode and the contact hole of described drain electrode is formed in described interlayer insulating film and described gate insulation layer.
Alternatively, the thickness of described first conducting metal is greater than the degree of depth of described groove;
And/or the degree of depth of groove is less than or equal to the thickness of described active layer.
Alternatively, described first conducting metal is: titanium, molybdenum or aluminum metal.
Second aspect, the invention provides a kind of preparation method of thin-film transistor, comprising:
Etch the region of corresponding contact hole in described active layer, form groove;
In described groove, fill first conducting metal with extension, described extension is covered in the active layer surface of described groove vicinity;
Above described active layer, form source electrode and drain electrode, described source electrode, described drain electrode contact with the first conducting metal of described active layer respectively by respective contact hole.
Alternatively, in described groove, fill first conducting metal with extension, comprising:
Depositing first conductive metal level on the reeded active layer of formation;
Mask plate is adopted to form the first conductive metal pattern on described first conductive metal layer;
Etch the first conductive metal layer, obtain first conducting metal with extension of filling in groove.
Alternatively, above described active layer, form source electrode and drain electrode, comprising:
Gate insulation layer is formed above described active layer;
Grid is formed above described gate insulation layer;
Interlayer insulating film is formed above described grid;
The contact hole of described source electrode and the contact hole of described drain electrode is formed in described interlayer insulating film and described gate insulation layer;
In the contact hole of described source electrode and the contact hole of described drain electrode, fill the second conducting metal, form source electrode and drain electrode, the second conducting metal in each contact hole is contacted with the first conducting metal of described active layer.
Alternatively, etch the region of corresponding contact hole in described active layer, before forming groove, described method also comprises:
One underlay substrate is provided;
Described underlay substrate forms resilient coating;
Described resilient coating forms amorphous silicon layer;
Described amorphous silicon layer is converted to polysilicon, obtains active layer;
Or,
One underlay substrate is provided;
Described underlay substrate forms shielding layer/light blocking layer;
Described shielding layer or light blocking layer form resilient coating;
Described resilient coating forms amorphous silicon layer;
Described amorphous silicon layer is converted to polysilicon, obtains active layer.
The third aspect, the invention provides a kind of display base plate, comprises above-mentioned arbitrary described thin-film transistor.
Fourth aspect, the invention provides a kind of display unit, and this display unit comprises above-mentioned arbitrary described display base plate.
As shown from the above technical solution, thin-film transistor of the present invention and preparation method thereof, display base plate, display unit, groove is formed by the region of contact hole corresponding in active layer, and then fill the first conducting metal in a groove, and make the extension of the first conducting metal cover the active layer of groove vicinity, and then can be contacted with the first conducting metal by respective contact hole with drain electrode in source electrode, the ohmic contact of metal and metal can not deposit the problem that active layer and Metal Contact are not measured or sidewall contact is bad in the prior art, ensure the performance of thin-film transistor, and improve the display quality of display unit.
Accompanying drawing explanation
Fig. 1 is the structural representation of thin-film transistor in prior art;
The structural representation of the thin-film transistor that Fig. 2 A provides for one embodiment of the invention;
The structural representation of the thin-film transistor that Fig. 2 B provides for another embodiment of the present invention;
The schematic flow sheet of the preparation method of the thin-film transistor that Fig. 3 provides for one embodiment of the invention;
Preparation method's schematic diagram of the thin-film transistor that Fig. 4 A to Fig. 4 I provides for one embodiment of the invention;
Fig. 5 is the vertical view of active layer in the embodiment of the present invention.
Description of reference numerals
In Fig. 1: the contact hole 02a of source electrode 01a, drain electrode 01b, source electrode, the contact hole 02b of drain electrode, active layer 03;
In Fig. 2 A to Fig. 5: substrate/underlay substrate 10, active layer 11, the extension 14 of groove 12, first conducting metal 13, first conducting metal, source electrode 15a, drain electrode 15b, the contact hole 16a of source electrode, the contact hole 16b of drain electrode, gate insulation layer 17, grid 18, interlayer insulating film 19, light shield layer/light blocking layer 20, resilient coating 21, amorphous silicon layer 22.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail.Following examples for illustration of the present invention, but are not used for limiting the scope of the invention.
In the embodiment of the present invention " on ", D score is as the criterion with sequencing during manufacturing array substrate, such as, refers to relatively at the pattern of rear formation at upper pattern, under pattern refer to the pattern relatively formerly formed.It should be noted that, " layer " in the present invention can refer to the thin film utilizing a certain material to utilize the techniques such as deposition on substrate to produce, and can also refer to the functional layer realizing a certain function that multiple material utilizes patterning processes to be formed on substrate respectively.
Fig. 1 and Fig. 2 respectively illustrates the structural representation of the thin-film transistor that one embodiment of the invention provides, and as depicted in figs. 1 and 2, the thin-film transistor of the present embodiment can comprise:
Active layer 11, in described active layer 11, the region of corresponding contact hole (16a and 16b as shown in fig. 4h) is formed with groove 12;
Be filled with the first conducting metal 13 in described groove 12, and the first conducting metal 13 has extension 14, this extension is covered in the active layer surface of groove vicinity, shown in Fig. 5 and Fig. 4 F described as follows;
Be formed at the source electrode 15a above active layer 11, drain electrode 15b; This source electrode 15a, drain electrode 15b contact with the first conducting metal 13 of described active layer 11 respectively by respective contact hole.
For example, the first conducting metal 13 can be titanium, molybdenum or aluminum metal etc.In actual applications, can select according to actual needs, the present embodiment does not limit it.
In addition, the thickness of aforementioned first conducting metal 13 is greater than the degree of depth of groove 12; The degree of depth of groove 12 can be less than or equal to the thickness of active layer 11.Particularly, the thickness of the degree of depth of groove 12, the first conducting metal 13 can be set according to actual needs, and the development length of the extension 14 of the first conducting metal, the present embodiment does not limit it.
In a particular application, thin-film transistor also comprises: be positioned at the gate insulation layer 17 above active layer 11, is positioned at the grid 18 above gate insulation layer 17, and is positioned at the interlayer insulating film 19 above grid 18;
The contact hole 16a (as shown at figure 4h) of source electrode 15a and the contact hole 16b (as shown at figure 4h) of drain electrode 15b is formed in interlayer insulating film 19 and gate insulation layer 17.
Certainly, the thin-film transistor of the present embodiment also can comprise substrate 10, resilient coating 21 (as shown in Figure 4 A) etc.The structure of this substrate 10, resilient coating 21, gate insulation layer 17 and interlayer insulating film 19 and the substrate of existing thin-film transistor, gate insulation layer are substantially identical with the structure of interlayer insulating film, and the present invention does not describe in detail at this.
The difference of the thin-film transistor shown in Fig. 1 and Fig. 2 is that the thin-film transistor shown in Fig. 1 does not comprise the thin-film transistor shown in light shield layer/light blocking layer 20, Fig. 2 and comprises and being positioned at above substrate 10, and is positioned at the light shield layer/light blocking layer 20 below resilient coating 21.For example, this light shield layer 20 can be positioned at pixel region, for preventing the light leakage phenomena of thin-film transistor, and improves the performance of thin-film transistor.
The thin-film transistor of the present embodiment, groove is formed by the region of contact hole corresponding in active layer, and then fill the first conducting metal in a groove, and make the extension of the first conducting metal cover the active layer of groove vicinity, and then can be contacted with the first conducting metal by respective contact hole with drain electrode in source electrode, the ohmic contact of metal and metal can not deposit the problem that active layer and Metal Contact are not measured or sidewall contact is bad in the prior art, ensure the performance of thin-film transistor, and improve the display quality of display unit.
Preparation method's schematic diagram of the thin-film transistor that Fig. 3 shows, as shown in Figure 3, the preparation method of the thin-film transistor of the present embodiment comprises following step.
301, etch the region of corresponding contact hole in described active layer, form groove;
302, in described groove, fill first conducting metal with extension, described extension is covered in the active layer surface of described groove vicinity;
303, above described active layer, form source electrode and drain electrode, described source electrode, described drain electrode contact with the first conducting metal of described active layer respectively by respective contact hole.
For example, above-mentioned steps 302 specifically can comprise following sub-step 3021 to sub-step 3023:
3021, depositing first conductive metal level on the reeded active layer of formation, as titanium coating;
3022, mask plate is adopted to form the first conductive metal pattern on described first conductive metal layer;
3023, etch the first conductive metal layer, obtain first conducting metal with extension of filling in groove.
In the method for the present embodiment, source electrode can be contacted with the first conducting metal by respective contact hole with drain electrode, the ohmic contact of metal and metal can not deposit the problem that active layer and Metal Contact are not measured or sidewall contact is bad in the prior art, ensure the performance of thin-film transistor, and improve the display quality of display unit.
Below in conjunction with Fig. 4 A to Fig. 4 I and specific embodiment, the manufacture method to LPTSTFT of the present invention describes in detail.
S01, provide a underlay substrate 10;
S02, on described underlay substrate 10, form resilient coating 21, as shown in Figure 4 A.
For example, according to actual needs before formation resilient coating 21, shielding layer/light blocking layer 20 can be formed on described underlay substrate 10.
In the present embodiment, if when the cleanliness factor of underlay substrate 10 does not meet the demands, first can carry out prerinse to underlay substrate 10, and then form resilient coating 21 on underlay substrate 10.
In addition, can on the glass substrate through cleaning in advance, resilient coating 21 is formed with methods such as PECVD, low-pressure chemical vapor deposition (LPCVD), sub-atmospheric CVD (APCVD), electron cyclotron resonance chemical vapour deposition (CVD) (ECR-CVD) or sputterings, for stopping in glass that contained Impurity Diffusion is with active layer, prevent from having an impact to characteristics such as the threshold voltage of thin-film transistor element and leakage currents.
The material of resilient coating 21 can select oxide, nitride or nitrogen oxide etc.Resilient coating can be individual layer, bilayer or sandwich construction.
S03, on described resilient coating 21, form amorphous silicon layer 22, as shown in Figure 4 B.
Particularly, PECVD, LPCVD or sputtering method can be adopted to form amorphous silicon layer and amorphous silicon membrane.When adopting deposition process to form amorphous silicon layer 22, depositing temperature can be controlled in less than 600 DEG C.The thickness of amorphous silicon layer 22 can be 100 dust to 3000 dusts, preferably 500 dust to 1000 dusts.
S04, described amorphous silicon layer 22 is converted to polysilicon layer, obtains active layer 11, as shown in Figure 4 C.
Alternatively, can carry out dehydrogenating technology to amorphous silicon layer 22 in advance in the present embodiment, desorption temperature can be 400 ~ 600 DEG C, and the processing time can be 20 ~ 120 minutes.It should be noted that, make hydrogen content in amorphous silicon layer below 3%, then can save the dehydrogenating technology to amorphous silicon layer according to additive method, concrete steps can be carried out according to actual conditions.
Secondly, under preset temperature, repeatedly laser annealing is carried out to described amorphous silicon layer, form polysilicon layer.Such as, excimer laser is adopted to carry out laser annealing process.
Moreover, patterning processes is carried out to polysilicon layer, obtains aforesaid active layer 11.
S05, be etched with the region of corresponding contact hole in active layer 11 (16a and 16b as shown in fig. 4h), form groove 12, as shown in Figure 4 D.
Will be understood that, usually, the opening of groove is normally greater than the respective regions of contact hole.
S06, on the active layer 11 being formed with groove 12 depositing first conductive metal level, as titanium coating, Mo layer or aluminum metal layer, as shown in Figure 4 E;
S07, employing mask plate form the first conductive metal pattern on the first conductive metal layer; , and then etching the first conductive metal layer, obtain first conducting metal 13 with extension of filling in groove 12, this extension 14 is covered in the active layer surface around groove 12, as illustrated in figure 4f;
S08, above active layer 11, form gate insulation layer 17.
Particularly, can adopt PEVCD method, deposit gate insulation layer 17 on the polysilicon layer, gate insulation layer 17 can select oxide, nitride or nitrogen oxide etc.In addition, gate insulation layer 17 can make individual layer, bilayer or sandwich construction etc.
S09, above gate insulation layer 17, form grid 18, as shown in Figure 4 G.
Such as, gate insulation layer 17 adopt the methods such as magnetron sputtering, thermal evaporation, PEVCD to form gate metal layer.Gate metal layer adopts coating one deck photoresist, and then etching forms grid 18.
The metal of the gate metal layer in the present embodiment can be in Pt, Ru, Au, Ag, Mo, Cr, Al, Ta, Ti, W one or more.
S10, above grid 18, form interlayer insulating film 19.
S11, in interlayer insulating film 19 and gate insulation layer 17, form the contact hole 16a of source electrode 15a and the contact hole 16b of drain electrode 15b, as shown at figure 4h.
S12, in the contact hole 16a of source electrode 15a and the contact hole 16b of drain electrode 15b, fill the second conducting metal, form source electrode 15a and drain electrode 15b, the second conducting metal in each contact hole is contacted, as shown in fig. 41 with the first conducting metal of described active layer.
That is, described source electrode 15a, described drain electrode 15b contact with the first conducting metal 13 of described active layer 11 respectively by respective contact hole.
It should be noted that the thin-film transistor shown in earlier figures 1 and Fig. 2 can adopt the preparation method described in this embodiment to prepare thin-film transistor.
Preparation method shown in above-mentioned Fig. 4 A to Fig. 4 I forms groove on active layer, and then fill first conducting metal with extension, thus, follow-up filling the second conducting metal in the contact hole can be contacted with the first conducting metal, solve in prior art due to source-drain electrode and active layer adopt at present sidewall contact and also active layer thinner, contact area is little, easily occurs the problem of loose contact.
In the present embodiment, first conducting metal and active layer directly can form good contact, in addition the second conducting metal in contact hole and the first conducting metal form contacting of metal and metal, thus good ohmic contact can be formed, the problem that active layer and Metal Contact are not measured or sidewall contact is bad in the prior art can not be deposited, ensure the performance of thin-film transistor, and improve the display quality of display unit.
Above-mentioned preparation technology is simple, and do not affect the technique of other steps, thin-film transistor prepared by above-described embodiment can be applicable to the association area such as liquid crystal display, OLED.
Further, the present invention also provides a kind of display base plate, thin-film transistor prepared by the preparation method that this display base plate comprises the above-mentioned any embodiment of employing to be provided.This display base plate is such as array base palte.
The present invention also can provide a kind of display unit, and this display unit can comprise the display base plate of the thin-film transistor prepared by said method, and thus, the display unit of the present embodiment has good display quality.Display unit can be: any product or parts with Presentation Function such as display floater, Electronic Paper, TV, display, DPF, mobile phone, panel computer.
One of ordinary skill in the art will appreciate that: above each embodiment, only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to foregoing embodiments to invention has been detailed description, those of ordinary skill in the art is to be understood that: it still can be modified to the technical scheme described in foregoing embodiments, or carries out equivalent replacement to wherein some or all of technical characteristic; And these amendments or replacement, do not make the essence of appropriate technical solution depart from the scope of the claims in the present invention.
Claims (10)
1. a thin-film transistor, is characterized in that, comprising:
Active layer, in described active layer, the region of corresponding contact hole is formed with groove;
Be filled with the first conducting metal in described groove, and the first conducting metal has extension, this extension is covered in the active layer surface of described groove vicinity;
Be formed at the source electrode above described active layer, drain electrode; Described source electrode, described drain electrode contact with the first conducting metal of described active layer respectively by respective contact hole.
2. thin-film transistor according to claim 1, is characterized in that, described thin-film transistor also comprises:
Be positioned at the gate insulation layer above described active layer, be positioned at the grid above described gate insulation layer, and be positioned at the interlayer insulating film above grid;
The contact hole of described source electrode and the contact hole of described drain electrode is formed in described interlayer insulating film and described gate insulation layer.
3. thin-film transistor according to claim 1, is characterized in that, the thickness of described first conducting metal is greater than the degree of depth of described groove;
And/or the degree of depth of groove is less than or equal to the thickness of described active layer.
4. thin-film transistor according to claim 1, is characterized in that, described first conducting metal is: titanium, molybdenum or aluminum metal.
5. a preparation method for thin-film transistor, is characterized in that, comprising:
Etch the region of corresponding contact hole in described active layer, form groove;
In described groove, fill first conducting metal with extension, described extension is covered in the active layer surface of described groove vicinity;
Above described active layer, form source electrode and drain electrode, described source electrode, described drain electrode contact with the first conducting metal of described active layer respectively by respective contact hole.
6. method according to claim 5, is characterized in that, fills first conducting metal with extension, comprising in described groove:
Depositing first conductive metal level on the reeded active layer of formation;
Mask plate is adopted to form the first conductive metal pattern on described first conductive metal layer;
Etch the first conductive metal layer, obtain first conducting metal with extension of filling in groove.
7. method according to claim 5, is characterized in that, forms source electrode and drain electrode, comprising above described active layer:
Gate insulation layer is formed above described active layer;
Grid is formed above described gate insulation layer;
Interlayer insulating film is formed above described grid;
The contact hole of described source electrode and the contact hole of described drain electrode is formed in described interlayer insulating film and described gate insulation layer;
In the contact hole of described source electrode and the contact hole of described drain electrode, fill the second conducting metal, form source electrode and drain electrode, the second conducting metal in each contact hole is contacted with the first conducting metal of described active layer.
8. method according to claim 5, is characterized in that, etches the region of corresponding contact hole in described active layer, and before forming groove, described method also comprises:
One underlay substrate is provided;
Described underlay substrate forms resilient coating;
Described resilient coating forms amorphous silicon layer;
Described amorphous silicon layer is converted to polysilicon, obtains active layer;
Or,
One underlay substrate is provided;
Described underlay substrate forms shielding layer/light blocking layer;
Described shielding layer or light blocking layer form resilient coating;
Described resilient coating forms amorphous silicon layer;
Described amorphous silicon layer is converted to polysilicon, obtains active layer.
9. a display base plate, comprises the arbitrary described thin-film transistor of Claims 1-4.
10. a display unit, is characterized in that, described display unit comprises display base plate as claimed in claim 9.
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| CN105304722B (en) | 2018-09-04 |
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