CN105304650A - Thin-film transistor array substrate and preparation method and display device thereof - Google Patents
Thin-film transistor array substrate and preparation method and display device thereof Download PDFInfo
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Abstract
The invention discloses a thin-film transistor array substrate, which comprises thin-film transistors which are arranged on a glass substrate in an array, wherein each thin-film transistor comprises a gate electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode; the material of each active layer is a metal oxide semiconductor material; an amorphous silicon layer is also arranged on each active layer, covers a channel region and extends between each source electrode and the active layer and each drain electrode and the active layer; and ohmic contact layers are also arranged between the source electrodes and the amorphous silicon layers and between the drain electrodes and the amorphous silicon layers respectively. The invention further discloses a preparation method of the array substrate and a display device including the array substrate.
Description
Technical field
The present invention relates to display technology field, particularly relate to a kind of thin-film transistor array base-plate and preparation method thereof, also relate to the display unit comprising this thin-film transistor array base-plate.
Background technology
Panel display apparatus has that fuselage is thin, power saving, the many merits such as radiationless, be widely used.Existing panel display apparatus mainly comprises liquid crystal indicator (LiquidCrystalDisplay, LCD) and organic electroluminescence display device and method of manufacturing same (OrganicLightEmittingDisplay, OLED).
OLED Display Technique based on Organic Light Emitting Diode is compared with the LCD of maturation, OLED is the display of active illuminating, there is the advantage such as self-luminous, high-contrast, wide viewing angle (reaching 170 °), fast response, high-luminous-efficiency, low operating voltage (3 ~ 10V), ultra-thin (thickness is less than 2mm), there is more excellent colour display image quality, broader viewing scope and larger design flexibility.
Thin-film transistor (ThinFilmTransistor, TFT) is the important component part of panel display apparatus, can be formed on glass substrate or plastic base, and usually used as opening the light, device and drive unit are used in such as LCD, OLED.Thin Film Transistor-LCD (ThinFilmTransistorLiquidCrystalDisplay is called for short TFT-LCD) has the features such as volume is little, low in energy consumption, radiationless, in current flat panel display market, occupy leading position.TFT-LCD obtains development at full speed in recent years, and its size and resolution constantly improve, and large scale, high-resolution LCD TV become a main flow of TFT-LCD development.Along with the continuous increase of TFT-LCD size, the improving constantly of resolution, in order to improve display quality, need the drive circuit adopting higher frequency, the mobility of existing amorphous silicon film transistor is difficult to the needs meeting liquid crystal display.The mobility of the thin transistor of amorphous silicon is generally at 0.6cm
2about/Vs, but at display size more than 80 inches, when driving frequency is 120Hz, need 1cm
2the mobility of/more than Vs, the mobility of present amorphous silicon silicon thin film transistor is obviously difficult to meet.
Oxide semiconductor TFT technology is current hot technology.Oxide semiconductor is owing to having higher electron mobility (oxide semiconductor mobility >10cm
2/ Vs, a-Si mobility only 0.5 ~ 0.8cm
2/ Vs), and compare LTPS (low temperature polycrystalline silicon), oxide semiconductor processing procedure is simple, higher with a-Si process-compatible, can be applicable to LCD (liquid crystal display), organic electroluminescent (OLED), Flexible Displays (Flexible) etc., can be applicable to size dimension display, there is good application development prospect, for current industry research is popular.
Fig. 1 is the structural representation of existing a kind of thin-film transistor array base-plate.As shown in Figure 1, this array base palte comprises array and is arranged at thin-film transistor 2 (only illustrating one of them thin-film transistor 2 in accompanying drawing) on glass substrate 1, and described thin-film transistor 2 have employed oxide semiconductor TFT technology.Particularly, consult Fig. 1, described thin-film transistor 2 comprises gate electrode 3, gate insulator 4, active layer 5, source electrode 6 and drain electrode 7.Wherein, gate electrode 3 is formed on described glass substrate 1, and gate insulator 4 covers on described gate electrode 3, and active layer 5 is formed on described gate insulator 4, and source electrode 6 and drain electrode are formed on described gate insulator 4; Spaced and have part respectively and be overlapped on described active layer 5 between described source electrode 6 and drain electrode 7, described active layer 5 corresponds to described source electrode 6 and the spaced formation channel region, region of drain electrode 7; Channel region portions on described active layer 5 is provided with etching barrier layer 8, and normally, the material mainly inorganic thin film of etching barrier layer 8 is such as SiN
xor SiO
x, etching barrier layer 8 is mainly used for, when preparing source electrode 6 and drain electrode 7, preventing from being damaged to active layer 5.Further, as shown in Figure 1, described array base palte also comprises the insulating protective layer 9 covered on described thin-film transistor 2.
Thin-film transistor array base-plate forms structure graph by repeatedly light shield technique (patterning processes) to have come, comprise the techniques such as mask, exposure, development, etching and stripping respectively again in light shield technique each time, wherein etching technics comprises dry etching and wet etching.The preparation technology of thin-film transistor array base-plate as above, at least comprises following light shield technique: (1) adopts first light shield technique to form gate electrode 3 on glass substrate 1.(2), prepare gate insulator 4 on gate electrode 3 after, gate insulator 4 adopt second light shield technique be formed with active layer 5.(3) on active layer 5, the 3rd road light shield technique is adopted to form etching barrier layer 8.(4) on active layer 5, the 4th road light shield technique is adopted to form source electrode 6 and drain electrode 7.The number of times of light shield technique can weigh the complicated and simple degree manufacturing thin-film transistor array base-plate, and the number of times reducing light shield technique just means the reduction of manufacturing cost.
Summary of the invention
In view of this, the invention provides a kind of thin-film transistor array base-plate and preparation method thereof, thin-film transistor wherein has more superior performance compared to prior art; Its preparation method, compared to prior art, decreases the number of times of light shield technique, reduces technology difficulty, provide cost savings.
To achieve these goals, present invention employs following technical scheme:
A kind of thin-film transistor array base-plate, comprise array and be arranged at thin-film transistor on glass substrate, described thin-film transistor comprises: gate electrode, is formed on described glass substrate; Gate insulator, covers on described gate electrode; Active layer, is formed on described gate insulator; Source electrode and drain electrode, be formed on described gate insulator; Spaced and have part respectively and be overlapped on described active layer between described source electrode and drain electrode, described active layer corresponds to described source electrode and the spaced formation channel region, region of drain electrode; Wherein, the material of described active layer is metal oxide semiconductor material, described active layer is also provided with an amorphous silicon layer, and described amorphous silicon layer covers described channel region, and extends between described source electrode and described active layer and between described drain electrode and described active layer; Also ohmic contact layer is respectively arranged with between described source electrode and described amorphous silicon layer and between described drain electrode and described amorphous silicon layer.
Wherein, described metal oxide semiconductor material be selected from ZnO, InZnO, ZnSnO, GaInZnO and ZrInZnO any one or two or more.
Wherein, the thickness of described active layer is
Wherein, the material of described amorphous silicon layer is transparent amorphous oxide semi-conducting material.
Wherein, the thickness of described amorphous silicon layer is
Wherein, described array base palte also comprises the insulating protective layer covered on described thin-film transistor.
The preparation method of thin-film transistor array base-plate as above, it comprises: adopt first light shield technique to form gate electrode on the glass substrate; Second light shield technique is adopted to be formed with active layer, amorphous silicon layer and ohmic contact layer; The 3rd road light shield technique is adopted to form source electrode and drain electrode.
Wherein, the method specifically comprises step: S1, provide a glass substrate, and this glass substrate is formed gate material rete; S2, by first light shield technique, described gate material rete etching is formed the gate electrode of predetermined pattern; S3, on the glass substrate of as above structure, form gate insulator, active layer material rete, amorphous silicon layer film layer and ohmic contact layer film layer successively; S4, the active layer being formed predetermined pattern by second light shield technique on described gate insulator, amorphous silicon layer and ohmic contact layer; Wherein, described active layer, amorphous silicon layer and ohmic contact layer are formed by etching by described active layer material rete, amorphous silicon layer film layer and ohmic contact layer film layer respectively; S5, on the glass substrate of as above structure, form source/drain electrode film layer; S6, by the 3rd road light shield technique, described source/drain electrode film layer etching is formed source electrode and the drain electrode of predetermined pattern; Wherein, the partial etching between described source electrode and drain electrode of described ohmic contact layer is fallen, exposes described amorphous silicon layer.
Further, the method also comprises step: S7, the glass substrate of structure that obtains in step S6 form one deck insulating protective layer.
Another aspect of the present invention is to provide a kind of display unit, and it comprises thin-film transistor array base-plate as above.
The thin-film transistor array base-plate provided in the embodiment of the present invention; in thin-film transistor wherein; active layer arranges amorphous silicon layer; amorphous silicon layer not only covers channel region; but also extend to source electrode to both sides and between drain electrode and the link position of active layer; amorphous silicon layer can as etching barrier layer when preparation source electrode and drain electrode to protect active layer; simultaneously; extend to source electrode due to amorphous silicon layer and between drain electrode and the link position of active layer, the effect increasing switching current can also be played.Above thin-film transistor array base-plate is applied in display unit, such as, be TFT-LCD or OLED, and display unit can be made to have more superior performance compared to prior art.Further, in the preparation technology of the thin-film transistor array base-plate of above structure, amorphous silicon layer as etching barrier layer can prepare by the ohmic contact layer on active layer and its in light shield technique, one light shield technique is saved compared to prior art, reduce technology difficulty, provide cost savings.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing a kind of thin-film transistor array base-plate;
Fig. 2 is the structural representation of the thin-film transistor array base-plate that the embodiment of the present invention 1 provides;
In the preparation method of the thin-film transistor array base-plate in Fig. 3 a-Fig. 3 g embodiment of the present invention 1, the graphical representation of exemplary of the device architecture that each step obtains;
Fig. 4 is the structural representation of the display unit that the embodiment of the present invention 2 provides.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.The example of these preferred implementations illustrates in the accompanying drawings.Shown in accompanying drawing and the embodiments of the present invention described with reference to the accompanying drawings be only exemplary, and the present invention is not limited to these execution modes.
At this, also it should be noted that, in order to avoid the present invention fuzzy because of unnecessary details, illustrate only in the accompanying drawings with according to the closely-related structure of the solution of the present invention and/or treatment step, and eliminate other details little with relation of the present invention.
Embodiment 1
The present embodiment provide firstly a kind of thin-film transistor array base-plate, as shown in Figure 2, this array base palte comprises array and is arranged at multiple thin-film transistors 20 (only illustrating one of them thin-film transistor 20 in accompanying drawing) on glass substrate 10, and described thin-film transistor 20 have employed oxide semiconductor TFT technology.Particularly, consult Fig. 2, described thin-film transistor 20 comprises gate electrode 21, gate insulator 22, active layer 23, source electrode 261 and drain electrode 262.Wherein, gate electrode 21 is formed on described glass substrate 10, gate insulator 22 covers on described gate electrode 21, active layer 23 is formed on described gate insulator 22, source electrode 261 and drain electrode 262 are arranged in same structure layer, be formed on described gate insulator 22, spaced and have part respectively and be overlapped on described active layer 23 between described source electrode 261 and drain electrode 262, described active layer 23 corresponds to described source electrode 261 and the spaced formation channel region, region of drain electrode 262.
In the present embodiment, consult Fig. 2, the material of described active layer 23 is metal oxide semiconductor material, described active layer 23 is also provided with an amorphous silicon layer 24, described amorphous silicon layer 24 covers described channel region, one end of amorphous silicon layer 24 extends between described source electrode 261 and described active layer 23, further, ohmic contact layer 25 (in this position, active layer 23, amorphous silicon layer 24, ohmic contact layer 25 and source electrode 261 successively lamination are arranged) is also provided with between source electrode 261 and amorphous silicon layer 24.The other end of amorphous silicon layer 24 extends between described drain electrode 262 and described active layer 23, further, ohmic contact layer 25 (in this position, active layer 23, amorphous silicon layer 24, ohmic contact layer 25 and drain electrode 262 successively lamination are arranged) is also provided with between drain electrode 262 and amorphous silicon layer 24.
Further, as shown in Figure 2, described array base palte also comprises the insulating protective layer 30 covered on described thin-film transistor 20.
Wherein, the material of described gate electrode 21 be selected from but be not limited in the low-resistance materials such as Cr, Mo, Al, Cu one or more, can be that one or more layers is stacking, the preferred Mo material of the present embodiment, thickness can not do concrete restriction, sets according to actual needs.
Wherein, described gate insulator 22 material mainly inorganic insulating material can be such as SiN
xor SiO
xor both combine, its thickness can be selected
between.
Wherein, the material of described active layer 23 is metal oxide semiconductor material, can be selected from ZnO, InZnO, ZnSnO, GaInZnO and ZrInZnO any one or two or more, can be that one or more layers is stacking, the preferred GaInZnO material of the present embodiment, its thickness can be selected
between.
Wherein, the material of described amorphous silicon layer 24 is transparent amorphous oxide semi-conducting material, and its thickness can be selected
between.Amorphous silicon layer 24 thickness total with ohmic contact layer 25 is selected
between be the scheme of comparative optimization.
Wherein, being selected from but being not limited to the low resistance metals such as Al, Ti, Cu and alloy thereof of described source electrode 261 and drain electrode 262, the preferred Al material of the present embodiment, its thickness can be selected
between.
Wherein, described insulating protective layer 30 material mainly inorganic insulating material can be such as SiN
xor SiO
xor both combine, its thickness can be selected
between.
As above the thin-film transistor array base-plate of structure; active layer 23 arranges amorphous silicon layer 24; amorphous silicon layer 24 not only covers channel region; but also between the link position extending to source electrode 261 and drain electrode 262 and active layer 23 to both sides; amorphous silicon layer 24 can as etching barrier layer when preparation source electrode 261 and drain electrode 262 to protect active layer 23; simultaneously; because amorphous silicon layer 24 extends between the link position of source electrode 261 and drain electrode 262 and active layer 23, the effect increasing switching current can also be played.
Introduce the preparation method of thin-film transistor array base-plate as above below in conjunction with Fig. 3 a-Fig. 3 g, it comprises: adopt first light shield technique to form gate electrode on the glass substrate; Second light shield technique is adopted to be formed with active layer, amorphous silicon layer and ohmic contact layer; The 3rd road light shield technique is adopted to form source electrode and drain electrode.Wherein, comprise the techniques such as mask, exposure, development, etching and stripping respectively again in light shield technique each time, wherein etching technics comprises dry etching and wet etching.Light shield technique has been the technology of existing comparative maturity, no longer launches to describe in detail at this.
Particularly, the method mainly comprises the following steps:
S1, as shown in Figure 3 a, provide a glass substrate 10, this glass substrate 10 is formed gate material rete 21a.Wherein, gate material rete 21a can be prepared by magnetron sputtering technique.
S2, as shown in Figure 3 b, etches the gate electrode 21 forming predetermined pattern by described gate material rete 21a by first light shield technique.Wherein, gate electrode 21 is formed after dry etching by gate material rete 21a.
S3, as shown in Figure 3 c, the glass substrate 10 of as above structure forms gate insulator 22, active layer material rete 23a, amorphous silicon layer film layer 24a (a-Si) and ohmic contact layer film layer 25a (n+a-Si) successively.Wherein, gate insulator 22 can be prepared by plasma enhanced chemical vapor deposition technique (PECVD), active layer material rete 23a can be prepared by magnetron sputtering technique, and amorphous silicon layer film layer 24a and ohmic contact layer film layer 25a can be prepared by magnetron sputtering technique plated film.
S4, as shown in Figure 3 d, forms the active layer 23 of predetermined pattern, amorphous silicon layer 24 and ohmic contact layer 25 by second light shield technique on described gate insulator 22.Wherein, described active layer 23, amorphous silicon layer 24 and ohmic contact layer 25 are formed by etching by described active layer material rete 23a, amorphous silicon layer film layer 24a and ohmic contact layer film layer 25a respectively.Can be first form ohmic contact layer 25 and amorphous silicon layer 24 by dry etching ohmic contact layer film layer 25a and amorphous silicon layer film layer 24a, then be formed with active layer 23 by wet etching active layer material rete 23a.
S5, as shown in Figure 3 e, the glass substrate 10 of as above structure forms source/drain electrode film layer 26a.Source/drain electrode film layer 26a can be prepared by magnetron sputtering technique.
S6, as illustrated in figure 3f, etches the source electrode 261 and drain electrode 262 that form predetermined pattern by described source/drain electrode film layer 26a by the 3rd road light shield technique.First source electrode 261 and drain electrode 262 is formed by wet etching source/drain electrode film layer 26a, then etched away by the part (corresponding to channel region) between source electrode 261 and drain electrode 262 of dry etching by ohmic contact layer 25, expose amorphous silicon layer 24.
S7, as shown in figure 3g, the glass substrate 10 of the structure obtained in step S6 forms one deck insulating protective layer 30, obtains the structure of thin-film transistor array base-plate as shown in Figure 2.The Each part of insulating protective layer 30 cover film transistor 20, insulating protective layer 30 can be prepared by plasma enhanced chemical vapor deposition technique (PECVD).It should be noted that, in thin-film transistor array base-plate, also should comprise other some pattern structures such as pixel electrode, but these structures and the present invention program are not closely related, no longer launch to describe in detail at this.
In the preparation technology of the thin-film transistor array base-plate more than provided, amorphous silicon layer 24 as etching barrier layer can prepare (step S4 as above) in light shield technique with active layer 23 and the ohmic contact layer on it 25, one light shield technique is saved compared to prior art, reduce technology difficulty, provide cost savings.
Embodiment 2
Present embodiments provide a kind of display unit, wherein have employed the thin-film transistor array base-plate as embodiment 1 provides.This display unit can be such as thin-film transistor LCD device (TFT-LCD) or organic electroluminescence display device and method of manufacturing same (OLED), have employed the thin-film transistor array base-plate as embodiment 1 provides, display unit can be made to have more superior performance compared to prior art, also reduce cost simultaneously.Particularly, for thin-film transistor LCD device, consult Fig. 4, this liquid crystal indicator comprises liquid crystal panel 100 and backlight module 200, described liquid crystal panel 100 is oppositely arranged with described backlight module 200, described backlight module 200 provides display light source to described liquid crystal panel 100, to make described liquid crystal panel 100 show image.Wherein, liquid crystal panel 100 comprises the array base palte 101 and optical filtering substrate 102 that are oppositely arranged, also comprises the liquid crystal layer 103 between array base palte 101 and optical filtering substrate 102.Wherein, namely array base palte 101 have employed the thin-film transistor array base-plate as embodiment 1 provides.
It should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.
The above is only the embodiment of the application; it should be pointed out that for those skilled in the art, under the prerequisite not departing from the application's principle; can also make some improvements and modifications, these improvements and modifications also should be considered as the protection range of the application.
Claims (10)
1. a thin-film transistor array base-plate, comprise array and be arranged at thin-film transistor on glass substrate, described thin-film transistor comprises:
Gate electrode, is formed on described glass substrate;
Gate insulator, covers on described gate electrode;
Active layer, is formed on described gate insulator;
Source electrode and drain electrode, be formed on described gate insulator; Spaced and have part respectively and be overlapped on described active layer between described source electrode and drain electrode, described active layer corresponds to described source electrode and the spaced formation channel region, region of drain electrode; It is characterized in that,
The material of described active layer is metal oxide semiconductor material, described active layer is also provided with an amorphous silicon layer, described amorphous silicon layer covers described channel region, and extends between described source electrode and described active layer and between described drain electrode and described active layer; Also ohmic contact layer is respectively arranged with between described source electrode and described amorphous silicon layer and between described drain electrode and described amorphous silicon layer.
2. thin-film transistor array base-plate according to claim 1, is characterized in that, described metal oxide semiconductor material be selected from ZnO, InZnO, ZnSnO, GaInZnO and ZrInZnO any one or two or more.
3. thin-film transistor array base-plate according to claim 1 and 2, is characterized in that, the thickness of described active layer is
4. thin-film transistor array base-plate according to claim 1 and 2, is characterized in that, the material of described amorphous silicon layer is transparent amorphous oxide semi-conducting material.
5. thin-film transistor array base-plate according to claim 4, is characterized in that, the thickness of described amorphous silicon layer is
6. thin-film transistor array base-plate according to claim 1, is characterized in that, described array base palte also comprises the insulating protective layer covered on described thin-film transistor.
7. a preparation method for the thin-film transistor array base-plate as described in as arbitrary in claim 1-6, is characterized in that, comprising:
First light shield technique is adopted to form gate electrode on the glass substrate;
Second light shield technique is adopted to be formed with active layer, amorphous silicon layer and ohmic contact layer;
The 3rd road light shield technique is adopted to form source electrode and drain electrode.
8. the preparation method of thin-film transistor array base-plate according to claim 7, is characterized in that, the method specifically comprises step:
S1, provide a glass substrate, this glass substrate is formed gate material rete;
S2, by first light shield technique, described gate material rete etching is formed the gate electrode of predetermined pattern;
S3, on the glass substrate of as above structure, form gate insulator, active layer material rete, amorphous silicon layer film layer and ohmic contact layer film layer successively;
S4, the active layer being formed predetermined pattern by second light shield technique on described gate insulator, amorphous silicon layer and ohmic contact layer; Wherein, described active layer, amorphous silicon layer and ohmic contact layer are formed by etching by described active layer material rete, amorphous silicon layer film layer and ohmic contact layer film layer respectively;
S5, on the glass substrate of as above structure, form source/drain electrode film layer;
S6, by the 3rd road light shield technique, described source/drain electrode film layer etching is formed source electrode and the drain electrode of predetermined pattern; Wherein, the partial etching between described source electrode and drain electrode of described ohmic contact layer is fallen, exposes described amorphous silicon layer.
9. the preparation method of thin-film transistor array base-plate according to claim 8, is characterized in that, the method also comprises step:
S7, the glass substrate of structure that obtains in step S6 form one deck insulating protective layer.
10. a display unit, is characterized in that, comprises the arbitrary described thin-film transistor array base-plate of claim 1-6.
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| US20030164910A1 (en) * | 2002-03-01 | 2003-09-04 | Shunpei Yamazaki | Liquid crystal display device |
| CN101064318A (en) * | 2006-04-24 | 2007-10-31 | 三星电子株式会社 | Thin film transistor array panel for display and manufacturing method of the same |
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Application publication date: 20160203 |