CN105304634B - Three-dimensional memory devices - Google Patents
Three-dimensional memory devices Download PDFInfo
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- CN105304634B CN105304634B CN201410342696.6A CN201410342696A CN105304634B CN 105304634 B CN105304634 B CN 105304634B CN 201410342696 A CN201410342696 A CN 201410342696A CN 105304634 B CN105304634 B CN 105304634B
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Abstract
The invention discloses a kind of three-dimensional memory devices.Three-dimensional memory devices include memory element area, the first hierarchic structure, the second hierarchic structure, the first conductive bar and the second conductive bar.Memory element area includes the first laminated construction and the second laminated construction.First laminated construction includes the first semiconductor bar, and the second laminated construction includes the second semiconductor bar.First hierarchic structure is located at the side in memory element area, and one end of the first semiconductor bar connects the first hierarchic structure.Second ladder structure bit connects the second hierarchic structure in the offside in memory element area, one end of the second semiconductor bar.First conductive bar is coupled to the first semiconductor bar through the first hierarchic structure.Second conductive bar passes through the second ladder structure couples to the second semiconductor bar.
Description
Technical field
The invention relates to a kind of storage device, and in particular to a kind of plane of the multiple storage units of setting
Three-dimensional memory devices.
Background technology
With the progress of ic manufacturing technology, the three-dimensional memory devices of the storage unit of the multiple planes of lamination are developed
Out, the storage volume of bigger is thereby obtained.
In a 3 D memory array, bit line is arranged to for accessing the different layers in storage array, therefore position
The configuration of line is to significantly affect the speed of reading and/or programmable memory.Therefore, memory reading can be improved by how providing one kind
And/or the storage device of program bandwidth, it is one of problem that current industry is endeavoured.
The content of the invention
The invention relates to a kind of three-dimensional memory devices, it is to improve storage that the conductive structure of this three-dimensional memory devices, which is set,
The reading of device and program bandwidth.
According to an embodiment, a kind of three dimensional integrated circuits, including memory element area, the first hierarchic structure, second-order are proposed
Terraced structure, the first conductive bar and the second conductive bar.Memory element area includes the first laminated construction and the second laminated construction.The
One laminated construction includes the first semiconductor bar, and the second laminated construction includes the second semiconductor bar.First hierarchic structure is positioned at storage
The side of element region, one end of the first semiconductor bar connect the first hierarchic structure.Second ladder structure bit is in memory element area
Offside, one end of the second semiconductor bar connect the second hierarchic structure.First conductive bar is coupled to first through the first hierarchic structure
Semiconductor bar.Second conductive bar passes through the second ladder structure couples to the second semiconductor bar.
More preferably understand to have to the above-mentioned and other aspect of the present invention, preferred embodiment cited below particularly, and coordinate institute
Accompanying drawings, are described in detail below：
Brief description of the drawings
Fig. 1 illustrates the schematic diagram of the three-dimensional memory devices according to an embodiment.
Fig. 2 illustrates the top view of three-dimensional memory devices.
Fig. 3 illustrates an example schematic diagram of the read operation of three-dimensional memory devices.
Fig. 4 illustrates the signal waveform figure for reading three-dimensional memory devices.
Another illustration that Fig. 5 illustrates the read operation of three-dimensional memory devices is intended to.
Fig. 6 illustrates to read the sensing amplifier of three-dimensional memory devices.
Fig. 7 illustrates the related signal oscillogram that sensing amplifier reads three-dimensional memory devices.
Fig. 8 illustrates the top view of the three-dimensional memory devices according to one embodiment of the invention.
【Symbol description】
100、800：Three-dimensional memory devices
102、802(1)、802(2)：Memory element area
104A、104B、804A、804B、804C：Hierarchic structure
106(1)-106(8)、806(1)-806(8)：Conductive bar
108(1)-108(8)：Laminated construction
114：Conductive plunger
112(1)-112(n)、116(1)-116(8)、118(1)-118(8)、120_odd、120_even：Conductive structure
702：Sensing amplifier
A1-A4、B1-B4：Semiconductor bar
ML1：The first metal layer
ML2：Second metal layer
ML3：3rd metal layer
SV：Sense signal
GV：Mask signal
MS：Memory cell string
P1：Pre-charging stage
P2：Setting and sensing stage
P3：Reduction phase
GSL：It is grounded selection line signal
CSL：Source electrode line signal
SSL_sel：Selected concatenation selection line signal
SSL_unsel：Unselected concatenation selection line signal
Channel：Memory cell channel voltage
ML3BL：The bit line signals of 3rd metal layer
WL_unsel：Unselected word lines signal
WL_sel：Selected wordline signal
BLCLAMP：Bit line reed position signal
CSL、SSL、BLSEL、BLC、BLK、BLC_I、LPC、BRST、BRSTN、STBN、CNB：Signal
Embodiment
It is to propose that embodiment is described in detail below, embodiment can't limit this hair only to illustrate as example
The bright scope to be protected.In addition, the schema in embodiment is to omit unnecessary element, to clearly show that the technology of the present invention is special
Point.
It please also refer to Fig. 1 and Fig. 2.Fig. 1 illustrates the schematic diagram of the three-dimensional memory devices 100 according to an embodiment.Fig. 2 is painted
Show the top view of three-dimensional memory devices 100.Three-dimensional memory devices 100 include memory element area 102, hierarchic structure 104A, 104B
And multiple conductive bars 106 (1) -106 (8).Defined in memory element area 102 multiple storage units (memory cell), often
One conductive bar 106 (1) -106 (8) is for example located at line (bit line, BL) respectively as a memory cell string.
Memory element area 102 includes being discharged into the laminated construction 108 (1) -108 (8) of X-direction extension more.The lamination of odd row
Structure 108 (1), 108 (3), 108 (5), the laminated construction 108 (2) of 108 (7) and even rows, 108 (4), 108 (6), 108 (8)
It is staggered.Laminated construction 108 (1) and laminated construction 108 (2) parallel and adjacent to；Laminated construction 108 (3) and laminated construction 108
(4) parallel and adjacent to；Laminated construction 108 (5) and laminated construction 108 (6) parallel and adjacent to；Laminated construction 108 (7) and lamination knot
Structure 108 (8) parallel and adjacent to.Laminated construction 108 (1) -108 (8) each includes multiple semiconductor bar (such as lamination knots separated from each other
The semiconductor bar B1-B4 in semiconductor bar A1-A4, laminated construction 108 (2) in structure 108 (1)).As shown in Figure 1, semiconductor bar
A1-A4 is located at different layers and is separated with dielectric strips, and semiconductor bar B1-B4 is located at different layers and is separated with dielectric strips.In order to clear
Represent the structure of the storage device of embodiment, Fig. 1 does not show the part of dielectric strips.
112 (1) -112 (n) of conductive structure is arranged at the side wall of laminated construction 108 (1) -108 (8), and mutual along the Z direction
Mutually dividually configure, using for example as the wordline (word line, WL) of three-dimensional memory devices 100, wherein n is just whole more than 1
Number.
Hierarchic structure 104A is located at the side in memory element area 102, the laminated construction 108 (1) of odd row, 108 (3), 108
(5), one end connection hierarchic structure 104A of the semiconductor bar of 108 (7).Hierarchic structure 104B is located at pair in memory element area 102
Side, the laminated construction 108 (2) of even rows, 108 (4), 108 (6), 108 (8) semiconductor bar one end connection hierarchic structure
104B。
Conductive bar 106 (1), 106 (3), 106 (5), 106 (7) and conductive bar 106 (2), 106 (4), 106 (6), 106 (8)
It is staggered.Conductive bar 106 (1), 106 (3), 106 (5), 106 (7) pass through the lamination that hierarchic structure 104A is coupled to odd row
Structure 108 (1), 108 (3), 108 (5), the semiconductor bar of 108 (7).In the example in fig 1, conductive bar 106 (1), 106 (3),
The 3rd metal layer ML3 of 106 (5), 106 (7) positions above laminated construction 108 (1) -108 (8), and conductive plunger is passed through respectively
(plug) 114 different layers for being connected to hierarchic structure 104A, be electrically connected to laminated construction 108 (1), 108 (3), 108 (5),
The semiconductor bar of different layers in 108 (7).Similarly, conductive bar 106 (2), 106 (4), 106 (6), 106 (8) positions are in the 3rd metal
Layer ML3, and it is respectively coupled to different layers in laminated construction 108 (2), 108 (4), 108 (6), 108 (8) through hierarchic structure 104B
Semiconductor bar.
In the example in fig 1, the semiconductor bar of the parallel each lamination 108 (1) -108 (8) of conductive bar 106 (1) -106 (8).Lead
Electric bar 106 (1), 106 (3), 106 (5), 106 (7) are across memory element area 102 and the top of hierarchic structure 104B, and and rank
Terraced structure 104B is electrically isolated.Conductive bar 106 (2), 106 (4), 106 (6), 106 (8) are across memory element area 102 and ladder
The top of structure 104A, and electrically isolated with hierarchic structure 104A.The two adjacent semiconductor bars positioned at identical layer are (as being located at phase
With the semiconductor bar B1 of semiconductor bar A1 and the laminated construction 108 (2) of the laminated construction 108 (1) of layer) spacing (pitch) with
The spacing of two neighbouring conductive bars (such as conductive bar 106 (1) and 106 (2)) is equal.Compared to conventional three-dimensional memory construction, sheet
The three-dimensional storage device of inventive embodiments can provide larger reading and program bandwidth.
In the example in fig 1, conductive structure 116 (1), 116 (3), 116 (5), 116 (7) are respectively arranged at odd row lamination
Structure 108 (1), 108 (3), 108 (5), 108 (7) semiconductor bar side wall on and adjacent stepchain structure 104A, to conduct
Odd row laminated construction 108 (1), 108 (3), 108 (5), the concatenation selection line of 108 (7).Similarly, conductive structure 116 (2),
116 (4), 116 (6), 116 (8) are respectively arranged at even rows laminated construction 108 (2), 108 (4), 108 (6), 108 (8) are partly led
On the side wall of body bar and adjacent stepchain structure 104B, to as even rows laminated construction 108 (2), 108 (4), 108 (6), 108
(8) concatenation selection line.In other words, in the example in fig 1, recto is in the opposite direction with the selection grid that concatenates of verso
Set.
Conductive structure 116 (1) -116 (8) is electrically connected to the string that the first metal layer ML1 and second metal layer ML2 is formed
Selection line is connect, selection line is concatenated with what second metal layer ML2 was formed to the first metal layer ML1 by providing voltage, can control
The semiconductor bar of corresponding laminated construction is selection (selected) state or non-selected (unselected) state.
Conductive structure 118 (1), 118 (3), 118 (5), 118 (7) be arranged at odd row laminated construction 108 (1), 108 (3),
108 (5), 108 (7) semiconductor bar side wall on and positioned at adjacent stepchain structure 104B position, to as laminated construction
108 (1), 108 (3), 108 (5), the source electrode line of 108 (7).Laminated construction 108 (1), 108 (3), 108 (5), 108 (7) are partly led
One end of body bar is to terminate at conductive structure 118 (1), 118 (3), 118 (5), 118 (7).Similarly, conductive structure 118 (2),
118 (4), 118 (6), 118 (8) are arranged at even rows laminated construction 108 (2), 108 (4), 108 (6), the semiconductor bar of 108 (8)
Side wall on and positioned at adjacent stepchain structure 104A position, to as laminated construction 108 (2), 108 (4), 108 (6), 108
(8) source electrode line.Laminated construction 108 (2), 108 (4), 108 (6), one end of semiconductor bar of 108 (8) are to terminate at conductive knot
Structure 118 (2), 118 (4), 118 (6), 118 (8).
Conductive structure 120_oddIt is arranged at odd row laminated construction 108 (1), 108 (3), 108 (5), the semiconductor of 108 (7)
On the side wall of bar, to as laminated construction 108 (1), 108 (3), 108 (5), 108 (7) ground connection selection line.Similarly, lead
Electric structure 120_evenBe arranged at even rows laminated construction 108 (2), 108 (4), 108 (6), 108 (8) semiconductor bar side wall
On, to as laminated construction 108 (2), 108 (4), 108 (6), 108 (8) ground connection selection line.In one embodiment, as
The conductive structure for being grounded selection line is located at as the conductive structure for concatenating selection line and as between the conductive structure of source electrode line, and
The neighbouring conductive structure as source electrode line.
It will be appreciated that the columns of stratum's number of the number of rows of the laminated construction of above-described embodiment, semiconductor bar, wordline, leading
Number of electric bar etc. is not limited to number as shown in Figure 1, and visual actual state is respectively designed to more or fewer numbers.This
Outside, the conductive material in above-described embodiment may include metal, polysilicon, metal silicide or other suitable materials.Dielectric material
Material may include oxide or silicide, such as silica, silicon nitride or silicon oxynitride, or other suitable materials.
Fig. 3 is refer to, it illustrates an example of the read operation of three-dimensional memory devices 100.In the example in figure 3, can first select
Select a recto.By apply sensing signal SV to be used as the conductive bar 106 (1) of bit line, 106 (3), 106 (5), 106 (7) with
The storage unit of K layers (K=4 in this example) in storage device 100 is sensed, and by applying mask signal GV (such as ground voltage) extremely
Conductive bar 106 (2), 106 (4), 106 (6), 106 (8) are to be masked it (shielded).Then, the even number of selection is opened
Page.In the present embodiment, sensing operation can carry out in a wordline sets waveform, therefore substantially be to read two in a waveform
Page, and then double memory reading speed.
Fig. 4 illustrates an example for the signal waveform figure for reading three-dimensional memory devices 100.In pre-charging stage P1, ground connection selection
Line signal (GSL) is set to high voltage, and source electrode line signal (CSL) is set to ground voltage, and concatenates selection line signal
(SSL_sel) and unselected concatenation selection line signal (SSL_unsel) high voltage is set to set memory cell channel voltage
(Channel) it is ground connection level.Setting and sensing stage P2, selected string selection line (SSL_sel) be applied through (pass)
Voltage (about 6 volts)；Unselected string selection line signal (SSL_unsel) it is set to low-voltage (about -2 volts)；3rd metal layer
Bit line signals (ML3BL) be set to sensing voltage (about 1 volt)；Unselected word lines signal (WL_unsel) be set to pass through
Voltage (about 6 volts)；Selected wordline signal (WL_sel) it is set to low-voltage (being approximately less than 0 volt).By applying bit line reed
Position signal (BLCLAMP), the data being stored in storage unit can pass through sensing circuit and are sensed.Set bit line and sensing rank
Section for example repeats the reading of two pages.In reduction phase P3, memory cell channel is discharged to be reduced (recovery)
To ground voltage.It is understood that the oscillogram of Fig. 4 is only as purposes of discussion, and it is not used to the limitation present invention.
Fig. 5 is refer to, it illustrates another illustration of the read operation of three-dimensional memory devices 100 and is intended to.In the example of Fig. 5
In, can simultaneous selection page two to be read out, wherein one page is recto, and another page is verso.Read to double memory
Speed, bit line and ground connection selection line are set, and all concatenation selection lines are closed.
It refer to Fig. 6 and Fig. 7.Fig. 6 illustrates to read an example of the sensing amplifier 702 of three-dimensional memory devices 100.Figure
7 illustrate an example that sensing amplifier 702 reads the related signal oscillogram of three-dimensional memory devices 100.As shown in fig. 7, three-dimensional is deposited
The related signal of storage device 100 include signal CSL, SSL, BLSEL, BLC, BLK, BLC_I, LPC, BRST, BRSTN, STBN,
CNB.Sensing amplifier 702 is operated by above-mentioned signal with performing traditional memory sensing, therefore details are not described herein again that sensing is put
The details of operation of big device 702.For a memory cell string MS of three-dimensional memory devices 100, sensing amplifier 702 performs electric current sense
Survey to read the data stored by particular memory location.
Fig. 8 illustrates the top view of the three-dimensional memory devices 800 according to one embodiment of the invention.Three-dimensional memory devices 800 wrap
Containing multiple memory element areas.As shown in figure 8, three-dimensional memory devices 800 include multiple memory element areas 802 (1) and 802 (2).
Memory element area 802 (1), 802 (2) and multiple hierarchic structure 804A, 804B, 804C are staggered.Memory element area 802 (1)
And in 802 (2) laminated construction setting it is identical with previous embodiment, so it will not be repeated.Conductive bar 806 (1) -806 (8) is with depositing
The laminated construction stored up in element region 802A and 802B is parallel.Conductive bar 806 (1), 806 (3), 806 (5), 806 (7) and ladder
Structure 804A and 804C through conductive plug be electrically connected, and with hierarchic structure 804B electrically isolate (not with hierarchic structure 804B
Connection).Conductive bar 806 (2), 806 (4), 806 (6), 806 (8) are electrically connected with hierarchic structure 804B through conductive plug, and
Electrically isolate and (be not connected with hierarchic structure 804A, 804C) with hierarchic structure 804A, 804C.In other words, conductive bar 806 (1),
806 (3), 806 (5), 806 (7) are electrically connected to the hierarchic structure of odd column.Conductive bar 806 (2), 806 (4), 806 (6), 806
(8) it is electrically connected to the hierarchic structure of even column.In this embodiment, the position of each hierarchic structure 804A-804C can be in X direction
Translation.For example, translation can be used to upset (shift-scamble) design with average bit line inductance capacitance.
According to above-mentioned, the three-dimensional memory devices of the embodiment of the present invention are to provide a bit line design for possessing intensive spacing.By
In the quantity increase of bit line, therefore can be carried compared to conventional three-dimensional memory construction, the three-dimensional storage device of the embodiment of the present invention
For improved reading and program bandwidth.
In conclusion although the present invention has been disclosed by way of example above, it is not intended to limit the present invention..Institute of the present invention
Belong in technical field and have usually intellectual, without departing from the spirit and scope of the present invention, when various changes and profit can be made
Decorations.Therefore, subject to protection scope of the present invention ought be defined depending on appended claims scope.
Claims (8)
1. a kind of three-dimensional memory devices, including：
One memory element area, including：
One first laminated construction, including one first semiconductor bar；And
One second laminated construction, including one second semiconductor bar, second laminated construction is parallel with first laminated construction and phase
It is adjacent；
One first hierarchic structure, the side outside the memory element area, one end of first semiconductor bar connect first rank
Terraced structure；
One second hierarchic structure, the offside outside the memory element area, one end of second semiconductor bar connect the second-order
Terraced structure；
One first conductive bar, first semiconductor bar is coupled to through first hierarchic structure；And
One second conductive bar, through the second ladder structure couples to second semiconductor bar；
Wherein between the spacing of first semiconductor bar and second semiconductor bar and first conductive bar and second conductive bar
Away from equal.
2. three-dimensional memory devices according to claim 1, wherein the memory element area further include：
Multiple first laminated construction, including multiple first semiconductor bars separated from each other；And
Multiple second laminated construction, including multiple second semiconductor bars separated from each other, these first laminated construction and this
A little second laminated construction are staggered.
3. three-dimensional memory devices according to claim 2, including：
Multiple first conductive bars, these first semiconductor bars of different layers are respectively connected to through first hierarchic structure；With
And
Multiple second conductive bars, these second semiconductor bars of different layers are respectively connected to through second hierarchic structure, this
A little first conductive bars are staggered with these second conductive bars.
4. three-dimensional memory devices according to claim 1, wherein first conductive bar are across the memory element area and are somebody's turn to do
The top of second hierarchic structure, and electrically isolated with second hierarchic structure；Second conductive bar across the memory element area with
And the top of first hierarchic structure, and electrically isolated with first hierarchic structure.
5. a kind of three-dimensional memory devices, including：
The one first memory element area in multiple memory element areas, wherein these memory element areas includes：
One first laminated construction, including one first semiconductor bar；And
One second laminated construction, including one second semiconductor bar, second laminated construction is parallel with first laminated construction and phase
It is adjacent；
Multiple hierarchic structures, these hierarchic structures are staggered with these memory element areas；
One first conductive bar, first semiconductor bar is coupled to through one first hierarchic structure of these hierarchic structures, wherein should
First conductive bar is electrically connected to these hierarchic structures of odd column；And
One second conductive bar, through these hierarchic structures one second ladder structure couples to second semiconductor bar, wherein should
Second conductive bar is electrically connected to these hierarchic structures of even column；
Wherein between the spacing of first semiconductor bar and second semiconductor bar and first conductive bar and second conductive bar
Away from equal.
6. three-dimensional memory devices according to claim 5, wherein the first memory element area further include：
Multiple first laminated construction, including multiple first semiconductor bars separated from each other；And
Multiple second laminated construction, including multiple second semiconductor bars separated from each other, these first laminated construction and this
A little second laminated construction are staggered.
7. three-dimensional memory devices according to claim 6, including：
Multiple first conductive bars, these first semiconductor bars of different layers are respectively connected to through first hierarchic structure；With
And
Multiple second conductive bars, these second semiconductor bars of different layers are respectively connected to through second hierarchic structure, this
A little first conductive bars are staggered with these second conductive bars.
8. three-dimensional memory devices according to claim 5, wherein these hierarchic structures of first conductive bar and even column
Electrically isolate；These hierarchic structures of second conductive bar and its ordered series of numbers electrically isolate.
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| US20140198576A1 (en) * | 2013-01-16 | 2014-07-17 | Macronix International Co, Ltd. | Programming technique for reducing program disturb in stacked memory structures |
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