CN105304594A - Interposer and method of manufacturing the same - Google Patents
Interposer and method of manufacturing the same Download PDFInfo
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- CN105304594A CN105304594A CN201410372802.5A CN201410372802A CN105304594A CN 105304594 A CN105304594 A CN 105304594A CN 201410372802 A CN201410372802 A CN 201410372802A CN 105304594 A CN105304594 A CN 105304594A
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- 238000004519 manufacturing process Methods 0.000 title description 2
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 238000000034 method Methods 0.000 claims abstract description 35
- 239000010410 layer Substances 0.000 claims description 273
- 239000011241 protective layer Substances 0.000 claims description 48
- 230000004888 barrier function Effects 0.000 claims description 16
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 4
- 239000011810 insulating material Substances 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 229910001069 Ti alloy Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- UHOVQNZJYSORNB-UHFFFAOYSA-N monobenzene Natural products C1=CC=CC=C1 UHOVQNZJYSORNB-UHFFFAOYSA-N 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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Abstract
An interposer and a method for fabricating the same, the interposer comprising: the substrate body is provided with a first surface and a second surface which are opposite, and a substrate body cavity and a plurality of conductive through holes, wherein the substrate body cavity and the conductive through holes penetrate through the first surface and the second surface; a first dielectric layer formed on the first surface and exposing the conductive through holes; a circuit layer formed on the first dielectric layer and electrically connected to the conductive through holes; a plurality of electrical connection pads formed on the second surface and electrically connected to the conductive through holes; and a second dielectric layer formed on the second surface and correspondingly exposing the electrical connection pads. The cavity of the substrate body can release or block thermal expansion strain and stress, and greatly reduces the warping phenomenon of the intermediate plate.
Description
Technical field
The invention provides a kind of intermediate plate and method for making thereof, the espespecially a kind of intermediate plate with substrate body hole or dielectric layer opening and method for making thereof that can prevent warpage.
Background technology
Because wafer function is increasingly powerful, cause the day by day intensive and high-density wiring of conductive projection, then create the technology of various intermediate plate.
Please refer to Fig. 1, it is the cutaway view of existing intermediate plate 1, and this intermediate plate 1 comprises substrate body 10, first dielectric layer 13, line layer 14, insulating protective layer 15, multiple electric connection pad 19 and the second dielectric layer 18.Such as the substrate body 10 of silicon has relative first surface 10a and second surface 10b, and there are multiple conductive through holes 11 of through this first surface 10a and second surface 10b, and be formed with insulating barrier 12 between those conductive through holes 11 and this substrate body 10.
First dielectric layer 13 as above to be formed on this first surface 10a and to expose those conductive through holes 11, and this line layer 14 to be formed on this first surface 10a and the first dielectric layer 13 and to have connected circuit 141 and electrical contact 142, this circuit 141 is electrically connected those conductive through holes 11, and this first dielectric layer 13 and line layer 14 are formed with the insulating protective layer 15 exposing this electrical contact 142, and this electrical contact 142 can be formed such as projection underlying metal layer (underbumpmetallurgy, be called for short UBM) metal level 16, this metal level 16 can be formed with the conductive projection 17 of reflow process.
As above can such as multiple electric connection pads 19 of projection underlying metal layer are formed on this second surface 10b and be electrically connected those conductive through holes 11.And the second dielectric layer 18 as above is formed on this second surface 10b and correspondence exposes outside those electric connection pads 19, and those electric connection pads 19 can be formed with the conductive projection 17 of reflow process.
When forming existing intermediate plate, owing to often using high temperature process (as reflow), and the thermal coefficient of expansion (Coefficientofthermalexpansion of layers of material because of intermediate plate, CTE) difference is very large (such as: the CTE of the silicon of substrate body is 2.6ppm/ DEG C, the CTE of the silicon dioxide of insulating barrier is 0.5ppm/ DEG C, the CTE of the copper of conductive through holes and line layer is the polyimides (polyimide of 16.7ppm/ DEG C and the first dielectric layer and the second dielectric layer, or ring benzene butylene (Bis-Benzo-Cyclo-Butene PI), BCB) CTE be respectively 35 and 3ppm/ DEG C), therefore in high temperature process and after cooling, often because thermal expansion inequality causes the problem of intermediate plate warpage, thus make successive process be difficult to contraposition, and reduce the production yield of intermediate plate widely.
Summary of the invention
Because the disappearance of above-mentioned prior art, object of the present invention, for providing a kind of intermediate plate and method for making thereof, greatly reduces the warping phenomenon of intermediate plate.
Intermediate plate of the present invention comprises: have relative first surface and second surface and have the substrate body of substrate body hole and multiple conductive through holes, this substrate body hole and conductive through holes this first surface through and second surface; To be formed on this first surface and to expose outside the first dielectric layer of those conductive through holes; To be formed on this first dielectric layer and to be electrically connected the line layer of those conductive through holes; To be formed on this second surface and to be electrically connected multiple electric connection pads of those conductive through holes; And to be formed on this second surface and correspondence exposes outside the second dielectric layer of those electric connection pads.
The present invention also provides a kind of intermediate plate, comprising: have relative first surface and second surface and have the substrate body of multiple conductive through holes of this first surface through and second surface; Being formed on this first surface and exposing outside the first dielectric layer of those conductive through holes, this first dielectric layer has the first dielectric layer opening run through; To be formed on this first dielectric layer and to be electrically connected the line layer of those conductive through holes; To be formed on this second surface and to be electrically connected multiple electric connection pads of those conductive through holes; And to be formed on this second surface and correspondence exposes outside the second dielectric layer of those electric connection pads.
The present invention provides again a kind of intermediate plate, comprising: have relative first surface and second surface and have the substrate body of multiple conductive through holes of this first surface through and second surface; To be formed on this first surface and to expose outside the first dielectric layer of those conductive through holes; To be formed on this first dielectric layer and to be electrically connected the line layer of those conductive through holes; To be formed on this second surface and to be electrically connected multiple electric connection pads of those conductive through holes; And to be formed on this second surface and correspondence exposes outside the second dielectric layer of those electric connection pads, this second dielectric layer also has the second dielectric layer opening run through.
The present invention provides again a kind of method for making of intermediate plate, comprising: this first surface in the substrate body with relative first surface and second surface forms multiple first groove and the second groove, and forms conductive through holes in those first grooves each; On the first surface of this substrate body, form line layer and the first dielectric layer, this line layer to be formed on this first surface and to be electrically connected those conductive through holes, and this first dielectric layer to be formed on this first surface and to expose outside this line layer; The segment thickness of this substrate body is removed, to expose one end of those second grooves and conductive through holes from the second surface sidesway of this substrate body; And on this second surface, form the second dielectric layer and the multiple electric connection pads being electrically connected those conductive through holes, and this second dielectric layer correspondence exposes outside those electric connection pads, and those second grooves form the substrate body hole of this first surface through and second surface.
The present invention also provides a kind of method for making of intermediate plate, comprising: the first surface in the substrate body with relative first surface and second surface forms multiple first groove, and forms conductive through holes in those first grooves each; Line layer and the first dielectric layer is formed on the first surface of this substrate body, this line layer to be formed on this first surface and to be electrically connected those conductive through holes, this first dielectric layer to be formed on this first surface and to expose outside this line layer, and this first dielectric layer has the first dielectric layer opening run through; The segment thickness of this substrate body is removed, to expose one end of this conductive through holes from the second surface sidesway of this substrate body; And on this second surface, form the second dielectric layer and the multiple electric connection pads being electrically connected those conductive through holes, and this second dielectric layer correspondence exposes outside those electric connection pads.
The present invention reoffers a kind of method for making of intermediate plate, comprising: the first surface in the substrate body with relative first surface and second surface forms multiple first groove, and forms conductive through holes in each this first groove; On the first surface of this substrate body, form line layer and the first dielectric layer, this line layer to be formed on this first surface and to be electrically connected those conductive through holes, and this first dielectric layer to be formed on this first surface and to expose outside this line layer; The segment thickness of this substrate body is removed, to expose one end of those conductive through holes from the second surface sidesway of this substrate body; And on this second surface, form the second dielectric layer and the multiple electric connection pads being electrically connected those conductive through holes, and this second dielectric layer correspondence exposes outside those electric connection pads, this second dielectric layer has the second dielectric layer opening run through.
Intermediate plate of the present invention and method for making thereof are by the first surface of through substrate body and the substrate body hole of second surface, the first dielectric layer opening running through the first dielectric layer, opening or run through the second dielectric layer opening of the second dielectric layer and avoid too large the caused thermal expansion strain of the thermal expansion coefficient difference because of layers of material of prior art and stress problem, therefore the present invention greatly can reduce the warping phenomenon of intermediate plate.
Accompanying drawing explanation
Fig. 1 is the cutaway view of existing intermediate plate.
Fig. 2 A to Fig. 2 D is the cutaway view of an embodiment of the method for making of intermediate plate of the present invention, and Fig. 2 D ' is the vertical view of Fig. 2 D, and Fig. 2 D-1 to Fig. 2 D-4 is the different embodiments of Fig. 2 D.
Fig. 3 A to Fig. 3 D is the cutaway view of another embodiment of the method for making of intermediate plate of the present invention, and Fig. 3 D-1 to Fig. 3 D-3 is the different embodiments of Fig. 3 D.
Symbol description
1,2 intermediate plates
10,20 substrate body
10a, 20a first surface
10b, 20b second surface
11,21 conductive through holes
12,22 insulating barriers
13,23 first dielectric layers
14,24 line layers
141,241 circuits
142,242 electrical contacts
15,25 insulating protective layers
16,26 metal levels
17,27 conductive projections
18,28 second dielectric layers
19,29 electric connection pads
201 first grooves
202 second grooves
204 substrate body holes
231 first dielectric layer openings
232 openings
251 insulating protective layer openings
281 second dielectric layer openings
AA ' line.
Embodiment
By particular specific embodiment, embodiments of the present invention are described below, those skilled in the art can understand other advantages of the present invention and effect easily by content disclosed in the present specification.The present invention also can be implemented by other different specific embodiment or be applied, and the every details in this specification also based on different viewpoints and application, can carry out various modification and change under not departing from spirit of the present invention.
Please refer to Fig. 2 A to Fig. 2 D, it is the cutaway view of an embodiment of the method for making of intermediate plate of the present invention.
As shown in Figure 2 A, first the method for making of intermediate plate of the present invention forms multiple first groove 201 and the second groove 202 in this first surface 20a of the substrate body 20 with relative first surface 20a and second surface 20b, and forms conductive through holes 21 in each this first groove 201.
Specifically but non-limiting, the material of this substrate body 20 generally can be the semiconductor as silicon, but also can need according to design and use insulating material or dielectric material to make, and the present invention also can before those conductive through holes 21 of formation, the insulating barrier 22 that can be silicon dioxide is formed in those the first groove 201 surfaces, to make this insulating barrier 22 between those conductive through holes 21 and this substrate body 20, and it is such as that the conductive layer (not shown) of titanium/copper alloy is in this insulating barrier 22 surface that the present invention still can form one after forming this insulating barrier 22, to make this conductive layer between those conductive through holes 21 and this insulating barriers 22, in addition, those second grooves 202 can need according to design and be distributed in this substrate body 20 beyond those first grooves 201, to discharge thermal expansion strain and the stress of this substrate body 20, particularly, those second grooves 202 can be distributed in this substrate body 20 respectively between this first groove 201, and those second grooves 202 can be strip, blocked with the thermal expansion of the material making substrate body 20, thus reduce the warping phenomenon of intermediate plate.
Afterwards as shown in Figure 2 B, formation first dielectric layer 23 on the first surface 20a of this substrate body 20, and on this first dielectric layer 23, form the line layer 24 being electrically connected those conductive through holes 21, this first dielectric layer 23 to be formed on this first surface 20a and to expose outside this line layer 24, and this first dielectric layer 23 has the first dielectric layer opening 231 running through this first dielectric layer 23.
In details of the words but non-limiting, when this substrate body 20 is semiconductor, this the first dielectric layer 23 can be formed on this first surface 20a and correspondence exposes those conductive through holes 21, the circuit 241 being electrically connected those conductive through holes 21 is formed afterwards on those conductive through holes 21, and on this first dielectric layer 23, form the electrical contact 242 be connected with circuit 241, or any other applicable process strategies can be taked to make this line layer 24 be formed on this first surface 20a and to be electrically connected those conductive through holes 21, and this first dielectric layer 23 to be formed on this first surface 20a and to expose outside this electrical contact 242 of this line layer 24.In addition, this first dielectric layer 23 can have the first dielectric layer opening 231 running through this first dielectric layer 23, to discharge thermal expansion strain and the stress of this first dielectric layer 23, particularly, this first dielectric layer opening 231 can be distributed in this first dielectric layer 23 beyond each this conductive through holes 21 upright projection, and respectively this first dielectric layer opening 231 can be strip, blocked with the thermal expansion of the material making the first dielectric layer 23, thus reduce the warping phenomenon of intermediate plate, and more particularly, respectively this first dielectric layer opening 231 may correspond to and exposes respectively this second groove 202.In addition, the correspondence that also has this first dielectric layer 23 exposes the opening 232 of this circuit 241, particularly, this opening 232 correspondence exposes the bottom surface of this circuit 241 and does not expose the side of this circuit 241, and this opening 232 also can make the thermal expansion of the material of the first dielectric layer 23 be blocked.
Then as shown in Figure 2 C, the insulating protective layer 25 exposing this electrical contact 242 is formed on this first dielectric layer 23 and line layer 24, and this insulating protective layer 25 can have the insulating protective layer opening 251 running through this insulating protective layer 25, to discharge thermal expansion strain and the stress of this insulating protective layer 25, further, this insulating protective layer opening 251 of part may correspond to and exposes this first dielectric layer opening 251 and electrical contact 242, it is such as projection underlying metal layer (underbumpmetallurgy that this electrical contact 242 exposed is formed, UBM) metal level 26, and on this metal level 26, form conductive projection 27 subsequently and give reflow process.
In addition, the segment thickness of this substrate body 20 is removed from the second surface 20b sidesway of this substrate body 20, to expose one end of those second grooves 202 and conductive through holes 21, and when the surface of those the first grooves 201 be formed this insulating barrier 22, this step also removes this insulating barrier 22 be positioned at bottom those first grooves 201, now, those second grooves 201 form the substrate body hole 204 of through this first surface 20a and second surface 20b.
Finally, as shown in Figure 2 D, formation second dielectric layer 28 and the multiple electric connection pads 29 (such as, projection underlying metal layer) being electrically connected those conductive through holes 21 on this second surface 20b, and this second dielectric layer 28 correspondence exposes outside those electric connection pads 29.
In addition, this second dielectric layer 28 can have the second dielectric layer opening 281 running through this second dielectric layer 28, to discharge thermal expansion strain and the stress of this second dielectric layer 28, particularly, this second dielectric layer opening 281 can be distributed in this second dielectric layer 28 beyond each this conductive through holes 21 upright projection, and respectively this second dielectric layer opening 281 can be strip, blocked with the thermal expansion of the material making this second dielectric layer 28, thus reduce the warping phenomenon of intermediate plate, and more particularly, respectively this second dielectric layer opening 281 may correspond to and exposes respectively this substrate body hole 204.
In addition, the present invention can form conductive projection 27 and give reflow process on electric connection pad 29.
In addition, also another line layer (not shown) can be formed on this second dielectric layer 28, to be electrically connected those electric connection pads 29.
Referring again to Fig. 2 D and Fig. 2 D ', it is the cutaway view of an embodiment of intermediate plate 2 of the present invention, and Fig. 2 D ' is the vertical view of intermediate plate 2 of the present invention, and Fig. 2 D is the cutaway view of the line AA ' along Fig. 2 D '.
Intermediate plate 2 of the present invention comprises substrate body 20, first dielectric layer 23, line layer 24, multiple electric connection pad 29 and the second dielectric layer 28.Substrate body 20 as above has relative first surface 20a and second surface 20b, and this substrate body 20 has substrate body hole 204 and multiple conductive through holes 201, this substrate body hole 204 and conductive through holes 201 this first surface through 20a and second surface 20b.
In details of the words but non-limiting, this substrate body 20 generally can be the semiconductor as silicon, but also can use insulating material or dielectric material, and the present invention also can be formed between those conductive through holes 201 and this substrate body 20 be such as the insulating barrier 22 of silicon dioxide, and between a little conductive through holes 21 and this insulating barrier 22, also can form the conductive layer that is such as titanium/copper alloy, particularly, this substrate body hole 204 can be distributed in this substrate body 20 between those conductive through holes 201 each, and respectively this substrate body hole 204 can be strip.
Line layer 24 as above to be formed on this first dielectric layer 23 and to be electrically connected those conductive through holes 21, and this line layer 24 can have connected circuit 241 and electrical contact 242.In details of the words but non-limiting, when the material of this substrate body 20 is semiconductor, this first dielectric layer 23 is formed on this first surface 20a and correspondence exposes those conductive through holes 21, and this circuit 241 can be formed in be electrically connected those conductive through holes 21 and to extend on this first dielectric layer 23 on those conductive through holes 21, and this electrical contact 242 to be formed on this first dielectric layer 23 and to be connected with this circuit 241.In addition, this first dielectric layer 23 has the first dielectric layer opening 231 running through this first dielectric layer 23, particularly, this first dielectric layer opening 231 can be distributed in this first dielectric layer 23 beyond each this conductive through holes 21 upright projection, and respectively this first dielectric layer opening 231 can be strip as Suo Shi Fig. 2 D ', and more particularly, respectively this first dielectric layer opening 231 may correspond to and exposes respectively this substrate body hole 204.Moreover this first dielectric layer 23 also has the opening 232 that correspondence exposes this circuit 241, particularly, this opening 232 correspondence exposes the bottom surface of this circuit 241 and does not expose the side of this circuit 241.
As above can such as multiple electric connection pads 29 of projection underlying metal layer are formed on this second surface 20b and be electrically connected those conductive through holes 21.And the second dielectric layer 28 as above is formed on this second surface 20b and correspondence exposes outside those electric connection pads 29, and this second dielectric layer 28 can have the second dielectric layer opening 281 running through this second dielectric layer 28, and the distribution of this second dielectric layer opening 281, other features and function class are similar to this first dielectric layer opening 231, do not repeat them here.
In addition; the present invention can form the insulating protective layer 25 exposing this electrical contact 242 on this first dielectric layer 23 and line layer 24; and this insulating protective layer 25 can have the insulating protective layer opening 251 running through this insulating protective layer 25; further; this insulating protective layer opening 251 may correspond to and exposes this first dielectric layer opening 251, and this insulating protective layer opening 251 of part is for blocking thermal expansion phenomenon.
In addition, it is such as the metal level 26 of projection underlying metal layer that this electrical contact 242 can be formed, and this metal level 26 and those electric connection pads 29 can be formed with the conductive projection 27 of reflow process.
In intermediate plate of the present invention, this line layer 24 can be formed on this first dielectric layer 23, and connect those conductive through holes 21 that this first dielectric layer 23 exposes, and also can comprise another line layer (not shown), to be formed on this second dielectric layer 28 and to be electrically connected those electric connection pads 29.
Please refer to Fig. 2 D-1 to Fig. 2 D-4, it is the cutaway view of the different embodiments of intermediate plate 2 of the present invention.
As shown in Fig. 2 D-1, the difference of itself and Fig. 2 D is, Fig. 2 D-1 does not have the first dielectric layer opening 231, insulating protective layer opening 251 and the second dielectric layer opening 281.
As shown in Fig. 2 D-2, the difference of itself and Fig. 2 D is, Fig. 2 D-2 does not have the second dielectric layer opening 281.
As shown in Fig. 2 D-3, the difference of itself and Fig. 2 D is, Fig. 2 D-3 does not have the first dielectric layer opening 231, opening 232 and insulating protective layer opening 251.
As shown in Fig. 2 D-4, the difference of itself and Fig. 2 D is, the substrate body 20 of Fig. 2 D-4 is insulating material or dielectric material, therefore, this line layer 24 can be formed directly on this first surface 20a, and this dielectric layer 23 is formed on this first surface 20a and line layer 24 and correspondence exposes outside this electrical contact 242, and the present embodiment also can optionally be selected formed or do not form this substrate body hole 204, first dielectric layer opening 231, opening 232 or the second dielectric layer opening 281.
Please refer to Fig. 3 A to Fig. 3 D, it is the cutaway view of another embodiment of the method for making of intermediate plate of the present invention, the difference of itself and Fig. 2 A to Fig. 2 D is, the first surface 20a of the substrate body 20 of Fig. 3 A to Fig. 3 D only forms multiple first groove 201, therefore in time removing the segment thickness of this substrate body 20a, only expose one end of those conductive through holes 21, and not there is this substrate body hole 204.
Please refer to Fig. 3 D-1 to Fig. 3 D-3, it is the cut-away view of another embodiment of intermediate plate 2 of the present invention.
As shown in Fig. 3 D-1, the difference of itself and Fig. 3 D is, Fig. 3 D-1 has the first dielectric layer opening 231 and insulating protective layer opening 251, and does not have the second dielectric layer opening 281.
As shown in Fig. 3 D-2, the difference of itself and Fig. 3 D is, Fig. 3 D-1 does not have the first dielectric layer opening 231, opening 232 and insulating protective layer opening 251.
As shown in Fig. 3 D-3, the difference of itself and Fig. 3 D is, the substrate body 20 of Fig. 3 D-3 is insulating material or dielectric material, therefore, this line layer 24 can be formed directly on this first surface 20a, and this dielectric layer 23 is formed on this first surface 20a and line layer 24 and correspondence exposes outside those electrical contacts 242, and the present embodiment also can optionally be selected formed or do not form this substrate body hole 204, first dielectric layer opening 231, opening 232 or the second dielectric layer opening 281.
In intermediate plate of the present invention, this line layer 24 can be formed on this first dielectric layer 23, and connect those conductive through holes 21 that this first dielectric layer 23 exposes, and also can comprise another line layer (not shown), to be formed on this second dielectric layer 28 and to be electrically connected those electric connection pads 29.
It should be noted that the structure of Fig. 1, Fig. 2 A to Fig. 2 D, Fig. 2 D ', the circuit shown in Fig. 2 D-1 to Fig. 2 D-4, Fig. 3 A to Fig. 3 D, Fig. 3 D-1 to Fig. 3 D-3 or line layer is signal figure, but not for limiting the present invention.In addition, this first dielectric layer opening 231, opening 232 or the second dielectric layer opening 281 can be poroid or strip.
In sum, compared to prior art, due to the first surface of the present invention by through substrate body and the substrate body hole of second surface, run through the first dielectric layer opening of the first dielectric layer, opening or run through the second dielectric layer opening of the second dielectric layer, and make the thermal expansion strain of each layer and stress be discharged or block, and further can by making substrate body hole, first dielectric layer opening or the second dielectric layer opening are strip, and too large the caused thermal expansion strain of thermal expansion coefficient difference that can discharge or block because of layers of material and stress, thus reduce the warping phenomenon of intermediate plate.
Above-described embodiment only for illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can modify to above-described embodiment.Therefore the scope of the present invention, should listed by claims.
Claims (29)
1. an intermediate plate, comprising:
Substrate body, it has relative first surface and second surface, and has substrate body hole and multiple conductive through holes, this substrate body hole and conductive through holes this first surface through and second surface;
First dielectric layer, it to be formed on this first surface and to expose outside those conductive through holes;
Line layer, it to be formed on this first surface and to be electrically connected those conductive through holes;
Multiple electric connection pad, it to be formed on this second surface and to be electrically connected those conductive through holes; And
Second dielectric layer, it is formed on this second surface and correspondence exposes outside those electric connection pads.
2. an intermediate plate, it comprises:
Substrate body, it has relative first surface and second surface, and has multiple conductive through holes of this first surface through and second surface;
First dielectric layer, it to be formed on this first surface and to expose outside those conductive through holes, and this first dielectric layer has the first dielectric layer opening run through;
Line layer, it to be formed on this first surface and to be electrically connected those conductive through holes;
Multiple electric connection pad, it to be formed on this second surface and to be electrically connected those conductive through holes; And
Second dielectric layer, it is formed on this second surface and correspondence exposes outside those electric connection pads.
3. an intermediate plate, it comprises:
Substrate body, it has relative first surface and second surface, and has multiple conductive through holes of this first surface through and second surface;
First dielectric layer, it to be formed on this first surface and to expose outside those conductive through holes;
Line layer, it to be formed on this first surface and to be electrically connected those conductive through holes;
Multiple electric connection pad, it to be formed on this second surface and to be electrically connected those conductive through holes; And
Second dielectric layer, it is formed on this second surface and correspondence exposes outside those electric connection pads, and this second dielectric layer also has the second dielectric layer opening run through.
4. the intermediate plate as described in claim 1 or 3, is characterized by, and this first dielectric layer also has the first dielectric layer opening running through this first dielectric layer.
5. intermediate plate as claimed in claim 3, it is characterized by, this substrate body also has the substrate body hole of this first surface through and second surface.
6. intermediate plate as claimed in claim 1, it is characterized by, this first dielectric layer also has the first dielectric layer opening running through this first dielectric layer, and this second dielectric layer also has the second dielectric layer opening running through this second dielectric layer.
7. the intermediate plate as described in claim 1,2 or 3, is characterized by, and this intermediate plate also comprises insulating barrier, and it is formed between those conductive through holes and this substrate body.
8. the intermediate plate as described in claim 1,2 or 3, is characterized by, and this line layer comprises connected circuit and electrical contact, and this first dielectric layer also has the opening that correspondence exposes this circuit.
9. the intermediate plate as described in claim 2 or 6; it is characterized by; this intermediate plate also comprises insulating protective layer; it is formed on this first dielectric layer and line layer; this line layer has electrical contact, and this insulating protective layer has and runs through this insulating protective layer and not to should the insulating protective layer opening of electrical contact.
10. intermediate plate as claimed in claim 9, is characterized by, and this insulating protective layer opening is to should the first dielectric layer opening.
11. intermediate plates as claimed in claim 4; it is characterized by; this intermediate plate also comprises insulating protective layer; it is formed on this first dielectric layer and line layer; and this line layer has electrical contact, and this insulating protective layer has and runs through this insulating protective layer and not to should the insulating protective layer opening of electrical contact.
12. intermediate plates as claimed in claim 11, is characterized by, and this insulating protective layer opening is to should the first dielectric layer opening.
13. intermediate plates as described in claim 1,3 or 5; it is characterized by; this intermediate plate also comprises insulating protective layer; it is formed on this first dielectric layer and line layer; this line layer has electrical contact, and this insulating protective layer has and runs through this insulating protective layer and not to should the insulating protective layer opening of electrical contact.
14. intermediate plates as described in claim 1,2 or 3, it is characterized by, this line layer is formed on this first dielectric layer, and connects those conductive through holes that this first dielectric layer exposes.
15. intermediate plates as described in claim 1,2 or 3, it is characterized by, this intermediate plate also comprises another line layer, and it to be formed on this second dielectric layer and to be electrically connected those electric connection pads.
The method for making of 16. 1 kinds of intermediate plates, it comprises:
This first surface in the substrate body with relative first surface and second surface forms multiple first groove and the second groove, and forms conductive through holes in each this first groove;
On the first surface of this substrate body, form line layer and the first dielectric layer, this line layer to be formed on this first surface and to be electrically connected those conductive through holes, and this first dielectric layer to be formed on this first surface and to expose outside this line layer;
The segment thickness of this substrate body is removed, to expose one end of this second groove and conductive through holes from the second surface sidesway of this substrate body; And
The second dielectric layer and the multiple electric connection pads being electrically connected those conductive through holes are formed on this second surface, and this second dielectric layer correspondence exposes outside those electric connection pads, and this second groove forms the substrate body hole of this first surface through and second surface.
The method for making of 17. 1 kinds of intermediate plates, it comprises:
First surface in the substrate body with relative first surface and second surface forms multiple first groove, and forms conductive through holes in each this first groove;
Line layer and the first dielectric layer is formed on the first surface of this substrate body, this line layer to be formed on this first surface and to be electrically connected those conductive through holes, this first dielectric layer to be formed on this first surface and to expose outside this line layer, and this first dielectric layer has the first dielectric layer opening run through;
The segment thickness of this substrate body is removed, to expose one end of this conductive through holes from the second surface sidesway of this substrate body; And
On this second surface, form the second dielectric layer and the multiple electric connection pads being electrically connected those conductive through holes, and this second dielectric layer correspondence exposes outside those electric connection pads.
The method for making of 18. 1 kinds of intermediate plates, comprising:
First surface in the substrate body with relative first surface and second surface forms multiple first groove, and forms conductive through holes in each this first groove;
On the first surface of this substrate body, form line layer and the first dielectric layer, this line layer to be formed on this first surface and to be electrically connected those conductive through holes, and this first dielectric layer to be formed on this first surface and to expose outside this line layer;
The segment thickness of this substrate body is removed, to expose one end of those conductive through holes from the second surface sidesway of this substrate body; And
On this second surface, form the second dielectric layer and the multiple electric connection pads being electrically connected those conductive through holes, and this second dielectric layer correspondence exposes outside those electric connection pads, this second dielectric layer has the second dielectric layer opening run through.
The method for making of 19. intermediate plates as described in claim 16 or 18, it is characterized by, this first dielectric layer also has the first dielectric layer opening run through.
The method for making of 20. intermediate plates as claimed in claim 16, it is characterized by, this first dielectric layer also has the first dielectric layer opening running through this first dielectric layer, and this second dielectric layer also has the second dielectric layer opening running through this second dielectric layer.
The method for making of 21. intermediate plates as described in claim 16,17 or 18, it is characterized by, before those conductive through holes of formation, also be included in those first groove surfaces and form insulating barrier, to make this insulating barrier between those conductive through holes and this substrate body, and the step removing the segment thickness of this substrate body also comprises the insulating barrier removing and be positioned at those the first bottom portion of groove.
The method for making of 22. intermediate plates as described in claim 16,17 or 18, it is characterized by, this line layer comprises connected circuit and electrical contact, and this first dielectric layer also has the opening that correspondence exposes this circuit.
The method for making of 23. intermediate plates as described in claim 17 or 20; it is characterized by; this line layer has electrical contact; after this line layer of formation; also be included on this first dielectric layer and line layer and form insulating protective layer, and this insulating protective layer has and runs through this insulating protective layer and not to should the insulating protective layer opening of electrical contact.
The method for making of 24. intermediate plates as claimed in claim 23, is characterized by, and this insulating protective layer opening is to should the first dielectric layer opening.
The method for making of 25. intermediate plates as claimed in claim 19; it is characterized by; this line layer has electrical contact; after this line layer of formation; also be included on this first dielectric layer and line layer and form insulating protective layer, and this insulating protective layer has and runs through this insulating protective layer and not to should the insulating protective layer opening of electrical contact.
The method for making of 26. intermediate plates as claimed in claim 25, is characterized by, and this insulating protective layer opening is to should the first dielectric layer opening.
The method for making of 27. intermediate plates as described in claim 16 or 18; it is characterized by; this line layer has electrical contact; after this line layer of formation; also be included on this first dielectric layer and line layer and form insulating protective layer, and this insulating protective layer has and runs through this insulating protective layer and not to should the insulating protective layer opening of electrical contact.
28. intermediate plates as described in claim 16,17 or 18, it is characterized by, this line layer is formed on this first dielectric layer, and connects those conductive through holes that this first dielectric layer exposes.
29. intermediate plates as described in claim 16,17 or 18, is characterized by, and after this second dielectric layer of formation, are also included on this second dielectric layer and form another line layer, to be electrically connected those electric connection pads.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW103124687 | 2014-07-18 | ||
| TW103124687A TWI585918B (en) | 2014-07-18 | 2014-07-18 | Interposer and method of manufacture |
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| CN105304594A true CN105304594A (en) | 2016-02-03 |
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| CN201410372802.5A Pending CN105304594A (en) | 2014-07-18 | 2014-07-31 | Interposer and method of manufacturing the same |
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| TW (1) | TWI585918B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107785332A (en) * | 2016-08-24 | 2018-03-09 | 南亚科技股份有限公司 | Semiconductor structure |
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| JP2013021085A (en) * | 2011-07-08 | 2013-01-31 | Panasonic Corp | Interposer, method for manufacturing the same, semiconductor device, and method for manufacturing the same |
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| TW201409653A (en) * | 2012-08-24 | 2014-03-01 | Bridge Semiconductor Corp | Wiring board with embedded device and electromagnetic shielding |
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| JP2003017625A (en) * | 2001-06-29 | 2003-01-17 | Sony Corp | Interposer and semiconductor package |
| CN102947931A (en) * | 2010-03-03 | 2013-02-27 | 佐治亚技术研究公司 | Through-package-via (tpv) structures on inorganic interposer and methods for fabricating same |
| US20120261805A1 (en) * | 2011-04-14 | 2012-10-18 | Georgia Tech Research Corporation | Through package via structures in panel-based silicon substrates and methods of making the same |
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| TW201605006A (en) | 2016-02-01 |
| TWI585918B (en) | 2017-06-01 |
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