CN105304560A - Method for preparing IPS-mode thin-film-transistor (TFT) substrate - Google Patents
Method for preparing IPS-mode thin-film-transistor (TFT) substrate Download PDFInfo
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- CN105304560A CN105304560A CN201510652312.5A CN201510652312A CN105304560A CN 105304560 A CN105304560 A CN 105304560A CN 201510652312 A CN201510652312 A CN 201510652312A CN 105304560 A CN105304560 A CN 105304560A
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- 238000000034 method Methods 0.000 title claims abstract description 58
- 239000000758 substrate Substances 0.000 title claims abstract description 41
- 239000010410 layer Substances 0.000 claims abstract description 47
- 238000000151 deposition Methods 0.000 claims abstract description 31
- 230000008569 process Effects 0.000 claims abstract description 23
- 238000004140 cleaning Methods 0.000 claims abstract description 14
- 238000002360 preparation method Methods 0.000 claims abstract description 14
- 239000011241 protective layer Substances 0.000 claims abstract description 13
- 230000008021 deposition Effects 0.000 claims description 22
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 3
- 239000000428 dust Substances 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 30
- 239000010408 film Substances 0.000 description 26
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000009931 harmful effect Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
The invention discloses a method for preparing an IPS-mode thin-film-transistor (TFT) substrate. The method comprises the procedures of a procedure of depositing a Gate layer on a substrate; a procedure of depositing an island layer according to a CVD process; a procedure of depositing a first ITO layer; a procedure of depositing a source electrode layer and a drain electrode layer; a procedure of depositing a protective layer according to a CVD process, and the procedure comprises a step of cleaning through plasma cleaning gas before CVD film forming is performed; and a procedure of depositing a second ITO layer. The method provided by the technical solution of the invention can suppress dust in a film in preparation process, thereby improving integral yield rate of the TFT substrate.
Description
Technical field
The present invention relates to field of semiconductor device preparation, particularly relate to a kind of IPS pattern TFT substrate preparation method.
Background technology
TFTLCD (Thin-Film-TransistorLiquidCrystalDisplay, Thin Film Transistor-LCD), due to advantages such as its high speed, high brightness, high-contrasts, has obtained general application at present.The pattern of TFT substrate has a lot, comparatively common are TN, IPS, MVA etc.TN pattern, response speed is the fastest, but color is the poorest, and visible angle is relatively little, and cost is low, is mainly used in display and micro television field.The TFT substrate of IPS pattern, be a kind of wide viewing angle Display Technique, visible angle is relatively high, and response speed is very fast, and color is accurate, moderate cost.
In conventional art, the TFT substrate of IPS pattern needs through multiple working procedure in preparation process, in order to deposit different film layer, comprises gate, island, ITO etc.The deposition of some film layer is had to be adopt CVD (ChemicalVaporDeposition, chemical vapour deposition (CVD)) technique.Inventor finds under study for action; in a upper operation of CVD film formation process; the last operation film layer having particulate or densification not is unavoidably adsorbed on prepared product surface; if directly carry out CVD film formation process; those particulates and rete fine and close not will become " in film the ash " of cvd film layer; the performance of integral device is impacted, thus affects the yield of TFT substrate.Therefore, need to provide a kind of method, the generation of ash in film can be suppressed in the TFT substrate preparation process of IPS pattern, thus promote the yield of TFT substrate.
Summary of the invention
Based on this, be necessary to provide a kind of IPS pattern TFT substrate preparation method, the generation of ash in film can be suppressed in preparation process, thus promote TFT substrate yield on the whole.
A kind of IPS pattern TFT substrate preparation method, comprising:
Substrate deposits the operation of Gate layer;
Adopt CVD technique, the operation of deposition island layer;
Deposit the operation of the first ITO layer;
The operation of deposition source drain layer;
Adopt CVD technique, the operation of Deposition of protective layer; In this operation, comprising: before carrying out CVD film forming, carried out the step cleaned by plasma cleaning gas;
Deposit the operation of the second ITO layer.
In one embodiment, described employing CVD technique, the operation of Deposition of protective layer comprises:
Substrate through this operation foregoing sequence enters CVD processing chamber;
Cleaned by plasma cleaning gas;
By the process gas of this operation, carry out CVD film forming;
Described substrate is optimized and destatics;
Described substrate is shifted out from described CVD processing chamber.
In one embodiment, described plasma cleaning gas is N2, NH3 or its mixed gas plasma; Carrying out in the process cleaned, the force value in described CVD chamber is 1500mTorr, and throughput is 1500sccm, and the radio-frequency power supply power producing plasma is 300 ~ 500W.
In one embodiment, the described process gas by this operation, carries out the step of CVD film forming, comprising:
By N2, NH3, SiH4, throughput is respectively 4000sccm, 1500sccm, 250sccm, and described CVD chamber internal pressure is 1500mTorr, carries out reaction and film forming.
In one embodiment, describedly described substrate is optimized to the step destaticed, comprises:
By H2, throughput is 800sccm, and described CVD chamber pressure is 1500mTorr, utilizes radio-frequency power supply to produce plasma and destatics.
In one embodiment, the described operation depositing Gate layer on substrate, the operation of described deposition first ITO layer, the operation of described deposition source drain layer, the operation of described deposition second ITO layer, adopts PVD film-forming process.
Above-mentioned IP S mode TFT substrate preparation method; in employing CVD technique; in the middle of the operation of Deposition of protective layer; before carrying out reaction film forming by process gas; first cleaned by plasma cleaning gas; inhibit ash in the film that may produce in this operation, ensure that electric field performance between the first ITO layer and the second ITO layer is from harmful effect, thus improve the yield of TFT substrate.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the IPS pattern TFT substrate preparation method in an embodiment;
Fig. 2 is the structural representation of the IPS pattern TFT substrate in an embodiment;
Fig. 3 is the schematic flow sheet of Deposition of protective layer operation in an embodiment.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
See Fig. 1 and Fig. 2, provide a kind of IPS (In-PlaneSwitching) pattern TFT substrate preparation method in one embodiment, comprising:
101, substrate deposits the operation of Gate layer.
Concrete, PVD (PhysicalVaporDeposition, physical vapour deposition (PVD)) film-forming process, on the base plate 20 plated metal can be adopted, obtain Gate pattern 21 through PROCESS FOR TREATMENT.
102, adopt CVD technique, the operation of deposition island layer.
Concrete, island (Island) layer is nonmetal rete, comprises G-SiNx (in Fig. 2 221), a-Si (in Fig. 2 region 222), n
+a-Si (in Fig. 2 223).
103, deposit the operation of the first ITO layer.
Concrete, adopt PVD to deposit ITO, an ITO as in Fig. 2 23.
104, the operation of deposition source drain layer.
Concrete, on aforementioned base, depositing metal layers, obtains source drain (S/D) pattern 24 through PROCESS FOR TREATMENT.
105, adopt CVD technique, the operation of Deposition of protective layer.
Concrete, in protective layer and Fig. 2 25, be non-metallic layer.Technique is CVD technique.Because protective layer 25 is clipped between the first ITO layer and the second ITO layer; if do not process the particulate of foregoing sequence substrate surface (especially the first ITO layer surface) and the rete of defective tightness; ash in the film in cvd film layer will be formed; thus the dielectric constant between two ITO layer is impacted, thus reduce the performance of integral device.In this operation, for suppressing ash in film, including before carrying out CVD film forming, being carried out the step cleaned by plasma cleaning gas.The particulate eliminating substrate surface and the rete compacted not, thus suppress the generation of ash in film.After cleaning completes, by the process gas (reacting gas) of this operation, carry out film forming, form protective layer.
106, deposit the operation of the second ITO layer.
Concrete, the second ITO layer is 26, employing PVD film-forming process in Fig. 2.
IPS pattern TFT substrate preparation method in above-described embodiment; in employing CVD technique; in the middle of the operation of Deposition of protective layer; before carrying out reaction film forming by process gas; first cleaned by plasma cleaning gas; inhibit ash in the film that may produce in this operation, ensure that electric field performance between the first ITO layer and the second ITO layer is from harmful effect, thus improve the yield of TFT substrate.
Further, in Fig. 3 embodiment, adopt CVD technique, the operation of Deposition of protective layer comprises:
301, the substrate through this operation foregoing sequence enters CVD processing chamber.
302, cleaned by plasma cleaning gas.
Plasma cleans gas Main Function suppresses, in film, to react with the first ITO layer, can from follow-up process gas preferably, and such as plasma cleaning gas is N2, NH3 or its mixed gas plasma.Carrying out in the process cleaned, the force value in CVD chamber is 1500mTorr, and throughput is 1500sccm, and the radio-frequency power supply power producing plasma is 300 ~ 500W.
303, by the process gas of this operation, carry out CVD film forming.
Concrete, by N2, NH3, SiH4, throughput is respectively 4000sccm, 1500sccm, 250sccm, and described CVD chamber internal pressure is 1500mTorr, carries out reaction and film forming.
304, substrate is optimized and destatics.
Concrete, by H2, throughput is 800sccm, and CVD chamber pressure is 1500mTorr, utilizes radio-frequency power supply to produce plasma and destatics.
305, from CVD processing chamber, shift out substrate.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (6)
1. an IPS pattern TFT substrate preparation method, is characterized in that, described method comprises:
Substrate deposits the operation of Gate layer;
Adopt CVD technique, the operation of deposition island layer;
Deposit the operation of the first ITO layer;
The operation of deposition source drain layer;
Adopt CVD technique, the operation of Deposition of protective layer; In this operation, comprising: before carrying out CVD film forming, carried out the step cleaned by plasma cleaning gas;
Deposit the operation of the second ITO layer.
2. method according to claim 1, is characterized in that, described employing CVD technique, and the operation of Deposition of protective layer comprises:
Substrate through this operation foregoing sequence enters CVD processing chamber;
Cleaned by plasma cleaning gas;
By the process gas of this operation, carry out CVD film forming;
Described substrate is optimized and destatics;
Described substrate is shifted out from described CVD processing chamber.
3. method according to claim 2, is characterized in that, described plasma cleaning gas is N2, NH3 or its mixed gas plasma; Carrying out in the process cleaned, the force value in described CVD chamber is 1500mTorr, and throughput is 1500sccm, and the radio-frequency power supply power producing plasma is 300 ~ 500W.
4. method according to claim 2, is characterized in that, the described process gas by this operation, carries out the step of CVD film forming, comprising:
By N2, NH3, SiH4, throughput is respectively 4000sccm, 1500sccm, 250sccm, and described CVD chamber internal pressure is 1500mTorr, carries out reaction and film forming.
5. method according to claim 2, is characterized in that, describedly described substrate is optimized to the step destaticed, and comprising:
By H2, throughput is 800sccm, and described CVD chamber pressure is 1500mTorr, utilizes radio-frequency power supply to produce plasma and destatics.
6. method according to claim 1, is characterized in that, the described operation depositing Gate layer on substrate, the operation of described deposition first ITO layer, the operation of described deposition source drain layer, the operation of described deposition second ITO layer, adopts PVD film-forming process.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510652312.5A CN105304560A (en) | 2015-10-10 | 2015-10-10 | Method for preparing IPS-mode thin-film-transistor (TFT) substrate |
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| CN201510652312.5A CN105304560A (en) | 2015-10-10 | 2015-10-10 | Method for preparing IPS-mode thin-film-transistor (TFT) substrate |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106098617A (en) * | 2016-08-01 | 2016-11-09 | 信利（惠州）智能显示有限公司 | A kind of wide viewing angle pattern TFT substrate preparation method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1276630A (en) * | 1999-06-02 | 2000-12-13 | 株式会社半导体能源研究所 | Semiconductor device and its mfg. method |
| US20150053988A1 (en) * | 2013-08-23 | 2015-02-26 | Boe Technology Group Co., Ltd. | Array substrate, method for manufacturing the same and display device |
| CN104733384A (en) * | 2013-08-22 | 2015-06-24 | 合肥京东方光电科技有限公司 | Display substrate, display substrate manufacturing method and display device |
-
2015
- 2015-10-10 CN CN201510652312.5A patent/CN105304560A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1276630A (en) * | 1999-06-02 | 2000-12-13 | 株式会社半导体能源研究所 | Semiconductor device and its mfg. method |
| CN104733384A (en) * | 2013-08-22 | 2015-06-24 | 合肥京东方光电科技有限公司 | Display substrate, display substrate manufacturing method and display device |
| US20150053988A1 (en) * | 2013-08-23 | 2015-02-26 | Boe Technology Group Co., Ltd. | Array substrate, method for manufacturing the same and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106098617A (en) * | 2016-08-01 | 2016-11-09 | 信利（惠州）智能显示有限公司 | A kind of wide viewing angle pattern TFT substrate preparation method |
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