CN105304124B - Resistance-type memory and its control method and storage unit - Google Patents
Resistance-type memory and its control method and storage unit Download PDFInfo
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Abstract
A kind of resistance-type memory of present invention offer and its control method and storage unit, the resistance-type memory include one first decoding unit, one second decoding unit, a control detection unit and multiple storage units.First decoding unit transmits an at least word signal by an at least wordline.Second decoding unit transmits an at least signal by an at least bit line.Detection unit is controlled by least source line, transmits an at least source signal.Each storage unit includes a transistor and a variable resistance.Variable resistance is coupled between a first end of transistor and bit line.One second end of transistor couples source electrode line.During one sets, source signal is a fixed level, and position signal is not fixed level.During one resets and during a reading, source signal is not fixed level, and position signal is fixed level.The present invention keeps the level of bit line during resetting and reading, is not required to the level of switching bit line, thus reduces switching time.
Description
Technical field
The invention relates to a kind of resistance-type memories, in particular to one kind during resetting and reading, keep
The resistance-type memory of the level of bit line.
Background technology
With the development of science and technology and under portable and power saving trend, storage demand of the electronic product for data
It is significantly increased.In general, memory is divided into volatile memory and nonvolatile memory.Traditional volatile memory packet
It includes, dynamic random access memory and static RAM.Nonvolatile memory includes read-only memory
(ROM), programmable read-only memory, erasable and programmable formula read-only memory (EPROM), erasable programmable read-only storage
Device and flash memory.
Current novel volatile memory includes that ferroelectric memory, Ovonics unified memory, magnetic storage and resistance-type are deposited
Reservoir.Since resistance-type memory has many advantages, such as that simple in structure, at low cost, speed with low-power consumption, therefore is substantially used soon.
Invention content
The purpose of the present invention is to provide a kind of resistance-type memory and its control methods and storage unit, further to carry
The action switch speed of high existing resistance-type memory.
The present invention provides a kind of resistance-type memory, including one first decoding unit, one second decoding unit, a control inspection
Survey unit and multiple storage units.First decoding unit transmits an at least word signal by an at least wordline.Second decoding is single
Member transmits an at least signal by an at least bit line.Detection unit is controlled by least source line, transmits an at least source electrode
Signal.Each storage unit includes a transistor and a variable resistance.Variable resistance be coupled to a first end of transistor with
Between bit line.One second end of transistor couples source electrode line.During one sets, it is one solid that control detection unit, which enables source signal,
Determine level, it is fixed level that the second decoding unit, which enables position signal not,.During one resets, control detection unit enables source signal not
For fixed level, it is fixed level that the second decoding unit, which enables position signal,.During one reads, control detection unit enables source signal
It is not fixed level, it is fixed level that the second decoding unit, which enables position signal,.
The present invention separately provides a kind of control method, is suitable for a resistance-type memory.Resistance-type memory has a crystal
Pipe and a variable resistance.Variable resistance is coupled between a first end of transistor and a bit line.The control method of the present invention
Including executing a set action, set action is that enable the level of bit line not be a fixed level, and enables the one second of transistor
End is fixed level；Execute resetting action, resetting action is that enable the level of bit line be fixed level, and enables the of transistor
Two ends are not fixed level；A read action is executed, read action is to enable the level of bit line for fixed level, and enable transistor
Second end be fixed level.
The present invention also provides a kind of resistive memory cells, including a transistor and a variable resistance.Transistor has
One first end and a second end.Variable resistance is coupled between a bit line and first end.During one sets, second end receives
One fixed level, bit line do not receive fixed level.During one resets, second end does not receive fixed level, and bit line, which receives, to be fixed
Level.During one reads, second end does not receive fixed level, and bit line receives fixed level.
The present invention keeps the level of bit line during resetting and reading, is not required to the level of switching bit line, thus reduces and cut
Change the time.
For the features and advantages of the present invention can be clearer and more comprehensible, it is cited below particularly go out preferred embodiment, and coordinate attached drawing, make
Detailed description are as follows：
Description of the drawings
Fig. 1 is the schematic diagram of the resistance-type memory of the present invention；
Fig. 2 is the schematic diagram of the storage unit of the present invention；
Fig. 3 A~3D are the possibility embodiment of control method of the present invention.
Symbol description：
100：Resistance-type memory；
110、120：Decoding unit；
130：Control detection unit；
140：Memory cell array；
WL1~WLN：Wordline；
BL1~BLM：Bit line；
SL1~SLM：Source electrode line；
M11~MMN：Storage unit；
210：Transistor；
220：Variable resistance；
VG：Gate signal；
VBL：Position signal；
VSL：Source signal；
S310：Set action；
S320：Resetting acts；
S330、S370：Read action；
S340：Action is reset again；
S360：Reset action；
S380：Formation acts；
S390：Initialization action；
S311, S312, S321, S322, S331~S334, S341, S342, S361, S362, S371~S373, S381,
S382、S391、S392：Step.
Specific implementation mode
Fig. 1 is the schematic diagram of the resistance-type memory of the present invention.As shown, resistance-type memory 100 includes that decoding is single
Member 110,120, one controls detection unit 130 and a memory cell array 140.Decoding unit 110 is to one first address signal
(not shown) is decoded, and generates multiple word signals according to decoding result, then passes through wordline WL1~WLNTransmission word signal, which gives, to be deposited
Storage unit array 140.
Decoding unit 120 is decoded one second address signal (not shown), and generates multiple positions according to decoding result
Signal, then pass through bit line BL1~BLMTraffic bit signal gives memory cell array 140.The unlimited definite decoding unit of the present invention 110 with
120 inside structure.As long as being capable of providing level appropriate gives wordline WL1~WLNWith bit line BL1~BLMCircuit, can make
For decoding unit 110 and 120.
Control detection unit 130 passes through source electrode line SL1~SLMSource signal is transmitted, to write data to storage unit battle array
Row 140.In the present embodiment, the detection of control detection unit 130 flows through source electrode line SL1~SLMElectric current, and according to testing result
Learn and export the data that memory cell array 140 is stored.The present invention does not limit the circuit frame of control detection unit 130
Structure.It is capable of providing level appropriate as long as any and gives source electrode line SL1~SLM, and detectable source electrode line SL1~SLMSize of current
Circuit framework, can be used as control detection unit 130.
In another embodiment, control detection unit 130 includes a voltage generation circuit and a detection circuit (not showing).
Voltage generation circuit is controlling source electrode line SL1~SLMLevel.Detection circuit is detecting 140 stored number of memory cell array
According to.
Memory cell array 140 includes storage unit M11~MMN.Each storage unit couples corresponding wordline, bit line
And source electrode line.By control wordline, the level of bit line and source electrode line, the impedance of control storage unit can be adjusted.It is different
Impedance represents different data.For example, when storage unit has high impedance, expression storage data 0；When storage unit has
Low ESR indicates storage data 1.Due to storage unit M11~MMNInside structure all same, thus it is following only with storage unit M11For
Example.
Referring to FIG. 2, storage unit M11Including a transistor 210 and a variable resistance 220.The control of transistor 210
End coupling wordline WL1, to receive a gate signal VG.Variable resistance 220 is coupled to bit line BL1With the first end of transistor 210 it
Between, to receive a signal VBL.The second end coupling source electrode line SL of transistor 2101, to receive a source signal VSL。
In the present embodiment, decoding unit 110,120 and control detection unit 130 are first to storage unit M11Carry out a setting
Action.During one sets, control detection unit 130 enables source signal VSLFor a fixed level, decoding unit 120 enables position signal
VBLIt is not fixed level.Position signal VBLLevel be any level appropriate.In a possible embodiment, fixed level one
Earth level.At this point, variable resistance 220 has Low ESR.
Then, decoding unit 110,120 and control detection unit 130 are to storage unit M11Carry out a resetting action.One
During resetting, control detection unit 130 enables source signal VSLIt is not fixed level, decoding unit 120 enables position signal VBLFor fixation
Level.At this point, variable resistance 220 has high impedance.Source signal VSLLevel can be any level appropriate.
Then, decoding unit 110,120 and control detection unit 130 are to storage unit M11Carry out a read action.One
During reading, control detection unit 130 enables source signal VSLIt is not fixed level, decoding unit 120 enables position signal VBLFor fixation
Level.Position signal VBLLevel system be any level appropriate.For example, the source signal V during readingSLLevel
It is equally likely to, is more than or less than the source signal V during resettingSLLevel.
Then, decoding unit 110,120 and control detection unit 130 are to storage unit M11Resetting again and again is executed to act.Again
Resetting action is similar to resetting action, is to enable source signal VSLIt is not fixed level, and position signal VBLFor fixed level.
The present invention does not limit the source signal V for resetting action againSLLevel.In a possible embodiment, then reset dynamic
The source signal V of workSLLevel be equal to, more than or less than the source signal V in the case where resetting actsSLLevel.In another possibility
In embodiment, then it is to gradually increase source signal V to reset actionSLLevel.
As source signal VSLLevel be equal to a preset value after, again to storage unit M11It is read out action.It is reading
Period, control detection unit 130 enable source signal VSLIt is not fixed level, and decoding unit 120 enables position signal VBLFor fixed electricity
It is flat.At this point, variable resistance 220 should have high impedance.If variable resistance 220 do not have high impedance, decoding unit 110,120 with
Detection unit 130 is controlled again to storage unit M11Action is reset again, until variable resistance 220 has high impedance.
The present invention does not limit the impedance how control detection unit 130 reads variable resistance 220.It may embodiment one
In, source electrode line SL is flowed through in the control detection of detection unit 1301Electric current.When flowing through source electrode line SL1Electric current be more than a reference value when,
Indicate that variable resistance 220 has Low ESR.On the contrary, when flowing through source electrode line SL1Electric current when not being more than reference value, indicate variable
Resistance 220 has high impedance.
In the present embodiment, during setting earlier than during resetting, and earlier than during reading during resetting.If desired to depositing
Storage unit M11When being reset action again, then action is reset again between resetting and read action.In other embodiments, may be used
Action is reset again using resetting substitution.In another possible embodiment, before executing set action, decoding unit 110,120
With control detection unit 130 first to storage unit M11A formation action and an initialization action are carried out, it is single to activate storage
First M11。
During one forms, control detection unit 130 enables source signal VSLFor fixed level, decoding unit 120 enables position believe
Number VBLIt is not fixed level.At this point, variable resistance 220 has Low ESR.In a possible embodiment, the position letter during formation
Number VBLLevel be equal to, more than or less than the position signal V during settingBLLevel.
During one initializes, control detection unit 130 enables source signal VSLIt is not fixed level, and decoding unit 120
Enable position signal VBLFor fixed level.In a possible embodiment, the source signal V during initializationSLLevel be equal to, greatly
In or less than in the source signal V for resetting or readingSLLevel.
During one may be located in embodiment, during initialization and be formed with during setting between.It may implement another
In example, is formed and dispatched from the factory preceding completion in resistance-type memory 100 with initialization action.After manufacture, resistance-type memory 100 only executes
Above-mentioned setting, resetting are reset and read action again.In other embodiments, in different periods, gate signal V in wordlineGTool it is different or
Same level, to the conducting state of controlling transistor 210.Therefore, any suitable level can be used as gate signal VG。
In some embodiments, after set action, decoding unit 110,120 can be first right with control detection unit 130
Storage unit M11Carry out one first read action.As storage unit M11When with Low ESR, then start to storage unit M11It carries out
Resetting acts, and after resetting action, to storage unit M11Carry out one second read action.
When carrying out the first read action, if storage unit M11It, then can be to storage unit M without Low ESR11It carries out again
Set action, and read again storage unit M11Impedance, until storage unit M11With Low ESR.It may embodiment one
In, it resets action and is similar to set action, the difference is that it is to gradually increase bit line BL to reset action1Level.
Fig. 3 A are a possible embodiment of control method of the present invention.Resistance-type memory is variable with a transistor and one
Resistance.For convenience of description, below by taking Fig. 2 as an example.As shown, variable resistance 220 is coupled to the first end of transistor 210 and one
Line BL1Between, and the second end of transistor 210 coupling source line SL.
First, to storage unit M11Carry out a set action (step S310).During one sets, bit line BL is enabled1Electricity
Flat is not a fixed level (step S311), and enables source electrode line SL1For fixed level (step S312).It may embodiment one
In, after having carried out set action, storage unit M11With Low ESR.Bit line BL1Level can be any level appropriate.
In one possible embodiment, fixed level is an earth level.
Then, to storage unit M11Carry out a resetting action (step S320).During one resets, bit line BL is enabled1Electricity
It puts down as fixed level (step S321), and enables source electrode line SL1Level be fixed level (step S322).It may implement one
In example, after having carried out resetting action, storage unit M11With high impedance.Source electrode line SL1Level can be any level appropriate.
Then, to storage unit M11Carry out a read action (step S330).Bit line BL is enabled during reading1Level is to fix
Level (step S331), and enable source electrode line SL1It is not fixed level (step S332).Do not limit source electrode line SL1Level.Source electrode
Line SL1Level can be any level appropriate.In one embodiment, step S332 source electrode lines SL1Level be equal to, be more than or less than
Step S322 source electrode lines SL1Level.
In the present embodiment, set action S310 acts S320 earlier than resetting, and resetting acts S320 earlier than read action
S330.In addition, when executing set action S310, resetting acting S320 and read action S330, the grid of transistor 210 connects
Receive corresponding gate signal.When executing different actions, the grid of transistor 210 may receive identical or different grid letter
Number.
Fig. 3 B are another possible embodiment of control method of the present invention.Fig. 3 B are similar to Fig. 3 A, and difference is more in Fig. 3 B
Again reset action S340.Action S340 is reset again to be located between resetting action S320 and read action S330.
During reading, bit line BL is enabled1For fixed level (step S331), and enable source electrode line SL1It is not fixed level
(step S332).Next, it is determined that storage unit M11Impedance whether be equal to a preset value (step S333).It may embodiment one
In, if storage unit M11Impedance be equal to preset value (such as high impedance), then it represents that storage unit M11Normally (step S334).If
It is no, then it executes and resets action S340 again.
During resetting again and again, bit line BL is enabled1For fixed level (step S341), and enable source electrode line SL1It is not fixed electricity
Flat (step S342).In another embodiment, step S342 is to gradually increase source electrode line SL1Level.Source electrode line SL1Level is changed
The number of change can be arbitrary number of times.Then, read action S330 is executed, to read storage unit M11Impedance.If storage unit
M11Do not have high impedance, then executes again and reset action S340 again, reset storage unit M again11, until storage unit M11Tool is high
Impedance.
How the present invention reads storage unit M if not limiting11Impedance.In a possible embodiment, flowed through by measurement
Source electrode line SL1The magnitude of current, just learn storage unit M11Impedance.If when flowing through source electrode line SL1The magnitude of current be more than one reference
When value, storage unit M is indicated11With Low ESR；If when no more than reference value, indicating tool high impedance.
In other embodiments, action S340 is reset again using resetting action S320 substitutions.In this instance, when storage is single
First M11Impedance be not equal to preset value when, then execute resetting action S320, to reset storage unit M again11.Due to holding
When row resetting acts S320 and read action S330, bit line BL1Fixed level is all maintained, therefore adjustment bit line BL can be greatly decreased1
Level time.
Fig. 3 C are another possible embodiment of control method of the present invention.Fig. 3 C are similar to Fig. 3 A, the difference is that Fig. 3 C
It is more to reset action S360 and read action S370.After set action S310, storage unit M11There should be Low ESR.Cause
This enables bit line BL during one reads1It is not fixed level (step S371), and enables source electrode line SL1For fixed level (step
S372).In a possible embodiment, the bit line BL of step S3711Level be equal to, the bit line BL more than or less than step S3611
Level.
Then, step S373 judges storage unit M11Impedance whether be equal to a preset value (such as low level).If it is not, then holding
Row resets action S360, until storage unit M11Impedance be equal to preset value.As storage unit M11Impedance be equal to preset value
When, it executes resetting and acts S320.
During one resets, bit line BL is enabled1It is not fixed level (step S361), and enables source electrode line SL1For fixed level
(step S362).In another embodiment, step S361 gradually increases bit line BL1Level.In other embodiments, it can omit and set again
Surely S360 is acted.In this example, as storage unit M11Impedance be not equal to preset value when, then execute reset action S360, to
Setting storage unit M again11.In another embodiment, Fig. 3 B read action S330 and reset again action S340 can also be applied to
Fig. 3 C.Step S333 and S373 institutes using preset value and differ in this example.
Fig. 3 D are another possible embodiment of control method of the present invention.Fig. 3 D are similar to Fig. 3 A, the difference is that Fig. 3 D
More formation act S380 and initialization action S390.Formation acts S380 and initialization action S390 earlier than set action
S310, wherein initialization action S390 are later than to form action S380.
During one forms, source electrode line SL is enabled1Level be fixed level (step S381), and enable bit line BL1Level not
For fixed level (step S382).After completing formation action, storage unit M11With Low ESR.In a possible embodiment,
The bit line BL of step S3811Level be more than step S311 bit line BL1Level.In another embodiment, formation action is being executed
When S380, the grid of transistor 210 receives maximum gate signal, when being more than the other actions of execution, the grid of transistor 210
Received gate signal.
During one initializes, source electrode line SL is enabled1Level be not fixed level (step S391), and enable bit line BL1's
Level is fixed level (step S392).After completing initialization action S390, storage unit M11There should be high impedance.It can one
In energy embodiment, source electrode line SL when initialization action S390 is executed1Level be equal to, be more than or less than execute resetting action
Source electrode line SL when S320 or read action S3301Level.
In a possible embodiment, the formation action S380 and initialization action S390 of Fig. 3 D can be applied to Fig. 3 B or 3C
In.In another possible embodiment, the read action S330 of Fig. 3 B can be applied to action S340 is reset again in Fig. 3 D.Other
In embodiment, Fig. 3 C's resets action S360 and read action S370 and can also be applied in Fig. 3 D.In addition, the formation of Fig. 3 D is dynamic
Making S380 and initialization action S390 is completed in factory before memory manufacture.After manufacture, it is not required to execute formation action again
S380 and initialization action S390.
When executing resetting action, read action and resetting action again, bit line BL1Level be equal to fixed level, because
This, is not required to switching bit line BL1Level, thus reduce switching time.
Unless otherwise defined, all vocabulary belong to the general reason of the technical staff in the technical field of the invention herein
Solution.In addition, unless clear expression, definition of the vocabulary in general dictionary should be interpreted that the article of technical field associated therewith is favorite
It is adopted consistent, and should not be construed as perfect condition or excessively formal voice.
Although the present invention has been disclosed as a preferred embodiment, however, it is not to limit the invention, any affiliated technology
Technical staff in field, without departing from the spirit and scope of the present invention, when can make some changes and embellishment, therefore this hair
Bright protection domain is when subject to the attached claims institute defender.
Claims (14)
1. a kind of resistance-type memory, which is characterized in that the resistance-type memory includes：
One first decoding unit transmits an at least word signal by an at least wordline；
One second decoding unit transmits an at least signal by an at least bit line；
One control detection unit transmits an at least source signal by least source line；And
Multiple storage units, each storage unit include a transistor and a variable resistance, which is coupled to the crystalline substance
Between the first end and the bit line of body pipe, a second end of the transistor couples the source electrode line；
Wherein during one sets, it is a fixed level, second decoding unit which, which enables the source signal,
It is the fixed level to enable institute's bit signal not；During one resets, which enables the source signal not solid for this
Determine level, it is the fixed level which, which enables institute's bit signal,；During one reads, which enables institute
It is the fixed level to state source signal not, and it is the fixed level which, which enables institute's bit signal,.
2. resistance-type memory as described in claim 1, which is characterized in that earlier than during the resetting during the setting, this is heavy
Earlier than during the reading during setting.
3. resistance-type memory as described in claim 1, which is characterized in that during the reading, judge the variable resistance
Whether impedance is equal to a preset value, and when the impedance of variable resistance is not equal to the preset value, which enables the source
Pole signal is not the fixed level, and it is the fixed level which, which enables institute's bit signal,.
4. resistance-type memory as described in claim 1, which is characterized in that during the reading, control detection unit inspection
One electric current of the excessively described source electrode line of flow measurement, when the electric current for flowing through the source electrode line is more than a reference value, variable resistance tool
There is one first impedance, when the electric current for flowing through the source electrode line is not more than the reference value, which has one second resistance
Anti-, which is less than second impedance.
5. resistance-type memory as described in claim 1, which is characterized in that during one forms, which enables
The source signal is the fixed level, and it is the fixed level which, which enables institute's bit signal not, in an initialization
Period, it is the fixed level which, which enables the source signal not, which enables institute's bit signal be
The fixed level, be located at earlier than during the setting during the formation, during the initialization during the formation with during the setting it
Between.
6. a kind of control method, is suitable for a resistance-type memory, the resistance-type memory is variable with a transistor and one
Resistance, the variable resistance are coupled between a first end of the transistor and a bit line, the second end coupling one of the transistor
Source electrode line, which is characterized in that the control method includes：
A set action is executed, which is that enable the level of the bit line not be a fixed level, and enables the source electrode line
Level is the fixed level；
Resetting action is executed, resetting action is to enable the level of the bit line for the fixed level, and enable the electricity of the source electrode line
Flat is not the fixed level；
A read action is executed, which is to enable the level of the bit line for the fixed level, and enable the electricity of the source electrode line
Flat is not the fixed level.
7. control method as claimed in claim 6, which is characterized in that the set action is acted earlier than the resetting, and the resetting is dynamic
Make earlier than the read action.
8. control method as claimed in claim 6, which is characterized in that the control method further includes：
Judge whether the impedance of the variable resistance is equal to a preset value；
It when the impedance of the variable resistance is not equal to the preset value, executes resetting again and again and acts, it is to enable that wherein this resets action again
The level of the bit line is the fixed level, and it is not the fixed level to enable the level of the source electrode line, and executes the reading again
Action.
9. control method as claimed in claim 6, which is characterized in that the control method further includes：
Formation action is executed, formation action is to enable the level of the source electrode line for the fixed level, and enable the electricity of the bit line
Flat is not the fixed level；And
An initialization action is executed, which is that enable the level of the source electrode line not be the fixed level, and enables the position
The level of line is the fixed level, and earlier than the set action, which is located at formation action for wherein formation action
Between the set action.
10. a kind of resistive memory cell, which is characterized in that the resistive memory cell includes：
One transistor has a first end and a second end；And
One variable resistance is coupled between a bit line and the first end, and wherein a second end of the transistor couples source line；
Wherein during one sets, which receives a fixed level, which does not receive the fixed level；The phase is reset one
Between, which does not receive the fixed level, which receives the fixed level；During one reads, which does not receive
The fixed level, the bit line receive the fixed level.
11. resistive memory cell as claimed in claim 10, which is characterized in that earlier than during the resetting during the setting,
Earlier than during the reading during the resetting.
12. resistive memory cell as claimed in claim 10, which is characterized in that during the reading, judge that this can power transformation
Whether the impedance of resistance is equal to a preset value, and when the impedance of the variable resistance is not equal to the preset value, which does not receive this
Fixed level, the bit line receive the fixed level.
13. resistive memory cell as claimed in claim 10, which is characterized in that during the reading, when flowing through the source electrode
When the electric current of line is more than a reference value, which has one first impedance, is somebody's turn to do when the electric current for flowing through the source electrode line is not more than
When reference value, which there is one second impedance, first impedance to be less than second impedance.
14. resistive memory cell as claimed in claim 10, which is characterized in that during one forms, which receives
The fixed level, the bit line do not receive the fixed level, and during one initializes, which does not receive the fixed level, should
Bit line receives the fixed level, earlier than during the setting during the formation, is set with this during being located at the formation during the initialization
Between between periodically.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7760538B1 (en) * | 2008-03-04 | 2010-07-20 | Xilinx, Inc. | Non-volatile SRAM cell |
| CN101789262A (en) * | 2009-01-22 | 2010-07-28 | 索尼公司 | Variable resistance memory device |
| CN102347073A (en) * | 2010-06-10 | 2012-02-08 | 夏普株式会社 | Resistance control method for nonvolatile variable resistive element |
| CN102456393A (en) * | 2010-11-04 | 2012-05-16 | 希捷科技有限公司 | Field assisted switching of a magnetic memory element |
| CN103035289A (en) * | 2011-10-07 | 2013-04-10 | 夏普株式会社 | Semiconductor memory device and semiconductor device |
| CN103229244A (en) * | 2011-11-29 | 2013-07-31 | 松下电器产业株式会社 | Resistance change type nonvolatile storage device and method of writing the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20100137884A (en) * | 2009-06-23 | 2010-12-31 | 삼성전자주식회사 | Variable resistive memory device compensating wordline resistance |
| US8563962B2 (en) * | 2009-12-28 | 2013-10-22 | Panasonic Corporation | Memory device and method of manufacturing the same |
-
2014
- 2014-07-10 CN CN201410326914.7A patent/CN105304124B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7760538B1 (en) * | 2008-03-04 | 2010-07-20 | Xilinx, Inc. | Non-volatile SRAM cell |
| CN101789262A (en) * | 2009-01-22 | 2010-07-28 | 索尼公司 | Variable resistance memory device |
| CN102347073A (en) * | 2010-06-10 | 2012-02-08 | 夏普株式会社 | Resistance control method for nonvolatile variable resistive element |
| CN102456393A (en) * | 2010-11-04 | 2012-05-16 | 希捷科技有限公司 | Field assisted switching of a magnetic memory element |
| CN103035289A (en) * | 2011-10-07 | 2013-04-10 | 夏普株式会社 | Semiconductor memory device and semiconductor device |
| CN103229244A (en) * | 2011-11-29 | 2013-07-31 | 松下电器产业株式会社 | Resistance change type nonvolatile storage device and method of writing the same |
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