CN105302748A - SDRAM control method and system - Google Patents
SDRAM control method and system Download PDFInfo
- Publication number
- CN105302748A CN105302748A CN201510744798.5A CN201510744798A CN105302748A CN 105302748 A CN105302748 A CN 105302748A CN 201510744798 A CN201510744798 A CN 201510744798A CN 105302748 A CN105302748 A CN 105302748A
- Authority
- CN
- China
- Prior art keywords
- data
- instruction
- sdram
- memory bank
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
Abstract
The invention provides an SDRAM control method and system. The method comprises: receiving each instruction for performing data reading/writing on an SDRAM, wherein at least two preset memory banks cyclically store data corresponding to each instruction in sequence; and performing a reading/writing operation on the data corresponding to each instruction according to each instruction, wherein before a current memory bank performs the data reading/writing operation, an activation operation of data in a next memory bank is performed, and the data reading/writing of the next memory bank is performed after the activation operation, so that the interval time for memory bank access is shortened and the SDRAM control efficiency is improved.
Description
Technical field
The present invention relates to SDRAM field, particularly a kind of SDRAM control method and system thereof.
Background technology
SDRAM (SynchronousDynamicRandomAccessMemory, Synchronous Dynamic Random Access Memory) storage space is made up of multiple memory bank (BANK), the quantity in general memory storehouse be 2,4,8 not etc.
Current SDRAM control method is all carry out sequential access successively to these memory banks, and to write data instance, the situation of accessing successively is exactly, and after writing full first piece of memory bank, just address can be jumped to second piece of memory bank and proceed write operation.And the characteristic of SDRAM self determines that needing every 64ms to realize self refreshes once, forbid in self-refresh process conducting interviews to SDRAM, so the control method of accessing successively, even if data are all at first piece of memory bank, also need the refresh operation waiting for other memory bank.
And no matter the repeatedly access control of current SDRAM is access instruction, or address date, be all carry out Serial Control successively in order.Such as, double write 8 bit data, carries out: send write order, first time sends 8 bit data start addresses, activate corresponding line according to assigned address, write data, closing rows waits for next operation, send write order, second time sends 8 bit data start addresses, wait for next operation according to assigned address activation corresponding line, write data, closing rows in the following order.Visible, also there is more interval time in the control method of current SDRAM many access.
Therefore, the elapsed time of current SDRAM control method, be consumed in a great extent and refresh stand-by period and the command interval time repeatedly between access, its efficiency is very low.
Summary of the invention
For the problem that the SDRAM control efficiency existed in above-mentioned prior art is low, the object of the present invention is to provide a kind of SDRAM control method and system thereof, the control efficiency of SDRAM can be improved.
A kind of SDRAM control method, comprising:
Receive each instruction SDRAM being carried out to reading and writing data, wherein, described SDRAM comprises at least two default memory banks, stores data corresponding to each instruction for circulating successively;
Perform the read-write operation of its corresponding data according to each instruction, wherein, carry out in current memory storehouse before data read-write operation completes, carrying out the activation manipulation of next memory bank data, after activation manipulation, performing next memory bank reading and writing data.
A kind of SDRAM control system, comprising:
Command reception module, for receiving each instruction SDRAM being carried out to reading and writing data, wherein, described SDRAM comprises at least two default memory banks, stores data corresponding to each instruction for circulating successively;
Data execution module, for performing the read-write operation of its corresponding data according to each instruction, wherein, carry out before data read-write operation completes in current memory storehouse, carry out the activation manipulation of next memory bank data, after activation manipulation, perform next memory bank reading and writing data.
SDRAM control method of the present invention and system thereof, by receiving each instruction SDRAM being carried out to reading and writing data, at least two default memory banks circulate successively and store data corresponding to each instruction, and the read-write operation of its corresponding data is performed according to each instruction, wherein, carry out in current memory storehouse before data read-write operation completes, carry out the activation manipulation of next memory bank data, next memory bank reading and writing data is performed after activation manipulation, thus reduce the interval time of accessing between each memory bank, improve the control efficiency of SDRAM.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the SDRAM control method of an embodiment;
Fig. 2 is the initialized schematic flow sheet of SDRAM of an embodiment;
Fig. 3 is the structural representation of the SDRAM control system of an embodiment;
Fig. 4 is the structural representation of the SDRAM control system interface module of an embodiment.
Embodiment
In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail.
Refer to the schematic flow sheet of the SDRAM control method of an embodiment in Fig. 1.
A kind of SDRAM control method, comprising:
S102, receives each instruction SDRAM being carried out to reading and writing data.
In this step, by receiving each instruction SDRAM being carried out to reading and writing data, improve the receiving efficiency of instruction.
S104, at least two default memory banks circulate successively and store data corresponding to each instruction.
Each memory bank of SDRAM stores data, and traditional mode is: first memory bank first stores data, and after first memory bank is filled with space, and then second memory bank store remaining data, so analogizes, until store all data.Due to the feature of SDRAM self, need constantly in Preset Time, to carry out precharge to all memory banks, refresh operation is carried out after precharge, the data refreshed in rear guarantee memory bank are not lost, traditional memory bank storage mode makes it that the mode of serial can only be adopted to carry out precharge to memory bank, the refresh operation that can complete in described Preset Time all memory banks can not be ensured, therefore, a refresh module need be increased, automatically refresh all memory banks by refresh module, thus preserve data.
This step is circulated successively by least two default memory banks and stores data corresponding to each instruction, make in follow-up data read-write operation, when current memory bank performs data read-write operation, other memory bank can carry out precharge operation simultaneously, refresh operation is carried out, therefore, without the need to increasing refresh module after precharge operation and then in time, also can complete the refresh operation to all memory banks in time in Preset Time, thus save system resource.
Further, described circulation successively stores data corresponding to each instruction, comprises circulation successively and stores the data of preset length corresponding to each instruction, thus facilitate the execution of follow-up data read-write operation.
Further, the data of described preset length are 32, and the quantity of at least two described memory banks is four.
Memory bank stores the data of 32 bit lengths at every turn, makes each read-write operation of SDRAM all will access the integer multiple data of 32, thus makes addressing data simple, reduces it and takies resource; And the memory bank of four quantity is while meeting data cached storage demand, reduce hardware cost to large extent.
Further, described circulation successively stores data corresponding to each instruction, also comprise and data corresponding for each instruction are carried out packet encapsulation, described packet comprises the header packet information of employing four one-hot codings and adopts the bag tail information of four corresponding one-hot codings.
Packet encapsulation is carried out to data, makes data in transmitting procedure, adopt the form of packet, improve the stability of data transmission; Described packet comprises header packet information and bag tail information, ensures the continuity of data packet transmission; Described header packet information and bag tail information adopt four corresponding one-hot codings respectively, such as, header packet information is four continuous print binary codings, be followed successively by: 1000,1100,1110,1111, bag tail information is similarly the corresponding binary coding of four continuous print, be followed successively by: 0111,0011,0001,0000, packet keeps high level in transmitting procedure, it is low level during end of transmission (EOT), only need according to the wherein coding in packet binary coding, the read-write state of data can be judged, thus improve the interference free performance of data.
S106, performs the read-write operation of its corresponding data according to each instruction, wherein, carry out before data read-write operation completes, carrying out the activation manipulation of next memory bank data, performing next memory bank reading and writing data after activation manipulation in current memory storehouse.
By this step, perform during data read-write operation in current memory storehouse, next memory bank can carry out activation manipulation in advance, thus reduces the time that each memory bank consumes owing to carrying out activation manipulation, improves the read-write efficiency of data further.
Further, the described read-write operation performing its corresponding data according to each instruction, comprises and gives different priority levels respectively by each instruction, sorts to each instruction according to described priority level; The read-write operation of each instruction corresponding data is performed according to ranking results.
Wherein, described sequence comprises and sorting continuously to the instruction of data continuous print.By carrying out priority level sequence to each instruction, can arrange continuous print data sequence on the one hand, realizing the continuous read-write of data; On the other hand for discontinuous data, the order that it performs read-write operation can be controlled, improve the dirigibility that data perform, strengthen Consumer's Experience.
Further, the described read-write operation performing each instruction corresponding data according to ranking results, be included in current memory storehouse to carry out when data read-write operation completes, completing the activation manipulation of next memory bank data, thus ensureing the integrality performing the data of read-write operation.
Further, describedly carry out before data read-write operation completes in current memory storehouse, carry out the activation manipulation of next memory bank data, being included in current memory storehouse carries out when data read-write operation completes, complete the activation manipulation of next memory bank data, after activation manipulation, perform next memory bank reading and writing data.So analogize, thus reduce the time that each memory bank consumes owing to carrying out activation manipulation to greatest extent, improve the read-write efficiency of data further.
In the present embodiment, by receiving each instruction SDRAM being carried out to reading and writing data, at least two default memory banks circulate successively and store data corresponding to each instruction, and the read-write operation of its corresponding data is performed according to each instruction, wherein, carry out in current memory storehouse before data read-write operation completes, carry out the activation manipulation of next memory bank data, next memory bank reading and writing data is performed after activation manipulation, thus reduce the interval time of accessing between each memory bank, improve the control efficiency of SDRAM.
Refer to the initialized schematic flow sheet of SDRAM of an embodiment in Fig. 2.
Wherein in an embodiment, described reception carries out each instruction of reading and writing data to SDRAM, also comprises before:
S202, receives charging time delay command, according to described charging time delay command, when arriving default delay time, carries out a precharge to the memory bank of SDRAM.
Further, described default delay time is 100 microseconds.
S204, when described precharge completes, carries out twice refreshing to described memory bank;
S206, when second time has refreshed, has carried out Initialize installation to SDRAM.
In the present embodiment, when described precharge completes, twice refreshing is carried out to memory bank described in each, to ensure the integrality that memory bank refreshes, and ensure that SDRAM can correctly initialization; Initialize installation is carried out to SDRAM, and then reduces the probability producing undefined mistake in SDRAM process, improve the efficiency of SDRAM.
Refer to the structural representation of the SDRAM control system of an embodiment in Fig. 3.
The present invention also provides a kind of SDRAM control system, comprising:
Command reception module 300, for receiving each instruction SDRAM being carried out to reading and writing data, wherein, described SDRAM comprises at least two default memory banks, stores data corresponding to each instruction for circulating successively.
Described command reception module 300 carries out each instruction of reading and writing data to SDRAM by receiving, improve the receiving efficiency of instruction; Circulated successively by least two default memory banks and store data corresponding to each instruction, make in follow-up data read-write operation, when current memory bank performs data read-write operation, other memory bank can carry out precharge operation simultaneously, refresh operation is carried out, therefore, without the need to increasing refresh module after precharge operation and then in time, also can complete the refresh operation to all memory banks in time in Preset Time, thus save system resource.
Data execution module 301, for performing the read-write operation of its corresponding data according to each instruction, wherein, carry out before data read-write operation completes in current memory storehouse, carry out the activation manipulation of next memory bank data, after activation manipulation, perform next memory bank reading and writing data.
Described data execution module 301 performs during data read-write operation in current memory storehouse, and next memory bank can carry out activation manipulation in advance, thus reduces the time that each memory bank consumes owing to carrying out activation manipulation, improves the read-write efficiency of data further.
In the present embodiment, command reception module 300 receives each instruction SDRAM being carried out to reading and writing data, and wherein, described SDRAM comprises at least two default memory banks, stores data corresponding to each instruction for circulating successively; Data execution module 301 performs the read-write operation of its corresponding data according to each instruction, wherein, carry out in current memory storehouse before data read-write operation completes, carry out the activation manipulation of next memory bank data, next memory bank reading and writing data is performed after activation manipulation, thus reduce the interval time of accessing between each memory bank, improve the control efficiency of SDRAM.
Wherein in an embodiment, described command reception module 300 also for the data storing preset length corresponding to each instruction that circulate successively, thus facilitates the execution of follow-up data read-write operation.
Further, the data of described preset length are 32, and the quantity of at least two described memory banks is four.Memory bank stores the data of 32 bit lengths at every turn, makes each read-write operation of SDRAM all will access the integer multiple data of 32, thus makes addressing data simple, reduces it and takies resource; And the memory bank of four quantity is while meeting data cached storage demand, reduce hardware cost to large extent.
Wherein in an embodiment, described command reception module 300 also comprises data encapsulation module, for data corresponding for each instruction are carried out packet encapsulation, described packet comprises the header packet information of employing four one-hot codings and adopts the bag tail information of four corresponding one-hot codings.
Packet encapsulation is carried out to data, makes data in transmitting procedure, adopt the form of packet, improve the stability of data transmission; Described packet comprises header packet information and bag tail information, ensures the continuity of data packet transmission; Described header packet information and bag tail information adopt four corresponding one-hot codings respectively, such as, header packet information is four continuous print binary codings, be followed successively by: 1000,1100,1110,1111, bag tail information is similarly the corresponding binary coding of four continuous print, be followed successively by: 0111,0011,0001,0000, packet keeps high level in transmitting procedure, it is low level during end of transmission (EOT), only need according to the wherein coding in packet binary coding, the read-write state of data can be judged, thus improve the interference free performance of data.
Wherein in an embodiment, described data execution module 301 comprises:
Sorting sub-module, for giving different priority levels respectively by each instruction, sorts to each instruction according to described priority level;
Data implementation sub-module, for performing the read-write operation of each instruction corresponding data according to ranking results.
In described sorting sub-module, described sequence comprises sorts continuously to the instruction of data continuous print.By carrying out priority level sequence to each instruction, can arrange continuous print data sequence on the one hand, realizing the continuous read-write of data; On the other hand for discontinuous data, the order that it performs read-write operation can be controlled, improve the dirigibility that data perform, strengthen Consumer's Experience.
Wherein in an embodiment, described data implementation sub-module also can not the data read-write operation of the low instruction of Interrupt Priority Level for the high instruction of priority level, thus ensures the integrality performing the data of read-write operation.
Wherein in an embodiment, described data execution module 301 also comprises:
Activating submodule, when data read-write operation completes, completing the activation manipulation of next memory bank data for carrying out in current memory storehouse.So analogize, thus reduce the time that each memory bank consumes owing to carrying out activation manipulation to greatest extent, improve the read-write efficiency of data further.
Wherein in an embodiment, described SDRAM control system also comprises:
Initialization module, for receiving charging time delay command, according to described charging time delay command, when arriving default delay time, carries out a precharge to the memory bank of SDRAM; When described precharge completes, twice refreshing is carried out to described memory bank; When second time has refreshed, Initialize installation is carried out to SDRAM.
In the present embodiment, initialization module, when described precharge completes, carries out twice refreshing to memory bank described in each, to ensure the integrality that memory bank refreshes, and ensures that SDRAM can correctly initialization; Initialize installation is carried out to SDRAM, and then reduces the probability producing undefined mistake in SDRAM process, improve the efficiency of SDRAM.
Further, as shown in Figure 4, described SDRAM control system also comprises interface module, and described interface module comprises task class interface, the enable interface of task, task start address interface, task start address latch enable interface, task read states packet interfaces, task write status data packet interface, time delay Token Interface, initialization complement mark interface, Data Input Interface, data output interface and SDRAM external interface.To be described in detail these interfaces below, as shown in the table:
Each technical characteristic of the above embodiment can combine arbitrarily, for making description succinct, the all possible combination of each technical characteristic in above-described embodiment is not all described, but, as long as the combination of these technical characteristics does not exist contradiction, be all considered to be the scope that this instructions is recorded.
The above embodiment only have expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a SDRAM control method, is characterized in that, comprising:
Receive each instruction SDRAM being carried out to reading and writing data, wherein, described SDRAM comprises at least two default memory banks, stores data corresponding to each instruction for circulating successively;
Perform the read-write operation of its corresponding data according to each instruction, wherein, carry out in current memory storehouse before data read-write operation completes, carrying out the activation manipulation of next memory bank data, after activation manipulation, performing next memory bank reading and writing data.
2. SDRAM control method according to claim 1, is characterized in that, described circulation successively stores data corresponding to each instruction, comprising:
Circulation stores the data of preset length corresponding to each instruction successively.
3. SDRAM control method according to claim 1 or 2, is characterized in that, described circulation successively stores data corresponding to each instruction, also comprises:
Data corresponding for each instruction are carried out packet encapsulation, and described packet comprises the header packet information of employing four one-hot codings and adopts the bag tail information of four corresponding one-hot codings.
4. SDRAM control method according to claim 1, is characterized in that, the described read-write operation performing its corresponding data according to each instruction, comprising:
Give different priority levels respectively by each instruction, according to described priority level, each instruction is sorted;
The read-write operation of each instruction corresponding data is performed according to ranking results.
5. SDRAM control method according to claim 4, is characterized in that, the described read-write operation performing each instruction corresponding data according to ranking results, comprising:
The high instruction of priority level can not the data read-write operation of the low instruction of Interrupt Priority Level.
6. SDRAM control method according to claim 1, is characterized in that, described carrying out in current memory storehouse before data read-write operation completes, carries out the activation manipulation of next memory bank data, comprising:
Carry out in current memory storehouse when data read-write operation completes, completing the activation manipulation of next memory bank data.
7. SDRAM control method according to claim 1, is characterized in that, described reception carries out each instruction of reading and writing data to SDRAM, also comprises before:
Receiving charging time delay command, according to described charging time delay command, when arriving default delay time, a precharge being carried out to the memory bank of SDRAM;
When described precharge completes, twice refreshing is carried out to described memory bank;
When second time has refreshed, Initialize installation is carried out to SDRAM.
8. a SDRAM control system, is characterized in that, comprising:
Command reception module, for receiving each instruction SDRAM being carried out to reading and writing data, wherein, described SDRAM comprises at least two default memory banks, stores data corresponding to each instruction for circulating successively;
Data execution module, for performing the read-write operation of its corresponding data according to each instruction, wherein, carry out before data read-write operation completes in current memory storehouse, carry out the activation manipulation of next memory bank data, after activation manipulation, perform next memory bank reading and writing data.
9. SDRAM control system according to claim 8, is characterized in that, described data execution module comprises:
Sorting sub-module, for giving different priority levels respectively by each instruction, sorts to each instruction according to described priority level;
Data implementation sub-module, for performing the read-write operation of each instruction corresponding data according to ranking results.
10. SDRAM control system according to claim 8, is characterized in that, also comprise:
Initialization module, for receiving charging time delay command, according to described charging time delay command, when arriving default delay time, carries out a precharge to the memory bank of SDRAM; When described precharge completes, twice refreshing is carried out to described memory bank; When second time has refreshed, Initialize installation is carried out to SDRAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510744798.5A CN105302748A (en) | 2015-11-03 | 2015-11-03 | SDRAM control method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510744798.5A CN105302748A (en) | 2015-11-03 | 2015-11-03 | SDRAM control method and system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105302748A true CN105302748A (en) | 2016-02-03 |
Family
ID=55200033
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510744798.5A Pending CN105302748A (en) | 2015-11-03 | 2015-11-03 | SDRAM control method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105302748A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010043505A1 (en) * | 2000-05-22 | 2001-11-22 | Jae-Hyeong Lee | Integrated circuit memory devices that utilize indication signals to increase reliability of reading and writing operations and methods of operating same |
| US6359832B2 (en) * | 2000-01-31 | 2002-03-19 | Infineon Technologies Ag | Method and circuit configuration for read-write mode control of a synchronous memory |
| CN101340365A (en) * | 2008-08-11 | 2009-01-07 | 杭州瑞纳科技有限公司 | Design method of DDR2 SDRAM controller of high bandwidth utilization |
-
2015
- 2015-11-03 CN CN201510744798.5A patent/CN105302748A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6359832B2 (en) * | 2000-01-31 | 2002-03-19 | Infineon Technologies Ag | Method and circuit configuration for read-write mode control of a synchronous memory |
| US20010043505A1 (en) * | 2000-05-22 | 2001-11-22 | Jae-Hyeong Lee | Integrated circuit memory devices that utilize indication signals to increase reliability of reading and writing operations and methods of operating same |
| CN101340365A (en) * | 2008-08-11 | 2009-01-07 | 杭州瑞纳科技有限公司 | Design method of DDR2 SDRAM controller of high bandwidth utilization |
Non-Patent Citations (2)
| Title |
|---|
| 人力资源和社会保障部职业技能鉴定中心: "《物联网应用技术》", 31 October 2014, 东营：石油大学出版社 * |
| 李燕萍: "基于FPGA的连续存储系统实现", 《中国优秀硕士学位论文全文数据库·信息科技辑》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9721640B2 (en) | Performance of additional refresh operations during self-refresh mode | |
| CN106856098B (en) | Device and method for refreshing DRAM or eDRAM | |
| US20030218930A1 (en) | Partial refresh for synchronous dynamic random access memory (sdram) circuits | |
| CN101916227B (en) | RLDRAM SIO storage access control method and device | |
| US20070274303A1 (en) | Buffer management method based on a bitmap table | |
| US20170300419A1 (en) | Memory access method, storage-class memory, and computer system | |
| CN103019974B (en) | memory access processing method and controller | |
| US11256568B2 (en) | Memory management systems and methods | |
| CN110322909A (en) | Current amplitude and duration during customizing programming pulse for memory devices | |
| EP2997576A1 (en) | Methods and systems for smart refresh of dynamic random access memory | |
| CN104505117A (en) | Dynamic memory refreshing method and refreshing controller | |
| US9685220B2 (en) | DDR controller, method for implementing the same, and chip | |
| CN110347621A (en) | The FPGA and storage system being connect with PSRAM memory | |
| US20160099042A1 (en) | Devices, Systems and Methods of Setting Machines | |
| CN102541769A (en) | Memory interface access control method and device | |
| CN105487988B (en) | The method for improving the effective access rate of SDRAM bus is multiplexed based on memory space | |
| US9966129B1 (en) | Controller and control method for dynamic random access memory | |
| CN105321548A (en) | Bank control circuit and semiconductor memory device including the same | |
| CN102751966B (en) | The latent time control circuit of delay circuit and memorizer and signal delay method thereof | |
| US20020136079A1 (en) | Semiconductor memory device and information processing system | |
| CN110970070B (en) | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers | |
| CN100370436C (en) | Method for improving storage access efficiency and storage coutroller | |
| US10878879B2 (en) | Refresh control method for memory system to perform refresh action on all memory banks of the memory system within refresh window | |
| CN105302748A (en) | SDRAM control method and system | |
| CN105304119A (en) | Refresh circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160203 |