CN105282070A - Reliability design method applied to communication protocol receiving end - Google Patents
Reliability design method applied to communication protocol receiving end Download PDFInfo
- Publication number
- CN105282070A CN105282070A CN201510735068.9A CN201510735068A CN105282070A CN 105282070 A CN105282070 A CN 105282070A CN 201510735068 A CN201510735068 A CN 201510735068A CN 105282070 A CN105282070 A CN 105282070A
- Authority
- CN
- China
- Prior art keywords
- signal
- reliability design
- communication
- system clock
- communication protocol
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006854 communication Effects 0.000 title claims abstract description 33
- 238000004891 communication Methods 0.000 title claims abstract description 32
- 238000000034 method Methods 0.000 title claims abstract description 18
- 230000000694 effects Effects 0.000 claims abstract description 11
- 230000008439 repair process Effects 0.000 claims abstract description 10
- 238000005070 sampling Methods 0.000 claims description 9
- 230000000630 rising effect Effects 0.000 claims description 6
- 230000011514 reflex Effects 0.000 claims description 5
- 241001269238 Data Species 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims description 3
- 238000003708 edge detection Methods 0.000 claims description 3
- 230000008030 elimination Effects 0.000 claims description 3
- 238000003379 elimination reaction Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000000284 extract Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000036039 immunity Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Landscapes
- Dc Digital Transmission (AREA)
Abstract
The invention discloses a reliability design method applied to a communication protocol receiving end.A system clock firstly eliminates high-frequency burrs of a communication signal, further eliminates the reflection effect of the signal, repairs the problem of signal integrity and is convenient for subsequent processing of the communication signal. Compared with the prior art, the reliability design method applied to the communication protocol receiving end has the characteristics of simplicity and convenience in implementation, diversification, strong anti-interference performance, wide application and the like, and has a wide application prospect.
Description
Technical field
The present invention relates to electronic technology field, specifically a kind of practical, reliability design approach of being applied to communication protocol receiving terminal.
Background technology
Time signal of communication is along transmission line onwards transmission, can run into certain impedance, if this impedance is constant, so signal of communication is stable; Otherwise run into any factor causing impedance variation, as resistance, electric capacity, inductance, terminal equipment etc., can there is reflection effect in signal of communication.Reflection coefficient is the important indicator of reflected signal reflection, supposes that the impedance before changing is Z
1, the impedance after change is Z
2, signal voltage is V, so impedance factor
, reflected voltage is
.This shows that reflected voltage can change the waveform of signal of communication, have significant impact in the judgement of communication receiver to signal.PS2 agreement, the communication protocols such as I2C agreement need to process based on signal edge, if the side information of acquisition signal that can not be correct, follow-up process just can not get ensureing, and in communication process, unavoidably have the appearance of frequency glitches.Based on this, now provide a kind of reliability design approach being applied to communication protocol receiving terminal, be used for specially eliminating frequency glitches, and then erasure signal reflection effect.
Summary of the invention
Technical assignment of the present invention is for above weak point, provides a kind of practical, reliability design approach of being applied to communication protocol receiving terminal.
A kind of reliability design approach being applied to communication protocol receiving terminal, its implementation procedure is, system clock first carries out frequency glitches elimination to signal of communication, and then the reflection effect of erasure signal, the problem of signal integrity is repaired, is convenient to the follow-up process to signal of communication.
The process of described reliability design is: first system clock compares signal sampling, then extracts signal edge, after frequency glitches is eliminated in shielding, and repair signal, inhibit signal integrality.
The detailed process of described reliability design is:
System clock first carries out double sampling with the probabilistic propagation of erasure signal to signal, and then again to its double sampling, compares three sampled datas below;
When these three signal values are " 101 " or " 010 ", middle " 0 " or " 1 " is frequency glitches, because the frequency glitches duration is less than system clock cycle, so this " 0 " or " 1 " will be eliminated, when system clock detects " 1x1 " or " 0x0 ", just be judged to be " 111 " or " 000 ", thus eliminate frequency glitches;
When signal trailing edge being detected, the repair signal reset of output, counts simultaneously and counts from 1, count down to preset value CNT always, before counter counts counts to CNT, and no longer detection signal rising edge; When running into trailing edge, counter counts again from 1, until count down to CNT, then opens rising edge detection;
When detect signal falls along time, the repair signal set of output, in other situation, signal remains unchanged, thus, the frequency glitches in communication and just completely eliminating due to the impedance signal reflex effect caused that changes.
A kind of reliability design approach being applied to communication protocol receiving terminal of the present invention, has the following advantages:
Be easy to implement and diversified, the present invention's design can pass through single-chip microcomputer, CPLD, FPGA, and even ASIC realization, execution mode has diversified feature.
Strong interference immunity, the frequency glitches that the present invention's design not only can occur in erasure signal transmission, and can remove the signal reflex effect in communication.
Be widely used, the present invention's design can be applied to PS2 agreement, also can be applied to I2C bus protocol, but be not limited only to PS2/I2C agreement, this method for designing all can be applied to improve the reliability of signal in every place with frequency glitches and signal reflex effect, practical, is easy to promote.
Accompanying drawing explanation
Accompanying drawing 1 realizes block diagram for design of the present invention.
Accompanying drawing 2 is design sequential chart of the present invention.
Embodiment
Below in conjunction with the drawings and specific embodiments, the invention will be further described.
The invention provides a kind of reliability design approach being applied to communication protocol receiving terminal, as shown in Figure 1, its implementation procedure is, system clock first carries out frequency glitches elimination to signal of communication, and then the reflection effect of erasure signal, the problem of signal integrity is repaired, is convenient to the follow-up process to signal of communication.
The process of described reliability design is: first system clock compares signal sampling, then extracts signal edge, after frequency glitches is eliminated in shielding, and repair signal, inhibit signal integrality.
The detailed process of described reliability design is:
System clock first carries out 2 samplings with the probabilistic propagation of erasure signal to signal, and then again to its 2 times samplings, 3 sampled datas are below compared, if these 3 signal values are " 101 " or " 010 ", " 0 " or " 1 " is so frequency glitches, because the frequency glitches duration can not exceed system clock cycle, so need to eliminate this " 0 " or " 1 ".
At this, as long as system clock detects " 1x1 " or " 0x0 ", be just judged to be " 111 " or " 000 ", thus eliminate frequency glitches.
Manage on basis herein, the frequency glitches of signal is eliminated, so when signal edge again being detected, that must be the edge of primary signal, instead of noise.
If signal trailing edge detected, the repair signal reset exported, counts simultaneously and counts from 1, count down to preset value CNT always, before counter counts counts to CNT, no longer detection signal rising edge, be equivalent to the primary signal of this time period to shield, but trailing edge still detects, run into trailing edge, counter will count again from 1, until count down to CNT, then open rising edge detection; If detect afterwards and edge falls in signal, the repair signal set of output, in other situation, signal remains unchanged.
Thus, the frequency glitches in communication and just completely eliminating due to the impedance signal reflex effect caused that changes.The sequential chart of this reliability design as shown in Figure 2.
Above-mentioned embodiment is only concrete case of the present invention; scope of patent protection of the present invention includes but not limited to above-mentioned embodiment; any according to the invention a kind of be applied to claims of the reliability design approach of communication protocol receiving terminal and the those of ordinary skill of any described technical field to its suitable change done or replacement, all should fall into scope of patent protection of the present invention.
Claims (3)
1. one kind is applied to the reliability design approach of communication protocol receiving terminal, it is characterized in that, its implementation procedure is, system clock first carries out frequency glitches elimination to signal of communication, and then the reflection effect of erasure signal, the problem of signal integrity is repaired, is convenient to the follow-up process to signal of communication.
2. a kind of reliability design approach being applied to communication protocol receiving terminal according to claim 1, it is characterized in that, the process of described reliability design is: first system clock compares signal sampling, then signal edge is extracted, after frequency glitches is eliminated in shielding, repair signal, inhibit signal integrality.
3. a kind of reliability design approach being applied to communication protocol receiving terminal according to claim 2, is characterized in that, the detailed process of described reliability design is:
System clock first carries out double sampling with the probabilistic propagation of erasure signal to signal, and then again to its double sampling, compares three sampled datas below;
When these three signal values are " 101 " or " 010 ", middle " 0 " or " 1 " is frequency glitches, because the frequency glitches duration is less than system clock cycle, so this " 0 " or " 1 " will be eliminated, when system clock detects " 1x1 " or " 0x0 ", just be judged to be " 111 " or " 000 ", thus eliminate frequency glitches;
When signal trailing edge being detected, the repair signal reset of output, counts simultaneously and counts from 1, count down to preset value CNT always, before counter counts counts to CNT, and no longer detection signal rising edge; When running into trailing edge, counter counts again from 1, until count down to CNT, then opens rising edge detection;
When detect signal falls along time, the repair signal set of output, in other situation, signal remains unchanged, thus, the frequency glitches in communication and just completely eliminating due to the impedance signal reflex effect caused that changes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510735068.9A CN105282070A (en) | 2015-11-03 | 2015-11-03 | Reliability design method applied to communication protocol receiving end |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510735068.9A CN105282070A (en) | 2015-11-03 | 2015-11-03 | Reliability design method applied to communication protocol receiving end |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105282070A true CN105282070A (en) | 2016-01-27 |
Family
ID=55150414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510735068.9A Pending CN105282070A (en) | 2015-11-03 | 2015-11-03 | Reliability design method applied to communication protocol receiving end |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105282070A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109309637A (en) * | 2018-10-08 | 2019-02-05 | 惠科股份有限公司 | Data storage method, device and storage medium for transmission signals |
| CN112526155A (en) * | 2020-11-16 | 2021-03-19 | 中国航空工业集团公司西安航空计算技术研究所 | Configurable rotating speed signal acquisition method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101141123A (en) * | 2007-10-11 | 2008-03-12 | 电子科技大学 | Burr testing apparatus |
| CN101568237A (en) * | 2009-05-19 | 2009-10-28 | 中兴通讯股份有限公司 | Method and device for eliminating signal noise |
| CN101593221A (en) * | 2008-05-28 | 2009-12-02 | 北京中电华大电子设计有限责任公司 | A kind of foreign lands' clock that prevents dynamically switches the Method and circuits of burr |
| CN102195619A (en) * | 2010-03-02 | 2011-09-21 | 国民技术股份有限公司 | Method and circuit for detecting and eliminating signal glitch |
| CN104467753A (en) * | 2014-11-28 | 2015-03-25 | 深圳中科讯联科技有限公司 | Jump edge detection method and device with glitches capable of being removed |
-
2015
- 2015-11-03 CN CN201510735068.9A patent/CN105282070A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101141123A (en) * | 2007-10-11 | 2008-03-12 | 电子科技大学 | Burr testing apparatus |
| CN101593221A (en) * | 2008-05-28 | 2009-12-02 | 北京中电华大电子设计有限责任公司 | A kind of foreign lands' clock that prevents dynamically switches the Method and circuits of burr |
| CN101568237A (en) * | 2009-05-19 | 2009-10-28 | 中兴通讯股份有限公司 | Method and device for eliminating signal noise |
| CN102195619A (en) * | 2010-03-02 | 2011-09-21 | 国民技术股份有限公司 | Method and circuit for detecting and eliminating signal glitch |
| CN104467753A (en) * | 2014-11-28 | 2015-03-25 | 深圳中科讯联科技有限公司 | Jump edge detection method and device with glitches capable of being removed |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109309637A (en) * | 2018-10-08 | 2019-02-05 | 惠科股份有限公司 | Data storage method, device and storage medium for transmission signals |
| WO2020073440A1 (en) * | 2018-10-08 | 2020-04-16 | 惠科股份有限公司 | Data storage method and device for transmission signal and storage medium |
| US11206156B2 (en) | 2018-10-08 | 2021-12-21 | HKC Corporation Limited | Method and apparatus for storing data of transmission signal, and computer readable storage medium |
| CN112526155A (en) * | 2020-11-16 | 2021-03-19 | 中国航空工业集团公司西安航空计算技术研究所 | Configurable rotating speed signal acquisition method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108267638B (en) | Power frequency synchronous communication signal detection device, system and method based on power frequency distortion | |
| CN102147426B (en) | Broadband triggering circuit of digital oscilloscope | |
| CN105282070A (en) | Reliability design method applied to communication protocol receiving end | |
| CN107395157A (en) | Grounded screen potential difference filtering method based on wavelet transformation and weighted moving average | |
| WO2016004687A1 (en) | Method for distinguishing initial time point of ultra-high-frequency partial discharge signal | |
| CN101499862B (en) | Mobile phone noise signal distinguishing method in electric appliance extra-high-frequency local discharging detection | |
| CN204287307U (en) | Transformer, current detection circuit based on transformer | |
| CN201859177U (en) | Measurement module for low-frequency alternating current signal in relay protection device | |
| CN203574663U (en) | Automatic baud rate detection module | |
| CN201590659U (en) | Surge response protection circuit of induction cooker | |
| CN204008849U (en) | Commercial power detection device | |
| CN106546830B (en) | A kind of N phase voltage phase shortage and negative phase sequence detection method | |
| CN104682981A (en) | Decoding board of ADS-B (automatic dependent surveillance broadcast) receiver | |
| CN104953985B (en) | A kind of digital filter circuit being applied in Long line transmission system | |
| CN203733113U (en) | Data flow reversing control circuit applied to RS485 interface | |
| CN104518755A (en) | Digital circuit noise filter and digital filtering method | |
| CN203961717U (en) | A kind of fire-proof roll screen control that there is the automatic detection of phase sequence and adjust function | |
| CN203672481U (en) | Electric equipment noise detection device | |
| CN102508108B (en) | Method for softly starting traveling wave in low signal to noise ratio | |
| CN103018580B (en) | Method and device for detecting vector transformation of three-phase power phase sequence | |
| CN109768792B (en) | Anti-interference detection device and method for capacitive touch key | |
| CN114637717A (en) | Detection circuit and differential receiver | |
| CN102841303B (en) | Serial peripheral interface (SPI) anomaly detection method and SPI anomaly detection device | |
| CN103078298A (en) | Overcurrent cascade protection circuit of IGBT (Insulated Gate Bipolar Translator) and control method thereof | |
| CN101699689A (en) | Surge response protection circuit of induction cooker |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160127 |
|
| WD01 | Invention patent application deemed withdrawn after publication |