CN105281886B - The timing control signal production method and device of cold ion quantum information processor - Google Patents
The timing control signal production method and device of cold ion quantum information processor Download PDFInfo
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- CN105281886B CN105281886B CN201510807889.9A CN201510807889A CN105281886B CN 105281886 B CN105281886 B CN 105281886B CN 201510807889 A CN201510807889 A CN 201510807889A CN 105281886 B CN105281886 B CN 105281886B
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Abstract
The invention discloses the timing control signal production methods of cold ion quantum information processor, are instructed on host computer by host computer and set radiofrequency signal and digital signal parameters；Host computer instruction map for machine instruction and is transferred to timing control FPGA；Timing control FPGA performs machine instruction and passes through the output of modular converter and radio frequency synthesis module progress digital signal and radiofrequency signal.The invention also discloses the timing control signal generation devices of cold ion quantum information processor, including host computer, further include time-sequence control module, radio frequency synthesis module and modular converter, the present invention realizes the directviewing description to timing control signal needed for experiment；The host computer instruction of establishment can avoid repeated work with Reusability, and convenient for according to experimental result constantly improve；The parameters such as the frequency, phase, amplitude of radiofrequency signal can easily be changed；Accurately control multi-way control signals collaborative work；Autgmentability is strong.
Description
Technical field
The present invention relates to cold atom (ion) quantum information experimental fields, and in particular to cold ion quantum information processor
Timing control signal generation device further relates to the timing control signal production method of cold ion quantum information processor, is suitable for
The generation of timing control signal, is also suitable for the fields such as optics frequency marking, quantum optices in the experiment of cold atom (ion) quantum information.
Background technology
The development and the continuous progress of scientific research maked rapid progress with semiconductor technology, the heavy demand of information technology
Traction will make computer characteristic size quickly approach physics limit, and classic computer faces many bottles such as arithmetic speed and power consumption
Neck！In this process, various quantum effects can display and eventually become the universal behavior of microcosmic particle under minute yardstick, most
Cause the failure of classic computer eventually.It is known clearly with the rapid progress of physics and to the deep of computer essence, the amount of combining
The emerging cross discipline of sub- mechanics, informatics and computer science --- quantum calculation science is come into being, and is had become now
One of scientific and technological commanding elevation that countries in the world are competitively fought for.
Quantum calculation utilizes some peculiar properties of quantum regime（Coherent superposition, quantum entanglement etc.）To calculating, encoding, believing
Breath processing procedure gives new annotation, to develop the new more efficiently information processing function.Amount based on quantum coherence
It is traditional counting that sub- computer, which possesses the parallel computation of Inner official reports and processing capacity, the potentiality in terms of calculating speed and storage capacity,
Machine is incomparable！The work that some classic computers cannot be completed（Such as crack the security system of existing bank）In quantum calculation
Completion that can be quickly on machine, therefore the numerous areas such as high-performance calculation, intelligence analysis, information security can be widely used in.In addition,
Quantum simulation technology based on quantum calculation significantly more efficient can solve classic computer and classic algorithm is difficult to solve or nothing
The fundamental problem of quantum mechanics that method solves, it will help further understanding associates by force the physical property of multi-body system to people, and then becomes
Generate new material or neoteric basic research means.
The developed countries such as the U.S., Europe, Japan are all subsidizing the key technology research of quantum calculation at present, are directed to
The Physical realization of quantum calculation includes ion trap, quantum dot, linear optics, superconduction etc..Although it can't judge at present most
Whole quantum calculation chance uses wherein which kind of scheme, but scientist generally believes the physics system that can realize quantum computer
Divincenzo criterions should be met.
Ion trap system is the physics system for theoretically proving to carry out quantum calculation earliest, and institute is met from principle
Some Divincenzo criterions, and most of criterion has been confirmed in experiment.Since ion trap system has, coherence time is long, is easy to
The advantages such as manipulation, are one of quantum calculation physics systems with the fastest developing speed, are also considered as quantum calculation physics realization most
One of promising scheme.
Typically atom is used at one（Ion）On the device for studying quantum calculation, user needs that quantum bit is implemented to grasp
Make.These operations, which are finally attributed to, creates a series of specific amplitude, phase, frequency and the laser of duration or microwave arteries and veins
Punching.The problem run into repeatedly in experiment is, how on the premise of the few mistake of few resource and introducing is used as far as possible,
The Sequence Transformed reality for needed for operation quantum bit of the predetermined pulse of directviewing description in the general purpose personal computer of user
Timing control pulse signal.
Solve the problems, such as that this method is segmented into two parts.First, required sequential control is described using proper method
Signal processed；Second is that one device of design, i.e. pulse sequence generator, the actual generation of the described timing control signal of back
Out.
The content of the invention
Object of the present invention is to provide the timing control signal production methods of cold ion quantum information processor.It can be with
Intuitively, pulse signal description is compactly realized, when manipulating quantum bit and various needed for Quantum logic gates so as to automatically generate
Sequence control signal.
The present invention also aims to provide the timing control signal generation device of cold ion quantum information processor, use
Family can be by pre-setting various experiments（Such as the cooling of Doppler cooling, sideband, the scanning of Zeeman spectrums and Rabi spectrum scannings
Deng）The parameter of required timing control signal, so that it may automatically generate corresponding timing control signal in an experiment.It avoids heavy
Repeated work saves substantial amounts of manpower and time.Meanwhile by the actual effect of experiment, can accordingly it be believed with constantly improve
Number parameter value is conducive to that experimental precision is continuously improved.
The timing control signal production method of cold ion quantum information processor, comprises the following steps：
Step 1, on host computer, pass through host computer instruction set quantum information test needed for radiofrequency signal parameter, radio frequency
Signal parameter includes the frequency values of radiofrequency signal, the amplitude of radiofrequency signal, the initial phase value of radiofrequency signal and radiofrequency signal
Duration；The low and high level signal and number that quantum information is set to test required digital signal parameters are instructed by host computer
The duration of signal,
Host computer instruction includes：Instruction wait is waited, for setting holding for the duration of radiofrequency signal and digital signal
The continuous time；Waveform frequency instructs frequency, for setting the frequency values of radiofrequency signal；Waveforms amplitude instructs dac, for setting
Put the amplitude of radiofrequency signal；Waveform initial phase instructs phase, for the initial phase value of radiofrequency signal；Numeral output instructs
Do, for setting the low and high level signal of digital signal,
Step 2, on host computer, by Labview softwares will characterize step 1 in each radiofrequency signal and digital signal
The host computer instruction map of parameter is the machine instruction of corresponding timing control FPGA, and machine instruction is passed through Ethernet interface
Circuit transmission gives timing control FPGA,
After step 3, timing control FPGA receive machine instruction, memory is first stored in, then takes out and performs one by one.
If the corresponding waveform frequency for radiofrequency signal of machine instruction instructs frequency, timing control FPGA to pass through
The frequency values of radiofrequency signal are transferred to radio frequency synthesis FPGA by level shifting circuit, and radio frequency synthesis FPGA receives radiofrequency signal
Direct digital synthesiser is set to cause the radiofrequency signal of direct digital synthesiser output respective frequencies value, Direct Digital after frequency values
The radiofrequency signal of synthesizer output exports after passing sequentially through variable gain amplifier, power amplifier and wave filter；
Instruct dac, timing control FPGA that will be penetrated by level shifting circuit for waveforms amplitude if machine instruction is corresponding
The amplitude of frequency signal is transferred to radio frequency synthesis FPGA, and radio frequency synthesizes FPGA and controls digital analog converter according to the amplitude of radiofrequency signal
Output, and then pass through the gain of digital analog converter control variable gain amplifier；
For waveform initial phase phase, timing control FPGA is instructed to pass through level conversion electricity if machine instruction is corresponding
The initial phase value of radiofrequency signal is transferred to radio frequency synthesis FPGA by road, and radio frequency synthesis FPGA receives the initial phase of radiofrequency signal
Direct digital synthesiser is set to cause the radiofrequency signal of the corresponding initial phase value of direct digital synthesiser output, directly number after place value
The radiofrequency signal of word synthesizer output exports after passing sequentially through variable gain amplifier, power amplifier and wave filter；
If machine instruction it is corresponding wait instruction wait, timing control FPGA maintained within the stand-by period radiofrequency signal with
The frequency values of current radio frequency signal, the amplitude of radiofrequency signal, the initial phase value of radiofrequency signal carry out continuing output；Timing control
FPGA maintains digital signal persistently to be exported with current low and high level signal within the stand-by period.
If the corresponding numeral output to set experiment required of machine instruction instructs do, timing control FPGA（3）According to
The low and high level signal of digital signal passes through level shifting circuit output digit signals.
The digital signal of step 4, the radiofrequency signal of wave filter output and digital signal output circuit output is loaded into AOM
On.AOM is modulated the laser for being transmitted through coming from laser according to the radiofrequency signal and digital signal of input.The width of radiofrequency signal
The power of degree control laser, the phase of the phase controlling laser of radiofrequency signal, the frequency of radiofrequency signal then carry out shift frequency to laser
Operation；Digital signal then controls the break-make of laser.Laser light incident after being modulated by AOM is mutual with cold ion into ion trap
Effect.
The timing control signal generation device of cold ion quantum information processor, including host computer, further includes timing control
Module, radio frequency synthesis module and modular converter,
Time-sequence control module includes ethernet interface circuit, timing control FPGA and memory,
Modular converter includes level shifting circuit, digital signal output circuit and external trigger input circuit,
Radio frequency synthesis module includes radio frequency synthesis FPGA, direct digital synthesiser, digital analog converter, variable gain amplification
Device, power amplifier and wave filter,
Host computer is connected by ethernet interface circuit with timing control FPGA, timing control FPGA and memory（4）Connection；
Timing control FPGA is connected with level shifting circuit, and level shifting circuit synthesizes FPGA, digital signal output electricity with radio frequency respectively
Road, the connection of external trigger input circuit, radio frequency synthesis FPGA is connected respectively with direct digital synthesiser and digital analog converter, variable
Gain amplifier is connected respectively with direct digital synthesiser, digital analog converter and power amplifier, power amplifier and wave filter
Connection.
Radio frequency synthesis module number as described above is 2 or 2 or more.
Compared with prior art, the present invention it has the advantages that：
1st, the directviewing description to timing control signal needed for experiment is realized；
2nd, the host computer instruction of establishment can avoid repeated work with Reusability, and convenient for continuous according to experimental result
It is perfect；
3rd, the parameters such as the frequency, phase, amplitude of radiofrequency signal can easily be changed；
4th, control speed fast, the radiofrequency signal switching of different parameters can be completed within tens nanoseconds；
5th, accurate phase associated radio frequency signal can be generated；
6th, multi-way control signals collaborative work is accurately controlled；
7th, autgmentability is strong, can be readily added radiofrequency signal way；
8th, device presses function modoularization, is connected between plate using LVDS buses, and circuit interference is few, and failure can be determined rapidly
Position.
Description of the drawings
Fig. 1 is the timing control signal generation device principle schematic of cold ion quantum information processor；
Wherein：1- host computers, 2- ethernet interface circuits, 3- timing control FPGA（Field Programmable Gate
Array, FPGA）, 4- memories, 5- level shifting circuits, 6- digital signal output circuits, 7- external trigger input circuits, 8- penetrates
Frequency synthesis FPGA, 9- direct digital synthesisers（DDS, Direct Digital Synthesizer）, 10- digital analog converters
（DAC, Digital to Analog Converter）, 11- variable gain amplifiers（VGA, Variable Gain
Amplifier）, 12- power amplifiers, 13- wave filters.A- radio frequency synthesis modules；B- time-sequence control modules；C- interconnecting modules.
Fig. 2 is a kind of example of physical system；
Wherein：14- lasers, 15- AOM（Acousto-optic modulator, Acousto-optical Modulators）, 16- ions
Trap.
The laser 14 includes pumping source and Ti∶Sapphire laser chamber, the first steady chamber and super steady chamber of high fineness；The acousto-optic tune
Device 15 processed includes acousto-optic modulation crystal and driving source；It is true that the ion trap systems 16 include the cold ion of electromagnetism imprison, superelevation
Cavity, vacuum pump, radio frequency source, field coil, laser optical path and ion fluorescence harvester.
Fig. 3 is the timing control signal production method flow diagram of cold ion quantum information processor；
Fig. 4 is timing control signal waveform illustrated example needed for experiment；
Fig. 5 generates the instruction set of control signal shown in Fig. 4.
Specific embodiment
Technical scheme is described in further detail below in conjunction with attached drawing.
As shown in Fig. 2, the timing control signal production method of cold ion quantum information processor, comprises the following steps：
Step 1, on host computer, pass through host computer instruction set quantum information test needed for radiofrequency signal parameter, radio frequency
Signal parameter includes the frequency values of radiofrequency signal, the amplitude of radiofrequency signal, the initial phase value of radiofrequency signal and radiofrequency signal
Duration；The low and high level signal and number that quantum information is set to test required digital signal parameters are instructed by host computer
The duration of signal.
Host computer instruction includes：Instruction wait is waited, for setting holding for the duration of radiofrequency signal and digital signal
The continuous time；Waveform frequency instructs frequency, for setting the frequency values of radiofrequency signal；Waveforms amplitude instructs dac, for setting
Put the amplitude of radiofrequency signal；Waveform initial phase instructs phase, for the initial phase value of radiofrequency signal；Numeral output instructs
Do, for setting the low and high level signal of digital signal.
Step 2, on host computer, by Labview softwares will characterize step 1 in each radiofrequency signal and digital signal
The host computer instruction map of parameter is the machine instruction of corresponding timing control FPGA3, and machine instruction is connect by Ethernet
Mouth circuit 2 is transferred to timing control FPGA3.
After step 3, timing control FPGA3 receive machine instruction, memory 4 is first stored in, then takes out and performs one by one.
If the corresponding waveform frequency for radiofrequency signal of machine instruction instructs frequency, timing control FPGA3 to pass through
The frequency values of radiofrequency signal are transferred to radio frequency synthesis FPGA8 by level shifting circuit 5, and radio frequency synthesis FPGA8 receives radio frequency letter
Number frequency values after set direct digital synthesiser 9 so that direct digital synthesiser 9 export respective frequencies value radiofrequency signal, directly
Connect digital synthesizer 9 output radiofrequency signal pass sequentially through variable gain amplifier 11, power amplifier 12 and wave filter 13 after
Output；
If machine instruction is corresponding to instruct dac for waveforms amplitude, timing control FPGA3 will by level shifting circuit 5
The amplitude of radiofrequency signal is transferred to radio frequency synthesis FPGA8, and radio frequency synthesizes FPGA8 and controls digital-to-analogue conversion according to the amplitude of radiofrequency signal
The output of device 10, and then pass through the gain of the control variable gain amplifier 11 of digital analog converter 10；
For waveform initial phase phase, timing control FPGA3 is instructed to pass through level conversion electricity if machine instruction is corresponding
The initial phase value of radiofrequency signal is transferred to radio frequency synthesis FPGA8 by road 5, and radio frequency synthesis FPGA8 receives the first of radiofrequency signal
Direct digital synthesiser 9 is set to cause the radiofrequency signal of the corresponding initial phase value of the output of direct digital synthesiser 9 after beginning phase value,
The radiofrequency signal that direct digital synthesiser 9 exports passes sequentially through variable gain amplifier 11, power amplifier 12 and wave filter 13
After export；
If machine instruction is corresponding instruction wait, timing control FPGA3 is waited to maintain radiofrequency signal within the stand-by period
It carries out continuing output with the initial phase value of the frequency values of current radio frequency signal, the amplitude of radiofrequency signal, radiofrequency signal；Sequential control
FPGA3 processed maintains digital signal persistently to be exported with current low and high level signal within the stand-by period.
If machine instruction is corresponding for the numeral output needed for experiment is set to instruct do, timing control FPGA3 is according to number
The low and high level signal of word signal passes through 5 output digit signals of level shifting circuit.
The digital signal that the radiofrequency signal and digital signal output circuit 6 that step 4, wave filter 13 export export is loaded into
On AOM15.AOM15 is modulated the laser for being transmitted through coming from laser 14 according to the radiofrequency signal and digital signal of input.It penetrates
The power of the amplitude control laser of frequency signal, the phase of the phase controlling laser of radiofrequency signal, the frequency of radiofrequency signal is then to swashing
Light carries out shift frequency operation；Digital signal then controls the break-make of laser.Laser light incident after being modulated by AOM15 is to ion trap 16
In with cold ionic interaction.Swap operation and CNOT gate operation are realized under the effect of the laser pulse of different amplitudes and phase.
As shown in Figure 1, the timing control signal generation device of cold ion quantum information processor include time-sequence control module,
Interconnecting module, radio frequency synthesis module and host computer 1,
Time-sequence control module B includes：Ethernet interface circuit 2, timing control FPGA3, memory 4.
Interconnecting module C includes：Level shifting circuit 5, digital signal output circuit 6, external trigger input circuit 7；
Radio frequency synthesis module A includes：Radio frequency synthesizes FPGA8, direct digital synthesiser 9, digital analog converter 10, variable gain
Amplifier 11, power amplifier 12, wave filter 13.
Wherein：
1st, host computer
Host computer 1 includes ordinary PC, Windows operating system, LabView softwares.Host computer 1 passes through Ethernet interface
Circuit 2 is connected with the timing control FPGA2 of time-sequence control module.
Host computer 1 instructs the radiofrequency signal parameter and number that set needed for experiment using LabView softwares by host computer
Signal parameter, and the host computer of characterization radiofrequency signal parameter and digital signal parameters is instructed the machine for switching to timing control FPGA2
Device instructs.In addition, machine instruction is also transferred to time-sequence control module FPGA2 by host computer 1 by ethernet interface circuit 2.
2nd, time-sequence control module
Time-sequence control module includes ethernet interface circuit 2, timing control FPGA3 and memory 4.Memory 4 and Ethernet connect
Mouth circuit 2 is all connected with timing control FPGA3；Ethernet interface circuit 2 is connected with host computer 1, timing control FPGA3 also with electricity
Flat conversion circuit 5 is connected.
2.1st, ethernet interface circuit 2
Ethernet interface circuit 2 is realized and the network communication of host computer 1, is realized using Ethernet chip DP83843.
2.2nd, timing control FPGA3
Timing control FPGA3 is the control core of whole system, and timing control FPGA3 sends for receiving host computer 1
Machine instruction and be stored in memory 4, then perform these machine instructions successively, and then pass sequentially through 5 sum number of level shifting circuit
Word signal output apparatus 6 generate digital signal and the frequency values of radiofrequency signal, the amplitude of radiofrequency signal, radiofrequency signal just
Beginning phase value issues the radio frequency synthesis FPGA8 of radio frequency synthesis module.Altera companies can be used in timing control FPGA3
Cyclone EP1C12, the chip have 12000 logic units, can realize complicated circuit function.
The firmware of timing control FPGA3 is realized by VHDL hardware description languages.Corresponding machine instruction includes：Wait instruction
Wait, for setting the duration of the duration of radiofrequency signal and digital signal；Waveform frequency instructs frequency, uses
In the frequency values of setting radiofrequency signal；Waveforms amplitude instructs dac, for setting the amplitude of radiofrequency signal；Waveform initial phase refers to
Phase is made, for the initial phase value of radiofrequency signal；Numeral output instructs do, for setting the low and high level of digital signal letter
Number.
2.3rd, memory 4
Memory 4 to store machine instruction, using CYC7C1386B sram chips realize, the chip capacity for 512K ×
36, it can store compared with multiple instructions.
3rd, interconnecting module
Interconnecting module includes level shifting circuit 5, digital signal output circuit 6 and external trigger input circuit 7.Level turns
Circuit 5 is changed respectively with digital signal output circuit 6 and external trigger input circuit 7 to be connected, level shifting circuit 5 also respectively with
Timing control FPGA3, radio frequency synthesis FPGA8 are connected, and digital signal output circuit 6 is then connected with the AOM15 of physical system.
Interconnecting module realizes the connection of time-sequence control module and multiple radio frequency synthesis modules.By way of addressing, one
Time-sequence control module can at most control 16 radio frequency synthesis modules.
3.1st, level shifting circuit 5
Level shifting circuit 5 realizes that the former is digital signal by chip DS90LV047A and DS90LV048A（CMOS/TTL
Signal）Be converted to low-voltage differential signal（LVDS, Low-Voltage Differential Signaling）, the latter is then difference
Sub-signal is converted to digital signal.Time-sequence control module, radio frequency synthesis module and interconnecting module all individually in one piece of circuit
It is realized on plate, in each inter-board communications using LVDS signals, can effectively exclude noise jamming.
3.2nd, digital signal output circuit 6
Digital signal output circuit 6 is realized that digital signal output circuit 6 leads to timing control FPGA3 by row's needle connector
Over level conversion circuit 5 is transmitted through the digital data transmission come to physical system.
3.3rd, external trigger input circuit 7
External trigger input circuit 7 is also realized that external trigger input circuit 7 leads to outer triggering signal by row's needle connector
Over level conversion circuit 5 is input to timing control FPGA3, and it is synchronous with external event to realize that instruction is performed.
4th, radio frequency synthesis module.
Each radio frequency synthesis module includes radio frequency synthesis FPGA8, direct digital synthesiser 9, digital analog converter 10, variable
Gain amplifier 11, power amplifier 12, wave filter 13.Radio frequency synthesizes the control port phase of FPGA8 and direct digital synthesiser 9
Even, radio frequency synthesizes input ports of the FPGA8 also with digital analog converter 10 and is connected, the radio frequency output port of direct digital synthesiser 9
Be connected with the input port of variable gain amplifier 11, the output port of digital analog converter 10 then with variable gain amplifier 11
Control port is connected, and the output port of variable gain amplifier 11 is connected with the input port of power amplifier 12, power amplification
The output port of device 12 is connected with the input port of low-pass filter 13, output port and the physical system phase of low-pass filter 13
Even.
4.1st, radio frequency synthesis FPGA8
Radio frequency synthesis FPGA8 receives radiofrequency signal parameter and digital signal parameters that time-sequence control module 3 is sent, radio frequency
Signal parameter includes the frequency values of radiofrequency signal, the amplitude of radiofrequency signal, the initial phase value of radiofrequency signal and radiofrequency signal
Duration.
If reception is the frequency values of radiofrequency signal, radio frequency synthesis FPGA8 sets direct digital synthesiser 9 so that directly counting
Word synthesizer 9 exports the radiofrequency signal of respective frequencies；
If receiving the initial phase value for the radiofrequency signal for being radiofrequency signal, radio frequency synthesis FPGA8 sets Direct Digital to close
9 are grown up to be a useful person so that the radiofrequency signal of the corresponding initial phase value of the output of direct digital synthesiser 9；
If what is received is the amplitude of radiofrequency signal, radio frequency synthesizes FPGA8 and according to the amplitude of radiofrequency signal digital-to-analogue is controlled to turn
The output of parallel operation 10, and then control the gain of variable gain amplifier 11；
The Cyclone EP2C5T144C6 of Altera companies can be used in radio frequency synthesis FPGA8, which possesses 4608
Logic unit can meet the system requirement.The firmware of radio frequency synthesis FPGA is also developed with hardware description language to be realized, firmware function
Including setting radio frequency signal frequency, setting radiofrequency signal phase, setting radio frequency signal amplitude etc..
4.2nd, direct digital synthesiser 9
Direct digital synthesiser 9 realizes the generation of RF radio frequency signal.To generate the height met needed for quantum information experiment
Frequency（Up to 400MHz）And the radiofrequency signal that frequency, phase and amplitude can switch in real time, solution of the invention are, choosing
With the AD9910 chips of ANALOG DEVICES companies, the sample clock frequency of the DDS chips is up to 1GSPS, highest 400MHZ
Simulation output, built-in 14 DAC can easily the frequency to radiofrequency signal, phase and amplitude be controlled.
4.3rd, digital analog converter 10
The digital signal for being transmitted through coming from radio frequency synthesis FPGA8 is converted to analog signal by digital analog converter 10, simulation letter
Number so for controlling the gain of variable gain amplifier 11.Digital analog converter uses the AD9744 of ANALOG DEVICES companies
Chip is realized.
4.4th, variable gain amplifier 11
Variable gain amplifier 11 is to realize that the amplitude of larger range of radiofrequency signal controls, using ANALOG
The AD8367 chips of DEVICES companies are realized.
4.5th, power amplifier 12
Power amplifier 12 is realized to increase the output power of radiofrequency signal using ERA-3SM+ chips.
4.6th, wave filter 13
Wave filter 13 realizes the filtering to radiofrequency signal, is realized using SALF-325 chips.
Specific example described herein is only to spirit explanation for example of the invention.The technical field of the invention
Technical staff described specific example can be made it is various modification, supplement or substitute in a similar way, but
Without departing from spirit of the invention or beyond the scope of the appended claims.
Claims (3)
1. the timing control signal production method of cold ion quantum information processor, comprises the following steps：
Step 1, on host computer, pass through host computer instruction set quantum information test needed for radiofrequency signal parameter, radiofrequency signal
Parameter includes the frequency values of radiofrequency signal, the amplitude of radiofrequency signal, the initial phase value of radiofrequency signal and continuing for radiofrequency signal
Time；The low and high level signal and digital signal that quantum information is set to test required digital signal parameters are instructed by host computer
Duration,
Host computer instruction includes：Wait instruction wait, for set the duration of radiofrequency signal and digital signal it is lasting when
Between；Waveform frequency instructs frequency, for setting the frequency values of radiofrequency signal；Waveforms amplitude instructs dac, is penetrated for setting
The amplitude of frequency signal；Waveform initial phase instructs phase, for the initial phase value of radiofrequency signal；Numeral output instructs do, uses
In setting digital signal low and high level signal,
Step 2, on host computer, by Labview softwares will characterize step 1 in each radiofrequency signal and digital signal parameters
Host computer instruction map be corresponding timing control FPGA (3) machine instruction, and machine instruction is passed through into Ethernet interface
Circuit (2) is transferred to timing control FPGA (3),
After step 3, timing control FPGA (3) receive machine instruction, memory (4) is first stored in, then takes out and performs one by one,
If the corresponding waveform frequency for radiofrequency signal of machine instruction instructs frequency, timing control FPGA (3) to pass through electricity
The frequency values of radiofrequency signal are transferred to radio frequency synthesis FPGA (8) by flat conversion circuit (5), and radio frequency synthesis FPGA (8), which is received, to be penetrated
Direct digital synthesiser (9) is set after the frequency values of frequency signal so that direct digital synthesiser (9) output respective frequencies value is penetrated
Frequency signal, the radiofrequency signal of direct digital synthesiser (9) output pass sequentially through variable gain amplifier (11), power amplifier
(12) exported afterwards with wave filter (13)；
If machine instruction is corresponding to instruct dac for waveforms amplitude, timing control FPGA (3) will by level shifting circuit (5)
The amplitude of radiofrequency signal is transferred to radio frequency synthesis FPGA (8), and radio frequency synthesis FPGA (8) controls digital-to-analogue according to the amplitude of radiofrequency signal
The output of converter (10), and then pass through the gain of digital analog converter (10) control variable gain amplifier (11)；
For waveform initial phase phase, timing control FPGA (3) is instructed to pass through level shifting circuit if machine instruction is corresponding
(5) initial phase value of radiofrequency signal is transferred to radio frequency synthesis FPGA (8), radio frequency synthesis FPGA (8) receives radiofrequency signal
Initial phase value after direct digital synthesiser (9) is set so that direct digital synthesiser (9) output corresponding initial phase value
Radiofrequency signal, the radiofrequency signal of direct digital synthesiser (9) output pass sequentially through variable gain amplifier (11), power amplifier
(12) exported afterwards with wave filter (13)；
If machine instruction it is corresponding wait instruction wait, timing control FPGA (3) maintained within the stand-by period radiofrequency signal with
The frequency values of current radio frequency signal, the amplitude of radiofrequency signal, the initial phase value of radiofrequency signal carry out continuing output；Timing control
FPGA (3) maintains digital signal persistently to be exported with current low and high level signal within the stand-by period,
If machine instruction is corresponding for the numeral output needed for experiment is set to instruct do, timing control FPGA (3) is according to number
The low and high level signal of signal by level shifting circuit (5) output digit signals,
The digital signal of step 4, the radiofrequency signal of wave filter (13) output and digital signal output circuit (6) output is loaded into sound
On optical modulator (15), acousto-optic modulator (15) is next to being transmitted through from laser (14) according to the radiofrequency signal and digital signal of input
Laser be modulated, the power of the amplitude of radiofrequency signal control laser, the phase of the phase controlling laser of radiofrequency signal, radio frequency
The frequency of signal then carries out shift frequency operation to laser；Digital signal then controls the break-make of laser, is adjusted by acousto-optic modulator (15)
Laser light incident after system into ion trap (16) with cold ionic interaction.
2. the timing control signal generation device of cold ion quantum information processor, including host computer (1), which is characterized in that also
Including time-sequence control module (B), radio frequency synthesis module (A) and modular converter (C),
Time-sequence control module (B) includes ethernet interface circuit (2), timing control FPGA (3) and memory (4),
Modular converter (C) includes level shifting circuit (5), digital signal output circuit (6) and external trigger input circuit (7),
Radio frequency synthesis module (A) includes radio frequency synthesis FPGA (8), direct digital synthesiser (9), digital analog converter (10), variable
Gain amplifier (11), power amplifier (12) and wave filter (13),
Host computer (1) is connected by ethernet interface circuit (2) with timing control FPGA (3), timing control FPGA (3) and memory
(4) connect；Timing control FPGA (3) is connected with level shifting circuit (5), and level shifting circuit (5) synthesizes respectively with radio frequency
FPGA (8), digital signal output circuit (6), external trigger input circuit (7) connection, radio frequency synthesis FPGA (8) respectively with directly
Digital synthesizer (9) and digital analog converter (10) connection, variable gain amplifier (11) respectively with direct digital synthesiser (9),
Digital analog converter (10) and power amplifier (12) connection, power amplifier (12) are connected with wave filter (13).
3. the timing control signal generation device of cold ion quantum information processor according to claim 2, feature exist
In described radio frequency synthesis module (A) number is 2 or 2 or more.
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| CN114565099B (en) * | 2022-02-28 | 2022-11-08 | 中国科学技术大学 | Method for generating superconducting quantum gate line based on FPGA |
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