CN105279037B - Watch dog monitoring method and system - Google Patents
Watch dog monitoring method and system Download PDFInfo
- Publication number
- CN105279037B CN105279037B CN201410306845.3A CN201410306845A CN105279037B CN 105279037 B CN105279037 B CN 105279037B CN 201410306845 A CN201410306845 A CN 201410306845A CN 105279037 B CN105279037 B CN 105279037B
- Authority
- CN
- China
- Prior art keywords
- cpu
- fpga
- errorlevel
- thread
- state value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
The invention discloses a kind of watch dog monitoring methods.The described method includes: FPGA and CPU power-up initializing；The FPGA is sent to watchdog chip feeds dog pulse signal, and the CPU runs the corresponding thread of task；The FPGA and the CPU are communicated, and the status information of other side is read, and whether abnormal judge operation, if so, control other side resets；The FPGA saves the status information of the CPU in real time.The present invention further correspondingly discloses a kind of watch dog monitoring system.Using technical solution of the present invention, it can be obtained by FPGA during monitoring and save CPU state information, in cpu reset, for user's orientation problem.
Description
Technical field
The present invention relates to electronic technology fields, more particularly to a kind of watch dog monitoring method and system.
Background technique
In computer systems, since the work of CPU usually will receive the interference from external electromagnetic field, program is caused to run
Flying, and falls into endless loop, the normal operation of program is interrupted, and system is caused to fall into dead state, unpredictable consequence occurs,
So a kind of chip dedicated for monitoring operating status is produced for the considerations of monitoring in real time to CPU operating status,
It is commonly called as " house dog " (watchdog) chip.
Traditional watch dog monitoring mode realizes CPU by feeding dog in real time using the watchdog chip outside CPU control sheet
The monitoring of software operating condition.Since software control is easy to be influenced by system environments, itself is also by the system of software itself
About, it is easy to lead to cpu system failure in some conditions, in cpu system failure, CPU does not record self information, so as to cause
User can not know the reason of system exception, also can not orientation problem after cpu reset is restarted.And it is traditional based on hardware
Mode monitoring watchdog, reset mode are fixed, not flexible.
Summary of the invention
Based on this, it is necessary to provide a kind of watch dog monitoring method and system, can be obtained during monitoring by FPGA
CPU state information is taken and saves, in cpu reset, for user's orientation problem.
A kind of watch dog monitoring method, comprising:
FPGA and CPU power-up initializing；
The FPGA is sent to watchdog chip feeds dog pulse signal, and the CPU runs the corresponding thread of task；
The FPGA and the CPU are communicated, and the status information of other side is read, and judge whether operation is abnormal, if so,
Control other side resets；
The FPGA saves the status information of the CPU in real time.
In one embodiment, the FPGA and the CPU are communicated, and read the status information of other side, judge to run
Whether Yi Chang step, comprising:
After the corresponding thread of CPU operation task, start the monitoring to the thread, and by the institute in preset time period
The state value for stating thread is sent to the FPGA, and the FPGA judges the CPU according to the corresponding errorlevel of the state value
Whether it is operating abnormally.
In one embodiment, the preset time period is 1ms to 32s.
In one embodiment, the corresponding errorlevel of the state value includes responding slow, accidental crc error, continuing
Crc error and communication disruption；It is described when the corresponding errorlevel of the state value is to continue crc error or communication disruption
FPGA determines the CPU to be operating abnormally state.
In one embodiment, the method also includes:
The CPU reads the status information of the CPU saved, initialization from the FPGA after abnormality is resetted
Continue crc error or the corresponding thread of communication disruption errorlevel state value, and continues to run other errorlevel state values pair
The thread answered, and generate CPU running log.
A kind of watch dog monitoring system, comprising: FPGA, CPU and watchdog chip；
The FPGA feeds dog pulse signal for sending after power-up initializing to the watchdog chip；
The CPU, for after power-up initializing, running the corresponding thread of task；
The FPGA and CPU, is also used to be communicated, and reads the status information of other side, judges whether operation is abnormal,
If so, control other side resets；
The FPGA is also used to save the status information of the CPU in real time.
In one embodiment, after the CPU is used to run the corresponding thread of task, start the monitoring to the thread,
And the state value of the thread in preset time period is sent to the FPGA；
The FPGA is used to judge whether the CPU is operating abnormally according to the corresponding errorlevel of the state value.
In one embodiment, the preset time period is 1ms to 32s.
In one embodiment, the corresponding errorlevel of the state value includes responding slow, accidental crc error, continuing
Crc error and communication disruption；
The FPGA, for determining when the corresponding errorlevel of the state value is to continue crc error or communication disruption
The CPU is operation exception state.
In one embodiment, the CPU is used for after abnormality is resetted, and reads preservation from the FPGA
The status information of CPU initializes and continues crc error or the corresponding thread of communication disruption errorlevel state value, and continues to run
The corresponding thread of other errorlevel state values, and generate CPU running log.
Above-mentioned watch dog monitoring method and system, FPGA and CPU are communicated, and the status information of other side is read, and judge to transport
Whether row is abnormal, if abnormal, control other side and resets, and FPGA can save the status information of CPU in real time, compared to
Traditional technology, realizing can be obtained by FPGA during monitoring and save CPU state information, in cpu reset,
For user's orientation problem.
Detailed description of the invention
Fig. 1 is the flow diagram of the watch dog monitoring method in one embodiment；
Fig. 2 is the structural schematic diagram of the watch dog monitoring system in one embodiment；
Fig. 3 is the attachment structure schematic diagram of the FPGA and watchdog chip in one embodiment；
Fig. 4 is the structural schematic diagram of the storing data of cpu monitor thread in one embodiment；
Fig. 5 is the storage organization schematic diagram of the status information for the CPU that FPGA is obtained in one embodiment.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
Referring to Fig. 1, in one embodiment, a kind of watch dog monitoring method is provided.This method comprises:
Step 101, FPGA and CPU power-up initializing.
Step 102, FPGA is sent to watchdog chip feeds dog pulse signal, and CPU runs the corresponding thread of task.
Specifically, after FPGA power-up initializing dog pulse signal can be fed to the lasting transmission of watchdog chip.CPU root
Task, such as the display etc. of read-write DDR, LCD are executed according to execution program or externally input instruction is powered on, it is every to execute one
Business, CPU can run corresponding thread.
Step 103, FPGA and CPU are communicated, and read the status information of other side, judge whether operation is abnormal, if so,
Control other side resets.
Specifically, FPGA and CPU mutually monitor the operating status of other side.Wherein, FPGA is from progress logical process, meeting
Logic state is recorded, CPU judges whether FPGA work is abnormal, controls FPGA if abnormal and is answered according to the logic state of record
Position.Related treatment process is similar with the principle that CPU controls other peripheral hardwares, and details are not described herein.
It further include that FPGA is monitored CPU in this step.After CPU runs the corresponding thread of task, start to thread
Monitoring, and the state value of the thread in preset time period is sent to FPGA, by FPGA according to corresponding mistake of the state value etc.
Grade judges whether CPU is operating abnormally.Wherein, preset time period can be configured by CPU, according to status information storage depth meeting
Different, range is 1ms to 32s.The errorlevel of state value carries out the school CRC to the relevant data communication of thread by CPU
It tests to obtain, multiple grades can be divided into advance, such as respond slow, accidental crc error, continue crc error and communication disruption.Work as shape
The corresponding errorlevel of state value is when continuing crc error or communication disruption, and FPGA determines CPU to be operating abnormally state.
Step 104, FPGA saves the status information of CPU in real time.
Specifically, FPGA saves the status information of CPU in real time, the operation shape that CPU can be analyzed so that user of service is subsequent
State.
Further, in the present embodiment, when FPGA determines that CPU is operating abnormally, by sending a reset level to CPU
After allowing it to reset, the CPU state information that CPU is saved from FPGA readback initializes and continues crc error or communication disruption mistake etc.
The corresponding thread of grade state value, and the thread of the state value to other errorlevels, reading the state value before resetting continues to run,
Improve reset speed.Also, CPU running log can be generated in CPU, for user of service's analysis.
Referring to fig. 2, in one embodiment, a kind of watchdog chip monitoring system is provided.The system include: FPGA,
CPU and watchdog chip.
FPGA feeds dog pulse signal for sending after power-up initializing to watchdog chip.
CPU, for after power-up initializing, running the corresponding thread of task.
FPGA and CPU is also used to be communicated, and reads the status information of other side, judges whether operation is abnormal, if so,
Control other side resets.
FPGA is also used to save the status information of CPU in real time.
In one embodiment, referring to Fig. 3, it is DOG_FEED respectively that FPGA watchdog circuit, which has three control pins altogether,
RESET_CTR and SYSTEM_RESET.DOG_FEED signal is that FPGA feeds dog pulse, and precision can achieve ns grades, normal
During feeding dog, FPGA continuously sends out fixed pulse to refresh watchdog chip.RESET_CTR signal is that watchdog reset is effectively believed
Number, reset switch is realized by this signal of logic control.SYSTEM_RESET signal connects FPGA active loading reset signal, control
Whether FPGA processed resets.
In one embodiment, referring to fig. 4, after CPU runs the corresponding thread of task, start the monitoring to thread (by Fig. 4
1) middle valid data bit is set to by 0, and the state value of the thread in preset time period is sent to FPGA, the preset time period
Range can be configured by CPU from 1ms to 32s.In Fig. 4, the data such as Thread1, Thread2 are each line of CPU configuration
The numerical value of the monitoring preset time period of journey.
In one embodiment, FPGA and CPU are communicated, and the status information for obtaining CPU is as shown in Figure 5.Data bit 15
It is valid, sets 1, identifies thread just in the monitoring state.Data bit 14init data bit marks the corresponding peripheral hardware of thread complete
At initialization.For data bit 13 to 0 misregistration grade of data bit, errorlevel includes: to respond slowly (0x10), accidental CRC mistake
Accidentally (0x20), lasting crc error (0x30) and communication disruption (0x40).FPGA is lasting in the corresponding errorlevel of state value
When crc error or communication disruption, CPU is determined to be operating abnormally state.FPGA can send reset level and draw to the reset of CPU at this time
Foot allows it to be resetted.
In one embodiment, CPU reads the status information of the CPU saved from FPGA after abnormality is resetted,
It initializes and continues crc error or the corresponding thread of communication disruption errorlevel state value, and continue to run other errorlevel shapes
The corresponding thread of state value, and CPU running log is generated, so that user of service analyzes.
Above-mentioned watch dog monitoring method and system, FPGA and CPU are communicated, and the status information of other side is read, and judge to transport
Whether row is abnormal, if abnormal, control other side and resets, and FPGA can save the status information of CPU in real time, compared to
Traditional technology, realizing can be obtained by FPGA during monitoring and save CPU state information, in cpu reset,
For user's orientation problem.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
Limitations on the scope of the patent of the present invention therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Protect range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (8)
1. a kind of watch dog monitoring method, which is characterized in that the described method includes:
FPGA and CPU power-up initializing；
The FPGA is sent to watchdog chip feeds dog pulse signal, and the CPU runs the corresponding thread of task；
The FPGA and the CPU are communicated, and the status information of other side is read, and judge whether operation is abnormal, if so, control
Other side resets；The FPGA and the CPU are communicated, and the status information of other side is read, and judge whether operation is abnormal
Step, including, after the CPU runs the corresponding thread of task, start the monitoring to the thread, and will be in preset time period
The state value of the thread is sent to the FPGA, and the FPGA is according to the corresponding errorlevel judgement of the state value
Whether CPU is operating abnormally；
The FPGA saves the status information of the CPU in real time.
2. the method according to claim 1, wherein the preset time period is 1ms to 32s.
3. the method according to claim 1, wherein the corresponding errorlevel of the state value includes that response is slow
Slowly, accidental crc error, lasting crc error and communication disruption；When the corresponding errorlevel of the state value is to continue crc error
Or when communication disruption, the FPGA determines the CPU to be operating abnormally state.
4. according to the method described in claim 3, it is characterized in that, the method also includes:
The CPU reads the status information of the CPU saved from the FPGA after abnormality is resetted, and initialization continues
Crc error or the corresponding thread of communication disruption errorlevel state value, and it is corresponding to continue to run other errorlevel state values
Thread, and generate CPU running log.
5. a kind of watch dog monitoring system, which is characterized in that the system comprises: FPGA, CPU and watchdog chip；
The FPGA feeds dog pulse signal for sending after power-up initializing to the watchdog chip；
The CPU, for after power-up initializing, running the corresponding thread of task；
The FPGA and CPU, is also used to be communicated, and reads the status information of other side, judges whether operation is abnormal, if
It is then to control other side and reset；After the CPU is used to run the corresponding thread of task, start the monitoring to the thread, and
The state value of the thread in preset time period is sent to the FPGA；
The FPGA is used to judge whether the CPU is operating abnormally according to the corresponding errorlevel of the state value；
The FPGA is also used to save the status information of the CPU in real time.
6. system according to claim 5, which is characterized in that the preset time period is 1ms to 32s.
7. system according to claim 5, which is characterized in that the corresponding errorlevel of the state value includes that response is slow
Slowly, accidental crc error, lasting crc error and communication disruption；
The FPGA is used for when the corresponding errorlevel of the state value is to continue crc error or communication disruption, described in judgement
CPU is operation exception state.
8. system according to claim 7, which is characterized in that the CPU is used for after abnormality is resetted, from institute
The status information that FPGA reads the CPU saved is stated, lasting crc error is initialized or communication disruption errorlevel state value is corresponding
Thread, and the corresponding thread of other errorlevel state values is continued to run, and generate CPU running log.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410306845.3A CN105279037B (en) | 2014-06-30 | 2014-06-30 | Watch dog monitoring method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410306845.3A CN105279037B (en) | 2014-06-30 | 2014-06-30 | Watch dog monitoring method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105279037A CN105279037A (en) | 2016-01-27 |
| CN105279037B true CN105279037B (en) | 2019-01-11 |
Family
ID=55148087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410306845.3A Active CN105279037B (en) | 2014-06-30 | 2014-06-30 | Watch dog monitoring method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105279037B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105929811B (en) * | 2016-04-06 | 2018-11-20 | 清华大学 | A kind of protection circuit for program deadlock |
| CN107025160A (en) * | 2017-04-14 | 2017-08-08 | 济南浪潮高新科技投资发展有限公司 | A kind of system of quick positioning question for Shen prestige processor platform |
| CN109062718B (en) * | 2018-07-12 | 2021-08-17 | 联想(北京)有限公司 | Server and data processing method |
| CN109726080B (en) * | 2018-12-29 | 2023-07-14 | 百度在线网络技术（北京）有限公司 | Method and device for monitoring working state of heterogeneous computing system |
| CN109815044A (en) * | 2019-03-29 | 2019-05-28 | 深圳市广联智通科技有限公司 | A kind of cascade watchdog circuit |
| CN110287055B (en) * | 2019-06-28 | 2021-06-15 | 联想(北京)有限公司 | Data recovery method of electronic equipment and electronic equipment |
| CN118377644A (en) * | 2024-06-21 | 2024-07-23 | 南京国电南自维美德自动化有限公司 | FPGA-based rapid CPU fault diagnosis lifting method and system |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060236150A1 (en) * | 2005-04-01 | 2006-10-19 | Dot Hill Systems Corporation | Timer-based apparatus and method for fault-tolerant booting of a storage controller |
| CN1908856A (en) * | 2005-08-05 | 2007-02-07 | 中兴通讯股份有限公司 | Position restoration circuit device |
| CN101271415A (en) * | 2008-05-07 | 2008-09-24 | 深圳国人通信有限公司 | Monitoring watchdog implementing method of built-in equipment |
| CN101964731A (en) * | 2010-06-18 | 2011-02-02 | 中兴通讯股份有限公司 | Method and device for monitoring data link |
| CN102081573A (en) * | 2010-02-01 | 2011-06-01 | 杭州华三通信技术有限公司 | Device and method for recording equipment restart reason |
| CN102141939A (en) * | 2010-02-01 | 2011-08-03 | 杭州华三通信技术有限公司 | Device capable of recording restart reason of whole machine |
| CN203386143U (en) * | 2013-07-24 | 2014-01-08 | 三维通信股份有限公司 | Remote machine reset device |
-
2014
- 2014-06-30 CN CN201410306845.3A patent/CN105279037B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060236150A1 (en) * | 2005-04-01 | 2006-10-19 | Dot Hill Systems Corporation | Timer-based apparatus and method for fault-tolerant booting of a storage controller |
| CN1908856A (en) * | 2005-08-05 | 2007-02-07 | 中兴通讯股份有限公司 | Position restoration circuit device |
| CN101271415A (en) * | 2008-05-07 | 2008-09-24 | 深圳国人通信有限公司 | Monitoring watchdog implementing method of built-in equipment |
| CN102081573A (en) * | 2010-02-01 | 2011-06-01 | 杭州华三通信技术有限公司 | Device and method for recording equipment restart reason |
| CN102141939A (en) * | 2010-02-01 | 2011-08-03 | 杭州华三通信技术有限公司 | Device capable of recording restart reason of whole machine |
| CN101964731A (en) * | 2010-06-18 | 2011-02-02 | 中兴通讯股份有限公司 | Method and device for monitoring data link |
| CN203386143U (en) * | 2013-07-24 | 2014-01-08 | 三维通信股份有限公司 | Remote machine reset device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105279037A (en) | 2016-01-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105279037B (en) | Watch dog monitoring method and system | |
| EP3427151B1 (en) | Memory backup management in computing systems | |
| US11210172B2 (en) | System and method for information handling system boot status and error data capture and analysis | |
| CN102081573B (en) | Device and method for recording equipment restart reason | |
| WO2017125014A1 (en) | Method and device for monitoring hard disk | |
| CN106201755B (en) | The repositioning method and device of the network equipment | |
| CN108549591A (en) | A kind of black box device and its implementation of embedded system | |
| US20140068350A1 (en) | Self-checking system and method using same | |
| US10013319B2 (en) | Distributed baseboard management controller for multiple devices on server boards | |
| CN105912481B (en) | Method for calculating power loss for processing device with non-volatile logic memory | |
| CN106557391A (en) | Display screen processing method and processing device | |
| US9135193B2 (en) | Expander interrupt processing | |
| US9275527B2 (en) | Controller | |
| CN111913669B (en) | SSD power-down speed improving method and device, computer equipment and storage medium | |
| US20170160778A1 (en) | Method and device for monitoring power-consuming applications, user terminal, computer program and storage medium | |
| CN112199642B (en) | Detection method for anti-debugging of android system, mobile terminal and storage medium | |
| CN116225812B (en) | Baseboard management controller system operation method, device, equipment and storage medium | |
| KR20210147340A (en) | Server and sensing device in system for logistics management | |
| CN113900875B (en) | Startup test method and device, computer equipment and storage medium | |
| CN116974804A (en) | Debugging method, device, equipment and storage medium for managing engine suspension | |
| CN111796872A (en) | Control method, robot, control apparatus, system, and medium | |
| CN109634796A (en) | A kind of method for diagnosing faults of computer, apparatus and system | |
| TWI461905B (en) | Computing device capable of remote crash recovery, method for remote crash recovery of computing device, and computer readable medium | |
| US20180276066A1 (en) | Disk device and notification method of the disk device | |
| CN110781517A (en) | Method for realizing data interaction by BIOS and BMC communication |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 516025 No. 1, Shunchang Road, Huinan Industrial Park, Zhongkai high tech Zone, Huizhou City, Guangdong Province Patentee after: WELLAV TECHNOLOGIES Ltd. Address before: 516006 Huitai Industrial Zone 63, Zhongkai High-tech Zone, Huizhou City, Guangdong Province Patentee before: HUIZHOU WELLAV TECHNOLOGIES Co.,Ltd. |
|
| CP03 | Change of name, title or address |