CN105278865B - Data managing method, memorizer control circuit unit and memory storage apparatus - Google Patents

Abstract

A kind of data managing method of present invention offer, memorizer control circuit unit and memory storage apparatus comprising：It is data bit area and redundancy ratio special zone by each physical procedures dividing elements；According to the first data management information of the first write instruction the first data corresponding with the generation of the first data；Judge whether the first data are compressible；And generate the first data compression information of corresponding first data.This data managing method further includes：If the first data are compressible, the first data are compressed to generate the first compressed data, by the first data bit area of the first compressed data and the first physical procedures unit among the first data management information sequencing to those physical procedures units of corresponding first data, and by the first redundancy ratio special zone of the first data compression information sequencing to the first physical procedures unit.

Description

Data managing method, memorizer control circuit unit and memory storage apparatus

Technical field

The invention relates to a kind of data managing method, memorizer control circuit unit and memory storage apparatus.

Background technology

Digital camera, mobile phone and MP3 are very rapid in growth over the years so that demand of the consumer to storage medium Also rapidly increase.Since rewritable non-volatile memory (rewritable non-volatile memory) has data Non-volatile, power saving, it is small, without the characteristics such as mechanical structure, read or write speed be fast, be most suitable for portable electronic product, such as pen Remember this computer.Solid state disk is exactly a kind of storage device using flash memory as storage media.Therefore, flash in recent years Device industry becomes a ring quite popular in electronic industry.

Support compression function (that is, the data that host system is stored in the control circuit of flash memory storage Be written again after being compressed to the function of fast-flash memory body memory) example in, if by the data of this corresponding compressed data Management information is also stored together into the redundancy ratio special zone for the physical procedures unit for storing this compressed data, can to store this The space in the redundancy ratio special zone of the physical procedures unit of compressed data is reduced, and the sky that can store error checking and correcting code is caused Between reduce, thus sacrifice error correction capability.Therefore, how the relevant information for capableing of compressed data is effectively managed, thus Field technology personnel project of interest.

Invention content

A kind of data managing method of present invention offer, memorizer control circuit unit and memory storage apparatus, energy The enough information for effectively managing compressed data, to increase the utilization ratio of storage space.

One example of the present invention embodiment provides a kind of data management for rewritable non-volatile memory module Method, wherein this rewritable non-volatile memory module are comprising multiple physical erase units and multiple logic units are to reflect Those least a portion of physical erase units are incident upon, and each physical erase unit has multiple physical procedures units.Above-mentioned number Include according to management method：It is data bit area and redundancy ratio special zone by each physical procedures dividing elements；Receive the first write-in First data of instruction and corresponding first write instruction, and according to the first write instruction and the first data generation corresponding first First data management information of data.Above-mentioned data managing method further includes：Judge whether the first data are compressible, and according to Judging result generates the first data compression information of corresponding first data.Above-mentioned data managing method further includes：If the first number When according to being compressible, the first data of compression are to generate the first compressed data, by the of the first compressed data and corresponding first data First data ratio of the first physical procedures unit among one data management information sequencing to those physical procedures units Special zone, and by the first redundancy ratio special zone of the first data compression information sequencing to the first physical procedures unit；And if If the first data are incompressible, by the first data bit area of the first Data programming to the first physical procedures unit, By the first redundant bit of the first data compression information and the first data management information sequencing to the first physical procedures unit Area.

In one example of the present invention embodiment, above-mentioned first write instruction instruction stores the first data to the first logic Subelement, and above-mentioned the first data management information according to the first write instruction the first data corresponding with the generation of the first data Step includes：First data error check caused by corresponding first data is integrated into the first data management information with correcting code In, and the address of the first logical subunit for recording corresponding to the first data is integrated into the first data management information.

In one example of the present invention embodiment, the step of above-mentioned generation corresponds to the first data compression information of the first data Including：The integrated instruction whether compressed information of the first data into the first data compression information, and if the first data be When compressible, the compression ratios of corresponding first data is integrated into the first data compression information.

In one example of the present invention embodiment, above-mentioned data managing method includes：If the first data are compressible, Compressing the first data becomes First Transition data, and judges the size of First Transition data.Above-mentioned data managing method also wraps It includes, if the size of First Transition data is less than or equal to the first default reduction length, First Transition data addition first is filled out Complement so that the size of the first compressed data is equal to the first default reduction length, and first is pressed according to the first compressed data is become Contracting data are divided into the first error checking and correcting code frame with the first data management information, wherein the first error checking and correcting code The size of frame is equal to the first error checking and correcting code frame length.Above-mentioned data managing method further includes, if First Transition number According to size be more than the first default reduction length and be less than the second default reduction length, the addition of First Transition data second is filled up Data become the first compressed data, so that the size of the first compressed data is equal to the second default reduction length, and first are compressed Data are divided into the first error checking and correcting code frame with the first data management information, wherein the first error checking and correcting code frame Size be equal to the second error checking and correcting code frame length.Above-mentioned data managing method further includes, if First Transition data Size be more than the second default reduction length and less than third preset reduction length, by First Transition data addition third fill up several According to as the first compressed data, so that the size of the first compressed data is equal to third and presets reduction length, and number is compressed by first It is divided into the first error checking and correcting code frame according to the first data management information, wherein the first error checking and correcting code frame Size is equal to third error checking and correcting code frame length.Above-mentioned data managing method further includes, if First Transition data Size is more than third and presets reduction length and be less than the 4th default reduction length, and data are filled up in First Transition data addition the 4th As the first compressed data, so that the size of the first compressed data is equal to the 4th default reduction length, and by the first compressed data It is divided into the first error checking and correcting code frame with the first data management information, wherein the first error checking and correcting code frame is big It is small to be equal to the 4th error checking and correcting code frame length.Above-mentioned data managing method further includes, by the first error checking and correction Code frame sequencing is to the first data bit area.

In one example of the present invention embodiment, the size of the first logical subunit is big with the first physical procedures unit Small is transmission unit size, and wherein transmission unit size is 4096 bytes.In addition, the first error checking and correcting code frame length Size is a quarter of the size of the first physical procedures unit, the size of the second error checking and correcting code frame length is the The size of the half of the size of one physical procedures unit, third error checking and correcting code frame length is the first physics journey 3/4ths and the 4th error checking of the size of sequence unit is the first physical procedures with the size of correcting code frame length The size of unit.

In one example of the present invention embodiment, above-mentioned data managing method further includes：Integrated corresponding First Transition data First fill up data, second fill up data, third fills up data or the 4th fills up the address of data and the information of size into In one data management information.

One example of the present invention embodiment provides a kind of for rewritable non-volatile memory module data manager Method, wherein rewritable non-volatile memory module are comprising multiple physical erase units and multiple logic units are to map to Those least a portion of physical erase units, and each physical erase unit has multiple physical procedures units.Above-mentioned data pipe Reason method includes：Each physical procedures unit is at least divided into data bit area and redundancy ratio special zone.Above-mentioned data management Method includes：Receive compressible first data；It is the first compressed data by the first data compression, and generates corresponding first data The first data compression information, wherein indicating a compression of first data whether compressed information and corresponding first data Rate is integrated into first data compression information.Above-mentioned data managing method also includes：By those physical procedures units it In the first data bit zoning of the first physical procedures unit be divided into the first user data field and the first management information area, And by the first compressed data sequencing to the first user data field.Above-mentioned data managing method further includes：First will be corresponded to In first data management information sequencing to the first management information area of data, and extremely by the first data compression information sequencing First redundancy ratio special zone of the first physical procedures unit.

In one example of the present invention embodiment, above-mentioned data managing method further includes：Receive incompressible second number According to, and by the data bit of the second physical procedures unit among the second Data programming to those physical procedures units Area.Above-mentioned data managing method further includes：By the second data management information and the second data compression information of corresponding second data Sequencing is to the redundancy ratio special zone of the second physical procedures unit, wherein indicating that the second data are the information quilt of incompressible data It is integrated into second data compression information.

The present invention provides a kind of memorizer control circuit unit, for controlling rewritable non-volatile memory module. This memorizer control circuit unit includes：Host interface, memory interface, memory management circuitry contract with data compression/decompression Circuit.Host interface is electrically connected to host system.It is non-volatile that memory interface is electrically connected to duplicative Memory module, wherein rewritable non-volatile memory module include multiple physical erase units, multiple logic units with Those at least part of physical erase units are mapped, and each physical erase unit has multiple physical procedures units.Storage Device management circuit is electrically connected to host interface and memory interface, and it is at least part of to map to configure multiple logic units Those physical erase units.Data compression/decompression contracting circuit is electrically connected memory management circuitry, and to press data Contracting or decompression operation.Memory management circuitry to by each physical procedures dividing elements be data bit area and redundancy ratio Special zone.Memory management circuitry also to receive the first data of the first write instruction and corresponding first write instruction, and According to the first data management information of the first write instruction the first data corresponding with the generation of the first data.And above-mentioned memory Circuit is managed also to judge whether the first data are compressible, and generates the first number of corresponding first data according to judging result According to compression information.If the first data are compressible, memory management circuitry is also to designation date compression/decompression circuit The first data are compressed to generate the first compressed data, and memory management circuitry is also assigning instruction sequence to duplicative Non-volatile memory module was extremely should the first compressed data with the first data management information sequencing of corresponding first data First data bit area of the first physical procedures unit among a little physical procedures units, and the first data compression is believed Sequencing is ceased to the first redundancy ratio special zone of the first physical procedures unit.If the first data are incompressible, memory Management circuit is also assigning instruction sequence to rewritable non-volatile memory module with by the first Data programming to the First data bit area of one physical procedures unit, and by the first data compression information and the first data management information program Change to the first redundancy ratio special zone of the first physical procedures unit.

In one example of the present invention embodiment, the instruction of the first write instruction stores the first data single to the first logic Member, and in the fortune of above-mentioned the first data management information according to the first write instruction the first data corresponding with the generation of the first data In work, the first data error check caused by corresponding first data is integrated into the first number by memory management circuitry with correcting code According in management information, and the address of the first logical subunit corresponding to the first data is integrated into the first data management information In.

In one example of the present invention embodiment, the fortune of the first data compression information of the first data is corresponded in above-mentioned generation Work includes：The integrated instruction whether compressed information of the first data of memory management circuitry is into the first data compression information.With And if the first data are when being compressible, memory management circuitry is also to the compression ratio of integrated corresponding first data into the first number According in compression information.

In one example of the present invention embodiment, if the first data are compressible, data compression/decompression contracting circuit pressure First data that contract become First Transition data, and memory management circuitry is also judging the size of First Transition data.If If the size of First Transition data is less than or equal to the first default reduction length, memory management circuitry is also to by First Transition Data, which are added first, which fills up data, becomes the first compressed data, so that the size of the first compressed data is equal to the first default compression length Degree, and the first compressed data and the first data management information are divided into the first error checking and correcting code frame, wherein first is wrong Flase drop is looked into is equal to one first error checking and correcting code frame length with the size of correcting code frame.And if First Transition data Size be more than the first default reduction length and be less than the second default reduction length, memory management circuitry is also to by the first mistake It crosses data addition second and fills up data as the first compressed data, so that the size of the first compressed data is equal to the second default compression Length, and the first compressed data and the first data management information are divided into the first error checking and correcting code frame, wherein first Error checking and the size of correcting code frame are equal to one second error checking and correcting code frame length.And if First Transition number According to size be more than the second default reduction length and preset reduction length less than third, memory management circuitry is also to by first Third, which is added, in transit data, which fills up data, becomes the first compressed data, so that the size of the first compressed data is equal to the default pressure of third Contracting length, and the first compressed data and the first data management information are divided into the first error checking and correcting code frame, wherein the One error checking and the size of correcting code frame are equal to third error checking and correcting code frame length.And if First Transition number According to size be more than third and preset reduction length and be less than the 4th default reduction length, memory management circuitry is also to by first Transit data, which is added the 4th, which fills up data, becomes the first compressed data, so that the size of the first compressed data is equal to the 4th default pressure Contracting length, and the first compressed data and the first data management information are divided into the first error checking and correcting code frame, wherein the One error checking and the size of correcting code frame are equal to the 4th error checking and correcting code frame length.Furthermore memory management circuitry Also assigning instruction sequence to rewritable non-volatile memory module with by the first error checking and correcting code frame program Change to the first data bit area.

In one example of the present invention embodiment, the size of above-mentioned first logical subunit and the first physical procedures unit Size be transmission unit size, wherein transmission unit size be 4096 bytes.Also, the first error checking and correcting code frame are long The size of degree is a quarter, the size of the second error checking and correcting code frame length of the size of the first physical procedures unit It is the first object for the half of the size of the first physical procedures unit, third error checking and the size of correcting code frame length The size of the 3/4ths and the 4th error checking for managing the size of programmed cell and correcting code frame length is the first physics journey The size of sequence unit.

In one example of the present invention embodiment, memory management circuitry is also to the of integrated corresponding First Transition data One fill up data, second fill up data, third fills up data or the 4th fills up the address of data and the information of size into the first number According in management information.

One example of the present invention embodiment provides a kind of storage for controlling rewritable non-volatile memory module Device control circuit unit.Memorizer control circuit unit includes：Host interface, memory interface, memory management circuitry and number According to compression/decompression circuit.Host interface is electrically connected to host system.Memory interface is electrically connected to answer Formula non-volatile memory module is write, wherein rewritable non-volatile memory module includes multiple physical erase units, more A logic unit is to map those at least part of physical erase units, and each physical erase unit has multiple physical procedures Change unit.Memory management circuitry is electrically connected to host interface and memory interface, and configures multiple logic units to reflect It is incident upon those least a portion of physical erase units.Data compression/decompression contracting circuit electric connection memory management circuitry, and to Compression or decompression operation, wherein memory management circuitry are carried out at least dividing each physical procedures unit to data For data bit area and redundancy ratio special zone, wherein memory management circuitry is to receive the first data, wherein the first data are can Compressed data, and the first data compression is the first compressed data by designation date compression/decompression circuit.In addition, memory The first data compression information that circuit generates corresponding first data is managed, wherein indicating the whether compressed information of first data It is integrated into first data compression information with a compression ratio of corresponding first data.Furthermore memory management circuitry is also Make the first data bit zoning of the first physical procedures unit among those physical procedures units is divided into first User data field and the first management information area, and instruction sequence is assigned to rewritable non-volatile memory module with by the One compressed data sequencing to the first user data field, by the first data management information sequencing of corresponding first data to the In one management information area, and by the first data compression information sequencing to the first redundant bit of the first physical procedures unit Area.

In one example of the present invention embodiment, upper memory management circuitry is also to receive the second data, wherein second Data are incompressible data.In addition, memory management circuitry is assigning instruction sequence to duplicative non-volatile holographic storage Device module is with by the data ratio of the second physical procedures unit among the second Data programming to those physical procedures units Special zone, and the second data management information and the second data compression information sequencing to the second physics journey that the second data will be corresponded to The redundancy ratio special zone of sequence unit, wherein indicating that the second data are that the information of incompressible data is integrated into the second data pressure In contracting information.

One example of the present invention embodiment provides a kind of memory storage apparatus comprising：Connecting interface unit can be made carbon copies Formula non-volatile memory module and memorizer control circuit unit.Connecting interface unit is electrically connected to a host system System.Rewritable non-volatile memory module has multiple physical erase units and multiple logic units are to map at least portion Those physical erase units divided, wherein each physical erase unit has multiple physical procedures units.Memory control electricity Road unit is electrically connected to connecting interface unit and rewritable non-volatile memory module, and configures multiple logic units To map those at least part of physical erase units.Memorizer control circuit unit to by each physical procedures unit draw It is divided into data bit area and redundancy ratio special zone.In addition, memorizer control circuit unit also to receive the first write instruction and First data of corresponding first write instruction, and according to the of the first write instruction the first data corresponding with the generation of the first data One data management information.Furthermore memorizer control circuit unit is also to judge whether the first data are compressible, and according to sentencing Disconnected result generates the first data compression information of corresponding first data.If the first data are compressible, memory control electricity Road unit is also compressing the first data to generate the first compressed data, by the first compressed data and the first of corresponding first data First data bit of the first physical procedures unit among data management information sequencing to those physical procedures units Area, and by the first redundancy ratio special zone of the first data compression information sequencing to the first physical procedures unit.And if When first data are incompressible, memorizer control circuit unit is also to by the first Data programming to the first physical procedures First data bit area of unit, and by the first data compression information and the first data management information sequencing to the first physics First redundancy ratio special zone of programmed cell.

In one example of the present invention embodiment, the instruction of the first write instruction stores the first data single to the first logic Member, and in the fortune of above-mentioned the first data management information according to the first write instruction the first data corresponding with the generation of the first data In work, memorizer control circuit unit integrates will correspond to the first data error check caused by the first data with correcting code Into in the first data management information.In addition, memorizer control circuit unit is also to by the first logic corresponding to the first data The address of subelement is integrated into the first data management information.

In one example of the present invention embodiment, above-mentioned generation corresponds to the running of the first data compression information of the first data Including：Memorizer control circuit unit is also to the integrated whether compressed information of first data into the first data compression information In.If the first data are compressible, memorizer control circuit unit is also to the compression ratio of integrated corresponding first data into the In one data compression information.

In one example of the present invention embodiment, if the first data are compressible, memorizer control circuit unit pressure First data that contract become First Transition data, and wherein memorizer control circuit unit is also judging the big of First Transition data It is small.If the size of First Transition data be less than or equal to the first default reduction length, memorizer control circuit unit also to Data are filled up in First Transition data addition first becomes the first compressed data, so that the size of the first compressed data is equal to first Default reduction length, and the first compressed data and the first data management information are divided into the first error checking and correcting code frame, Wherein the first error checking and the size of correcting code frame are equal to the first error checking and correcting code frame length.And if first The size of transit data is more than the first default reduction length and is less than the second default reduction length, and memorizer control circuit unit is also Become the first compressed data data are filled up in First Transition data addition second, so that the size of the first compressed data is equal to Second default reduction length, and the first compressed data and the first data management information are divided into the first error checking and correcting code Frame, wherein the first error checking and the size of correcting code frame are equal to the second error checking and correcting code frame length.And if the The size of one transit data is more than the second default reduction length and presets reduction length, memorizer control circuit unit less than third Also become the first compressed data First Transition data addition third is filled up data, so that the size etc. of the first compressed data Reduction length is preset in third, and the first compressed data and the first data management information are divided into the first error checking and correction Code frame, wherein the first error checking and the size of correcting code frame are equal to third error checking and correcting code frame length.And if The size of First Transition data is more than third and presets reduction length and be less than the 4th default reduction length, memorizer control circuit list Member also becomes the first compressed data data are filled up in First Transition data addition the 4th, so that the size of the first compressed data It is divided into the first error checking and school equal to the 4th default reduction length, and by the first compressed data and the first data management information Code frame, wherein the first error checking and the size of correcting code frame are equal to the 4th error checking and correcting code frame length.Furthermore it deposits Memory control circuit unit is also to by the first error checking and the sequencing of correcting code frame to the first data bit area.

In one example of the present invention embodiment, the size of the first logical subunit is big with the first physical procedures unit Small is transmission unit size, and wherein transmission unit size is 4096 bytes.Also, the first error checking and correcting code frame length Size is a quarter of the size of the first physical procedures unit, the size of the second error checking and correcting code frame length is the The size of the half of the size of one physical procedures unit, third error checking and correcting code frame length is the first physics journey 3/4ths and the 4th error checking of the size of sequence unit is the first physical procedures with the size of correcting code frame length The size of unit.

In one example of the present invention embodiment, memorizer control circuit unit is also to integrated corresponding First Transition data First fill up data, second fill up data, third fills up data or the 4th fills up the address of data and the information of size into In one data management information.

The present invention provides a kind of memory storage apparatus comprising：Connecting interface unit, duplicative non-volatile holographic storage Device module and memorizer control circuit unit.Connecting interface unit is electrically connected to host system.Duplicative is non-volatile to be deposited Memory modules, wherein rewritable non-volatile memory module have multiple physical erase units, and multiple logic units are to reflect Those least a portion of physical erase units are incident upon, and each physical erase unit has multiple physical procedures units.Memory Control circuit unit is electrically connected to connecting interface unit and rewritable non-volatile memory module, and configures multiple patrol Unit is collected to map those at least part of physical erase units.Memorizer control circuit unit is to by each physical procedures Dividing elements are data bit area and redundancy ratio special zone.In addition, memorizer control circuit unit is also to receive the first data, In the first data be compressible data.In addition, memorizer control circuit unit also to by the first data compression be first compression Data, and the first data compression information of corresponding first data is generated, wherein indicating the whether compressed letter of first data Breath is integrated into a compression ratio of corresponding first data in first data compression information.Furthermore memorizer control circuit Unit is also the first data bit zoning of the first physical procedures unit among those physical procedures units to be divided into First user data field will be right by the first compressed data sequencing to the first user data field with the first management information area In the first data management information sequencing to the first management information area for answering the first data, and by the first data compression information journey Sequence is to the first redundancy ratio special zone of the first physical procedures unit.

In one example of the present invention embodiment, memorizer control circuit unit is also to receive the second data, wherein Two data are incompressible data.In addition, memorizer control circuit unit is to by the second Data programming to those physics journeys The data bit area of the second physical procedures unit among sequence unit, and the second data management that the second data will be corresponded to Information and the second data compression information sequencing are to the redundancy ratio special zone of the second physical procedures unit, wherein indicating the second data It is integrated into second data compression information for the information of incompressible data.

Based on above-mentioned, the present invention can allow the data management information of corresponding compressed data with its corresponding to compression number According to being stored in together in data bit area, the space occupied to redundancy ratio special zone will not be gone to.Thus, can be in a physics When programmed cell stores more compressed datas, the redundancy ratio special zone of physical procedures unit can also be allow to retain sky Between to store other information, and then promote memory storage apparatus space service efficiency and effectively management can compress number According to relevant information.

To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to coordinate attached drawing to make Carefully it is described as follows.

Description of the drawings

Fig. 1 is the schematic diagram of the host system and memory storage apparatus shown by an exemplary embodiment；

Fig. 2 is computer, input/output device and the memory storage apparatus shown by exemplary embodiment of the present invention Schematic diagram；

Fig. 3 is the schematic diagram of the host system and memory storage apparatus shown by exemplary embodiment of the present invention；

Fig. 4 shows the schematic block diagram of memory storage apparatus shown in FIG. 1；

Fig. 5 is the schematic block diagram of the memorizer control circuit unit shown by an exemplary embodiment；

Fig. 6 is the schematic diagram for writing data to physical page shown by exemplary embodiment of the present invention；

Fig. 7 is the example schematic of the management physical blocks shown by exemplary embodiment of the present invention；

Fig. 8 is to be attached to transit data according to will fill up data and data management information shown by exemplary embodiment of the present invention Schematic diagram；

Fig. 9 is with unpacked data according to storage compressed data shown by exemplary embodiment of the present invention in multiple physical procedures Change the schematic diagram of the example of unit；

Figure 10 is with unpacked data according to storage compressed data shown by exemplary embodiment of the present invention in multiple physics journeys The schematic diagram of another example of sequence unit；

Figure 11 is according to the first exemplary embodiment of the invention, shown data managing method flow chart；

Figure 12 A~Figure 12 F are according to storage compressed data shown by exemplary embodiment of the present invention in physical procedures unit Schematic diagram；

Figure 13 is according to storage unpacked data shown by exemplary embodiment of the present invention in the signal of physical procedures unit Figure；

Figure 14 is according to the second exemplary embodiment of the invention, shown data managing method flow chart.

Reference sign：

1000：Host system；

1100：Computer；

1102：Microprocessor；

1104：Random access memory；

1106：Input/output device；

1108：System bus；

1110：Data transmission interface；

1202：Mouse；

1204：Keyboard；

1206：Display；

1208：Printer；

1212：USB flash disk；

1214：Storage card；

1216：Solid state disk；

1310：Digital camera；

1312：SD card；

1314：Mmc card；

1316：MS cards；

1318：CF cards；

1320：Embedded storage device；

100：Memory storage apparatus；

102：Connecting interface unit；

104：Memorizer control circuit unit；

106：Rewritable non-volatile memory module；

202：Memory management circuitry；

204：Host interface；

206：Memory interface；

208：Buffer storage；

210：Electric power management circuit；

212：Error checking and correcting circuit；

214：Data compression/decompression contracting circuit；

410 (0)~410 (N)：Physical erase unit；

502：Data field；

504：Idle area；

506：System area；

508：Replace area；

LBA (0)~LBA (H)：Logic unit；

LZ (0)~LZ (M)：Logic region；

RD1：First data；

TD1：First Transition data；

PD1：First fills up data；

CD1：First compressed data；

CD2：Second compressed data；

CD4：4th compressed data；

CD5：5th compressed data；

D3：Third data；

D6：6th data；

D7：7th data；

ECCF1：First error checking and correcting code frame；

ECCF2：Second error checking and correcting code frame；

ECCF3：Third error checking and correcting code frame；

ECCF4：4th error checking and correcting code frame；

ECCF5：5th error checking and correcting code frame；

ECCF6：6th error checking and correcting code frame；

ECCF7：7th error checking and correcting code frame；

ECCF8：8th error checking and correcting code frame；

ECCF9：9th error checking and correcting code frame；

DBA：Data bit area；

DBA1：First data bit area；

DBA2：Second data bit area；

DBA3：Third data bit area；

DBA4：4th data bit area；

DBA5：5th data bit area；

DMI1：First data management information；

DMI2：Second data management information；

DMI3：Third data management information；

DMI4：4th data management information；

DMI5：5th data management information；

DMI6：6th data management information；

DMI7：7th data management information；

SBA1：First redundancy ratio special zone；

SBA2：Second redundancy ratio special zone；

SBA3：Third redundancy ratio special zone；

SBA4：4th redundancy ratio special zone；

SBA5：5th redundancy ratio special zone；

UDA1：First user data field；

UDA2：Second user data field；

MIA1：First management information area；

MIA2：Second management information area.

Specific implementation mode

[the first exemplary embodiment]

Fig. 1 is the schematic diagram of the host system and memory storage apparatus shown by an exemplary embodiment.

Fig. 1 is please referred to, host system 1000 generally comprises computer 1100 and input/output (Input/Output, abbreviation I/ O) device 1106.Computer 1100 includes microprocessor 1102, random access memory (Random Access Memory, abbreviation RAM) 1104, system bus 1108 and data transmission interface 1110.Input/output device 1106 include as Fig. 2 mouse 1202, Keyboard 1204, display 1206 and printer 1208.It will be appreciated that the unrestricted input/output device of device shown in Fig. 2 1106, input/output device 1106 can further include other devices.

In exemplary embodiment of the present invention, memory storage apparatus 100 is by data transmission interface 1110 and host system The other elements of system 1000 are electrically connected.Pass through microprocessor 1102, random access memory 1104 and input/output device 1106 running can write data into memory storage apparatus 100 or read data from memory storage apparatus 100.Example Such as, memory storage apparatus 100 can be USB flash disk 1212, storage card 1214 or solid state disk (Solid State as shown in Figure 2 Drive, abbreviation SSD) 1216 equal rewritable non-volatile memory modular storage devices.

In general, host system 1000 is that can substantially coordinate with memory storage apparatus 100 to store appointing for data Meaning system.Although in this exemplary embodiment, host system 1000 is explained with computer system, however, of the invention another Host system 1000 can be digital camera, video camera, communication device, audio player or video playing in one exemplary embodiment The systems such as device.For example, when host system 1000 is digital camera (video camera) 1310, rewritable non-volatile memory mould Block storage device then be its used SD card 1312, mmc card 1314, MS cards (memory stick) 1316, CF cards 1318 or Embedded storage device 1320 (as shown in Figure 3).Embedded storage device 1320 includes embedded multi-media card (Embedded MMC, abbreviation eMMC).It is noted that embedded multi-media card is the substrate for being directly electrically connected at host system 1000 On.

Fig. 4 shows the schematic block diagram of memory storage apparatus shown in FIG. 1.

Fig. 4 is please referred to, memory storage apparatus 100 includes connecting interface unit 102, memorizer control circuit unit 104 With rewritable non-volatile memory module 106.

In this exemplary embodiment, connecting interface unit 102 is compatible with the advanced attachment of sequence (Serial Advanced Technology Attachment, abbreviation SATA) standard.However, it is necessary to be appreciated that, the invention is not limited thereto, connecting interface Unit 102 can also be to meet advanced attachment (Parallel Advanced Technology Attachment, abbreviation side by side PATA) standard, Institute of Electrical and Electric Engineers (Institute of Electrical and Electronic Engineers, abbreviation IEEE) 1394 standards, high-speed peripheral component connecting interface (Peripheral Component Interconnect Express, abbreviation PCI Express) standard, universal serial bus (Universal Serial Bus, Abbreviation USB) standard, a ultrahigh speed generation (Ultra High Speed-I, abbreviation UHS-I) interface standard, two generation of ultrahigh speed (Ultra High Speed-II, abbreviation UHS-II) interface standard, the advanced attachment of sequence (Serial Advanced Technology Attachment, abbreviation SATA) standard, MS cards (Memory Stick, abbreviation MS) interface standard, multimedia Storage card (Multi Media Card, abbreviation MMC) interface standard, compact flash (Compact Flash, abbreviation CF) interface mark Accurate, integrated form driving electrical interface (Integrated Device Electronics, abbreviation IDE) standard or other are suitable Standard.In this exemplary embodiment, connecting interface unit 102 can be encapsulated in a chip with memorizer control circuit unit 104 In, or be laid in outside a chip comprising memorizer control circuit unit 104.

Memorizer control circuit unit 104 is executing in the form of hardware or multiple logic gates of form of firmware implementation or control System instruction, and instruction sequence is assigned to rewritable non-volatile memory module 106 according to the instruction of host system 1000 The runnings such as to carry out the write-in of data, read and erase.

Rewritable non-volatile memory module 106 is electrically connected to memorizer control circuit unit 104, and uses The data being written with host system 1000.Rewritable non-volatile memory module 106 has physical erase unit 410 (0)~410 (N).For example, physical erase unit 410 (0)~410 (N) can belong to the same memory crystal grain (die) or Belong to different memory crystal grains.Each physical erase unit is respectively provided with a plurality of physical procedures units, such as the present invention Exemplary embodiment in, each physical erase unit includes 258 physical procedures units, and wherein belongs to the same physics The physical procedures unit of erased cell can be written independently and simultaneously be erased.However, it is necessary to be appreciated that, the present invention It is without being limited thereto, each physical erase unit be can by 64 physical procedures units, 256 physical procedures units or other Meaning physical procedures unit is formed.

In more detail, physical erase unit is the least unit erased.That is, each physical erase unit contains minimum number Mesh and the storage unit being erased.Physical procedures unit is the minimum unit of sequencing.That is, physical procedures unit is write-in The minimum unit of data.Each physical procedures unit generally include data bit area (Data Bits Area, abbreviation DBA) with Redundancy ratio special zone (Spare Bits Area, abbreviation SBA).Data bit area includes multiple physics access addresses to be made to store The data of user, and redundancy ratio special zone to storage system data (for example, control information, compression information or error checking With correcting code).In this exemplary embodiment, the size in the data bit area of each physical procedures unit is 4096 bytes (bytes) and include 4 physics access addresses, and the size of a physics access address is 102 bytes.However, at other Also it may include that the more or fewer physics access addresses of number, the present invention are not intended to limit in exemplary embodiment, in data bit area The size and number of physics access address.For example, in an exemplary embodiment, physical erase unit is physical blocks, and Physical procedures unit is physical page or physical sector, but invention is not limited thereto.

In this exemplary embodiment, rewritable non-volatile memory module 106 is multi-level cell memory (Multi Level Cell, abbreviation MLC) NAND type flash memory module be (that is, can store 2 bit datas in a storage unit Flash memory module, hereinafter referred to as MLC NAND type flash memories module), however, the invention is not limited thereto, duplicative is non- Volatile storage module 106 can also be single-order storage unit (Single Level Cell, abbreviation SLC) NAND type flash memory Memory modules (that is, the flash memory module of 1 bit data can be stored in a storage unit), three rank storage units (Trinary Level Cell, abbreviation TLC) NAND type flash memory module is (that is, can store 3 ratios in a storage unit The flash memory module of special data), other flash memory modules or other memory modules with the same characteristics.

In this exemplary embodiment, the physical erase unit of MLC NAND type flash memory modules has multiple physics journeys Sequence unit, and those physical procedures units further include due to that can store 2 bit datas in a storage unit Lower physical procedures unit (Lower programming unit) and upper physical procedures unit (Higher programming unit).And when generally using MLC NAND type flash memory modules storage data, multilayer can be used simultaneously Location pattem come under sequencing one of one of physical procedures unit and upper physical procedures unit with It writes data into storage unit.

Fig. 5 is the schematic block diagram of the memorizer control circuit unit shown by an exemplary embodiment.

Fig. 5 is please referred to, memorizer control circuit unit 104 includes memory management circuitry 202, host interface 204, storage Device interface 206, buffer storage 208, electric power management circuit 210, error checking and correcting circuit 212 and data compression/decompression Contracting circuit 214.

Memory management circuitry 202 to control memory control circuit unit 104 overall operation.Specifically, it deposits Reservoir, which manages circuit 202, has multiple control instructions, and when memory storage apparatus 100 operates, those control instruction meetings It is performed the runnings such as to carry out the write-in of data, read and erase.

In this exemplary embodiment, the control instruction of memory management circuitry 202 is to carry out implementation with form of firmware.For example, Memory management circuitry 202 has microprocessor unit (not shown) and read-only memory (not shown), and those controls refer to Order is programmed in so far read-only memory.When memory storage apparatus 100 operates, those control instructions can be by microprocessor Unit is executed the runnings such as to carry out the write-in of data, read and erase.

In another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also procedure code form The specific region of rewritable non-volatile memory module 106 is stored in (for example, being exclusively used in storage system in memory module The system area 506 of data) in.In addition, memory management circuitry 202 has microprocessor unit (not shown), read-only memory (not shown) and random access memory (not shown).In particular, this read-only memory has driving code, and work as memory control When circuit unit 104 processed is enabled, microprocessor unit can first carry out this driving code section, and will to be stored in duplicative non-volatile Control instruction in property memory module 106 is loaded into the random access memory of memory management circuitry 202.Later, micro- Processor unit such as can operate those control instructions to carry out the write-in of data, read and erase at the runnings.

In addition, in another exemplary embodiment of the present invention, the control instruction of memory management circuitry 202 can also a hardware Form carrys out implementation.For example, memory management circuitry 202 includes microcontroller, Storage Unit Management circuit, memory write-in electricity Road, memory reading circuitry, memory are erased circuit and data processing circuit.Storage Unit Management circuit, memory write-in electricity Circuit is erased on road, memory reading circuitry, memory and data processing circuit is electrically connected to microcontroller.Wherein, it stores Single Component Management circuit is managing the physical erase unit of rewritable non-volatile memory module 106；Memory write-in electricity Road is non-volatile to duplicative to write data into assign write instruction to rewritable non-volatile memory module 106 In property memory module 106；Memory reading circuitry refers to assign reading to rewritable non-volatile memory module 106 It enables to read data from rewritable non-volatile memory module 106；Memory erases circuit to non-to duplicative Volatile storage module 106 assigns instruction of erasing so that data to be erased from rewritable non-volatile memory module 106； And data processing circuit is intended to be written data to rewritable non-volatile memory module 106 and from can make carbon copies to handle The data read in formula non-volatile memory module 106.

Host interface 204 is electrically connected to memory management circuitry 202 and to receive and identify host system 1000 instructions transmitted and data.That is, the instruction that host system 1000 is transmitted can pass through host interface with data 204 are sent to memory management circuitry 202.In this exemplary embodiment, host interface 204 is compatible with SATA standard.So And, it should be understood that the invention is not limited thereto, and host interface 204 can also be to be compatible with PATA standards, the marks of IEEE 1394 Standard, PCI Express standards, USB standard, UHS-I interface standards, UHS-II interface standards, MS standards, MMC standards, CF mark Accurate, IDE standards or other suitable data transmission standards.

Memory interface 206 is electrically connected to memory management circuitry 202 and non-volatile to access duplicative Property memory module 106.That is, the data for being intended to be written to rewritable non-volatile memory module 106 can be via depositing Memory interface 206 is converted to the 106 receptible format of institute of rewritable non-volatile memory module.

In an exemplary embodiment of the invention, memorizer control circuit unit 104 further includes buffer storage 208, power supply Manage circuit 210 and error checking and correcting circuit 212.

Buffer storage 208 is electrically connected to memory management circuitry 202 and is configured to temporarily store come from host system 1000 data and the data for instructing or coming from rewritable non-volatile memory module 106.

Electric power management circuit 210 is electrically connected to memory management circuitry 202 and stores to control memory fill Set 100 power supply.

Error checking is electrically connected to memory management circuitry 202 and to execute wrong inspection with correcting circuit 212 It looks into correction program to ensure the correctness of data.Specifically, it is connect from host system 1000 when memory management circuitry 202 When receiving write instruction, error checking generates corresponding mistake with the data that correcting circuit 212 can be this corresponding write instruction and examines Look into correcting code (Error Checking and Correcting Code, abbreviation ECC Code), and memory management electricity The data of this corresponding write instruction can be written with correcting code to duplicative is non-volatile with corresponding error checking and be deposited by road 202 In memory modules 106.Later, when memory management circuitry 202 number is read from rewritable non-volatile memory module 106 According to when can read the corresponding error checking of this data and correcting code simultaneously, and error checking can be according to this with correcting circuit 212 Error checking executes error checking and correction program with correcting code to read data.

Data compression/decompression contracting circuit 214 is electrically connected to memory management circuitry 202.Here, data compression/solution Compressor circuit 214 is intended to be written data to rewritable non-volatile memory module 106 and to decompress to compress The read data from rewritable non-volatile memory module 106.For example, data compression/decompression contracting circuit 214 includes Compressor reducer (compressor) and decompressor (decompressor).Compressor reducer is finding out initial data (original Data data redundancy present in) (data redundancy) removes found out redundancy, and remaining necessary data is encoded And exports coding result, that is, compressed data (compressed data).And decompressor is to the compressed data that will read in It is decoded according to set step and sends out decoding result, that is, decompression data (decompressed data).In this example reality It applies in example, data compression/decompression contracting circuit 214 is to carry out compressed data using Lossless Compression algorithm, so that compressed data It can be reduced.

Fig. 6 and Fig. 7 is the example schematic of the management physical erase unit shown by an exemplary embodiment.

Fig. 6 is please referred to, memorizer control circuit unit 104 (or memory management circuitry 202) can be by physical erase unit 410 (0)~410 (N) are logically grouped into data field 502, idle area 504, system area 506 and substitution area 508.

It is to store to come from host system to logically belong to data field 502 and the physical erase unit in idle area 504 1000 data.Specifically, the physical erase unit of data field 502 is regarded as having stored the physical erase unit of data, And the physical erase unit in area 504 of leaving unused is to the physical erase unit in replacement data area 502.That is, working as from host When system 1000 receives write instruction with the data to be written, the meeting of memory management circuitry 202 extract from idle area 504 Erased cell is managed, and is write data into the physical erase unit extracted, is erased list with the physics in replacement data area 502 Member.

The physical erase unit for logically belonging to system area 506 is to record system data.For example, system data includes Manufacturer about rewritable non-volatile memory module 106 and model, rewritable non-volatile memory module 106 Physical erase unit number, each physical erase unit physical procedures unit number etc..

It is to replace program for bad physical erase unit to logically belong to the physical erase unit in substitution area 508, to take The physical erase unit of generation damage.Specifically, if still having normal physical erase unit and data in substitution area 508 When the physical erase unit damage in area 502, memory management circuitry 202 can extract normal physics from substitution area 508 and erase Unit replaces the physical erase unit of damage.

In particular, the quantity meeting of data field 502, idle area 504, system area 506 and the physical erase unit in substitution area 508 It is different according to different memory specifications.Further, it is necessary to be appreciated that, in the running of memory storage apparatus 100, The grouping relationship that physical erase unit is associated with to data field 502, idle area 504, system area 506 and substitution area 508 can be dynamically It changes.For example, when the physical erase unit damage in idle area 504 is substituted the physical erase unit substitution in area 508, then The physical erase unit in the area 508 of substitution originally can be associated to idle area 504.

Fig. 7 is please referred to, memorizer control circuit unit 104 (or memory management circuitry 202) can configuration logic unit LBA (0)~LBA (H) to map the physical erase unit of data field 502, wherein each logic unit have multiple logical subunits with Map the physical procedures unit of corresponding physical erase unit.Also, work as 1000 logic list to be write data to of host system Member or when updating storage the data in logic unit, memorizer control circuit unit 104 (or memory management circuitry 202) meeting A physical erase unit is extracted from idle area 504 data are written, with the physical erase unit of alternation data field 502. In this exemplary embodiment, logical subunit can be logical page (LPAGE) or logic sector.In this exemplary embodiment, logical subunit For logical page (LPAGE), size is 4 kilobytes (kilobytes, K bytes), identical as the size of physical procedures unit.

In order to identify that the data of each logic unit are stored in that physical erase unit, in this exemplary embodiment, Memorizer control circuit unit 104 (or memory management circuitry 202) can record between logic unit and physical erase unit Mapping.Also, when host system 1000 is intended to access data in logical subunit, memorizer control circuit unit 104 (or deposit Reservoir manages circuit 202) it can confirm logic unit belonging to this logical subunit, and to rewritable non-volatile memory Module 106 assigns corresponding instruction sequence to access data in this logic unit mapped physical erase unit.For example, In this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) can be non-volatile in duplicative Property memory module 106 in storage logic turn physical address mapping table and erase list to record each logic unit mapped physics Member, and when data to be accessed, logic can be turned physics by memorizer control circuit unit 104 (or memory management circuitry 202) Address mapping table is loaded into buffer storage 208 to safeguard.

Reflecting for all logic units is recorded it is noted that can not be stored since the capacity of buffer storage 208 is limited The mapping table of relationship is penetrated, therefore, in this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) logic unit LBA (0)~LBA (H) can be grouped into multiple logic region LZ (0)~LZ (M), and be each logic area One logic of configuration of territory turns physical address mapping table.In particular, when memorizer control circuit unit 104 (or memory management electricity Road 202) when being intended to update the mapping of some logic unit, the logic of the logic region belonging to this corresponding logic unit turns physical address Mapping table can be loaded on buffer storage 208 to be updated.

As described above, in this exemplary embodiment, the rewritable non-volatile memory mould of memory storage apparatus 100 Block 106 is managed based on physical procedures unit, therefore, when executing write instruction, no matter current data are It is written to the logical subunit of that logic unit, memorizer control circuit unit 104 (or memory management circuitry 202) is all Data can be written in such a way that a physical procedures unit connects a physical procedures unit.Specifically, memory Control circuit unit 104 (or memory management circuitry 202) can extract an empty physical erase unit from idle area 504 and make Data are written for physical erase unit used at present.Also, when this physical erase unit used at present has been fully written, Memorizer control circuit unit 104 (or memory management circuitry 202) can extract another empty physics from idle area 504 again Erased cell is as physical erase unit used at present, to continue to write to the corresponding write instruction for coming from host system 1000 Data.

In this exemplary embodiment, as described above, the error checking in memory storage apparatus 100 and correcting circuit 212 Whether correct it can be configured to the data stored in verification rewritable non-volatile memory module 106.However, executing When error-correcting routine, either coding or decoding step, error checking and correcting circuit 212 are wanted it will be clear that knowing Why is the data length of protection, so can just calculate correct condition code, to check correct errors present.In this example In embodiment, when memorizer control circuit unit 104 (or memory management circuitry 202) receives data, memory control Data first can be divided at least one yard of frame (Frame) by circuit unit 104 (or memory management circuitry 202), later mistake It checks with correcting circuit 212 again respectively to the corresponding error checking of the data generation of each yard of frame and correcting code (Error Checking and Correcting Code, abbreviation ECC).Then, (or the memory management of memorizer control circuit unit 104 Circuit 202) data of each yard of frame and corresponding error checking can be divided into an error checking and correction with correcting code Code frame, and data are written as unit of error checking and correcting code frame to rewritable non-volatile memory module 106.Here, the size of error checking and correcting code frame is to be divided according to the size of unit of transfer, and this unit of transfer is big Small determined according to the specifications of rewritable non-volatile memory module 106.That is, each unit of transfer must protect Protect (protect) how many a bits (bit).For example, unit of transfer is 4 kilobytes, 24 bits are protected.When error checking and school When code frame is set as 4 kilobytes, memorizer control circuit unit 104 (or memory management circuitry 202) can cut data It is the code frame less than 4 kilobytes for per unit.And the data that error checking can then be directed to each code frame with correcting circuit 212 carry out Error correction encodes, so that the error checking generated and the size summation of correcting code and each code frame are 4 kilobytes.

But it will be appreciated that the invention is not limited thereto, in another exemplary embodiment, error checking and correcting code frame Size can also be 1 kilobytes, 2 kilobytes or 3 kilobytes etc..It is noted that each physical procedures unit is big It is small to store at least one error checking and correcting code frame, so as to the data of physical procedures unit are stored in, with error checking Size with correcting code frame is unit, can be by the protection of error checking and correcting circuit 212.

For example, in this exemplary embodiment, the maximum protection ability of error checking and correcting circuit 212 is 24 bits, Therefore when the error bits numbers that error checking and correcting code frame are occurred are more than 24 (for example, 25), error checking and correction electricity Road 212 will be unable to correct in the wrong data in error checking and correcting code frame, cause to be stored in this error checking and correcting code The data of frame cannot normally be read, and become irreclaimable damage data.When this situation occurs, also representing has this damage number According to physical erase unit excessively aging and can't bear to use.Therefore memorizer control circuit unit 104 (or memory management Circuit 202) physical procedures unit of the meeting by error bits numbers more than error checking and 212 maximum protection ability of correcting circuit It is marked as bad physics programmed cell, and is recorded in a bad physics programmed cell distribution table.

Fig. 8 is to be attached to transit data according to will fill up data and data management information shown by exemplary embodiment of the present invention Schematic diagram.

Please refer to Fig. 8, for example, in this exemplary embodiment, when (or the memory of memorizer control circuit unit 104 Management circuit 202) be intended to by data length be 4 kilobytes the first data RD1 be written to physical procedures unit when, data pressure Contracting/decompression circuit 214 can scan the first data RD1 and test whether the first data RD1 can be compressed.If the first data When RD1 can be compressed, data compression/decompression contracting circuit 214 can obtain first after scanning and testing the first data RD1 The data aspect (pattern) of data RD1, then data compression/decompression contracting circuit 214, which can use, is suitble to the first data RD1 The compression method of data aspect and compression ratio carry out squeeze operation to export First Transition data (First to the first data RD1 Transition Data)TD1.It is noted that in this exemplary embodiment, before to the first data RD1 compressions, deposit Memory control circuit unit 104 (or memory management circuitry 202) can indicate error checking with correcting circuit 212 to the first data RD1 generates the first error checking and the correcting code of corresponding first data RD1, and the first error checking and correcting code are stored to right In the first data management information (the Data Management Information) DMI1 for answering the first data RD1.In addition, into When row squeeze operation, data compression/decompression contracting circuit 214 can carry out compressed data using Lossless Compression algorithm, to be allowed to Data after decompressing afterwards can be completely restored to.It will be appreciated that the invention is not limited thereto compression algorithm.Compressing the first data After RD1, memorizer control circuit unit 104 (or memory management circuitry 202) can will carry out compression behaviour to the first data RD1 Compress mode and compression ratio etc. relevant information used in making is recorded in the first data RD1 compression information, wherein this One data RD1 compressions information can also record whether the first data RD1 has compressed information.

However, the length of different write-in data generated compressed datas after overcompression may be different.For side Just the management of data, data compression/decompression contracting circuit 214 can export generated compressed data to preset reduction length. That is the length of generated compressed data is equal to default reduction length.It is noted that in this exemplary embodiment In, compressed data can be corresponded to using different default reduction lengths.

Specifically, it is assumed that when the first compressed length of data RD1 is between 1~1016 byte, data compression/ Decompression circuit 214 can fill up data (Padding Data, abbreviation PD) to be attached to generated First Transition number with one After TD1, as shown in Figure 8 first fills up data PD1, to generate the first compressed data CD1, wherein the first compression number It is equal to the first default reduction length (that is, 1016 bytes) according to the length of CD1.When the first compressed length of data RD1 between When between 1017~2040 bytes, data compression/decompression contracting circuit 214 with one can fill up data come caused by being attached to the After one transit data TD1, to generate the first compressed data CD1, preset wherein the length of the first compressed data CD1 is equal to second Reduction length (that is, 2040 bytes).When the first compressed length of data RD1 is between 2041~3064 bytes, data Compression/decompression circuit 214 with one can fill up data come after First Transition data TD1 caused by being attached to, to generate First compressed data CD1, wherein the length of the first compressed data CD1, which is equal to third, presets reduction length (that is, 3064 bytes).When When the first compressed length of data RD1 is between 3065~4088 bytes, data compression/decompression contracting circuit 214 can be with one Pen fills up data come after First Transition data TD1 caused by being attached to, to generate the first compressed data CD1, wherein first The length of compressed data CD1 is equal to the 4th default reduction length (that is, 4088 bytes).

Then, first data of correspondence can be added in memorizer control circuit unit 104 (or memory management circuitry 202) The data management information (hereinafter referred to as the first data management information DMI1) of RD1, after the first compressed data CD1.For example, first The size of data management information DMI1 is 8 bytes.Then, memorizer control circuit unit 104 (or memory management circuitry 202) First compressed data CD1 and the first data management information DMI1 can be integrated into the first error checking and correcting code frame ECCF1.

In this exemplary embodiment, the size of above-mentioned first error checking and correcting code frame ECCF1 are compressed according to first Depending on data CD1.For example, if the size of the first compressed data CD1 is the first default reduction length (that is, 1016 bytes) When, then the size of generated first error checking and correcting code frame ECCF1 are the first error checking and correcting code frame length Size, that is, 1024 bytes.If the size of the first compressed data CD1 is second default reduction length (that is, 2040 bytes), The size of first error checking and correcting code frame ECCF1 caused by then are big for the second error checking and correcting code frame length It is small, that is, 2048 bytes.If the size of the first compressed data CD1 presets reduction length (that is, 3064 bytes) for third, The size of generated first error checking and correcting code frame ECCF1 are the size of third error checking and correcting code frame length, Namely 3072 bytes.If the size of the first compressed data CD1 is the 4th default reduction length (that is, 4088 bytes), institute The size of the first error checking generated and correcting code frame ECCF1 are the size of the 4th error checking and correcting code frame length, It is exactly 4096 bytes.It is noted that the size setting of above-mentioned default reduction length and error-correcting code frame length is only For purposes of discussion, it is not used in the limitation present invention.

Please refer to Fig. 8, for example, when memorizer control circuit unit 104 (or memory management circuitry 202) is intended to count When being written to the first physical procedures unit extracted by the first data RD1 of 4 kilobytes according to length, data compression/decompression Contracting circuit 214 can be determined compress or how be compressed according to the data aspect of the first data RD1, and in the first number of compression Before RD1, the first error checking and correcting code first are generated to the first data RD1, then store the first error checking and correction Code is in the first data management information DMI1 of corresponding first data RD1.Then, data compression/decompression contracting circuit 214 can be by the One data RD1 is collapsed into First Transition data TD1, and size is 2000 bytes.Then, since 2000 bytes are between 1017 Between~2040 bytes, produced so data compression/decompression contracting circuit 214 can fill up data PD1 with one first to be attached to After raw First Transition data TD1, with the first pressure that one length of output is the second default reduction length (that is, 2040 bytes) Contracting data CD1.

Then, first data of correspondence can be added in memorizer control circuit unit 104 (or memory management circuitry 202) The first data management information DMI1 of RD1, after the first compressed data CD1, size is 8 kilobytes.Base this, first compression Data CD1 and the first data management information DMI1 can form the first error checking and correcting code frame ECCF1.Due to the first compression number Length according to CD1 is the second default reduction length (that is, 2040 bytes), and therefore, the first error checking is with correcting code frame ECCF1's Length is 2048 bytes.

In addition, in this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) is also deposited The information for storing up the compress mode about First Transition data TD1 (is not shown in the first compression information of the first redundancy ratio special zone SBA1 Go out) in.Also, when reading First Transition data TD1, memorizer control circuit unit 104 (or memory management circuitry 202) According to the first compression information the compression side of corresponding First Transition data TD1 can be used come designation date compression/decompression circuit 214 Formula decompresses First Transition data TD1.In the above example, the bit value of the first each bit for filling up data PD1 is " 1 ", however, the present invention is not limited thereto.That is, filling up the set that data can be fixed bit value.

It is noted that although in this exemplary embodiment, first, which fills up data PD1, is appended in First Transition number After TD1, however, it is necessary to be appreciated that, the invention is not limited thereto, and first, which fills up data PD1, can also be placed in First Transition number According to before TD1 or being inserted among First Transition data TD1.In addition, first to fill up data PD1 can be virtual data (Dummy Data) or the virtual data of the error checking code with corresponding first data RD1, wherein this error checking code can be corresponding the The cyclic redundancy check code or odd-even check code of one data RD1, the invention is not limited thereto.It can be with that is, filling up data It is any data aspect (pattern), but the purpose for filling up data is predominantly additional to compressed data, makes the length of compressed data Degree is default reduction length.

In particular, when needing to fill up data PD1 with first to be attached to First Transition data TD1 to generate the first compression number When according to CD1, data compression/decompression contracting circuit 214 can store the filling information about the first data RD1 in the first data RD1 pressures In contracting information, included to record this first compressed data CD1 first fills up the size of data PD1.In addition, corresponding first The position that the filling information of data RD1 also can fill up data PD1 included in the first compressed data CD1 first, in order to solve First Transition data TD1 is restored when pressure.For example, filling information can be recorded in rewritable non-volatile memory module 106 In in the physical blocks of memory system data, storage in the mapping table or be stored in corresponding this first data RD1's In first data RD1 compression information, wherein the first data RD1 compressions information can be stored in the first physics of the first data RD1 again In the first redundancy ratio special zone (First Spare Bits Area, abbreviation SBA1) of programmed cell or correspond to the first data In the first data management information DMI1 of RD1.

It is noted that in another exemplary embodiment, memorizer control circuit unit 104 (or memory management electricity Road 202) error checking and correcting circuit 212 can be indicated to the first error checking and correcting code frame ECCF1 to generate corresponding first First error-detecting code of error checking and correcting code frame ECCF1, and the first error checking and correcting code frame ECCF1 are stored Into the first data bit area DBA1 (referring to Fig. 9) of the first physical procedures unit.Meanwhile memorizer control circuit unit 104 (or memory management circuitries 202) examine the first mistake of the first error checking of generated correspondence and correcting code frame ECCF1 It surveys code to be stored in the first redundancy ratio special zone SBA1 of the first physical procedures unit, wherein this first error-detecting code can be pair The cyclic redundancy check code or odd-even check code of the first error checking and correcting code frame ECCF1 are answered, the invention is not limited thereto.When Memorizer control circuit unit 104 (or memory management circuitry 202) First Transition data TD1 to be decompressed becomes the first data Before RD1, memorizer control circuit unit 104 (or memory management circuitry 202) may further indicate that error checking and correcting circuit 212, it is examined with the first mistake of correcting code frame ECCF1 using the first error checking of correspondence of the first redundancy ratio special zone SBA1 is stored in Code is surveyed to check the first error checking and correcting code frame ECCF1.If do not detect mistake, memorizer control circuit unit 104 (or memory management circuitries 202) are according to the first data RD1 compression information and are stored in the first data management information DMI1 Information come decompress and decode First Transition data TD1 become the first data RD1.

In this exemplary embodiment, memorizer control circuit unit 104 (or memory management circuitry 202) meeting will be produced The first error checking and correcting code frame ECCF1 be written into the first data bit area DBA1 of the first physical procedures unit. In another exemplary embodiment, error checking can also be produced with correcting circuit 212 according to the first error checking and correcting code frame ECCF1 Raw corresponding first error-detecting code, and memorizer control circuit unit 104 (or memory management circuitry 202) can will be produced The first raw error-detecting code is stored to the first physical procedures list of corresponding storage the first error checking and correcting code frame ECCF1 In first redundancy ratio special zone SBA1 of member.

Later, when memorizer control circuit unit 104 (or memory management circuitry 202) is intended to from physical procedures unit When reading data with response to host system 1000, memory management circuitry 202 and data compression/decompression contracting circuit 214 are necessary Carry out restoring data with reverse program.

Fig. 9 is with unpacked data according to storage compressed data shown by exemplary embodiment of the present invention in multiple physical procedures Change the schematic diagram of the example of unit.

Please refer to Fig. 9, for example, the first physical procedures unit is divided into the first data bit area DBA1 and first Redundancy ratio special zone SBA1, and the second physical procedures unit is divided into the second data bit area DBA2 and the second redundant bit Area SBA2.First data RD1 is compressible data, and is had been compressed into as the first compressed data CD1, wherein the first compressed data The size of CD1 is 2040 bytes.Second data RD2 is compressible data, and is had been compressed into as the second compressed data CD2, In the second compressed data CD2 size be 2040 bytes.Third data D3 is incompressible data, and size is 4096 bytes. There are two error checking and correcting code frame, one is first for the first data bit area DBA1 storages of first physical procedures unit Error checking and correcting code frame ECCF1, the other is the second error checking and correcting code frame ECCF2, size is respectively second wrong Flase drop is looked into and correcting code frame ECCF2 length (that is, 2048 bytes).First error checking includes the first pressure with correcting code frame ECCF1 Contracting data CD1 and the first data management information DMI1, and the second error checking and correcting code frame ECCF2 include the second compression number According to CD2 and the second data management information DMI2.As can be seen from Fig. 9, with relevant first data management informations of the first data RD1 DMI1 and with the relevant second data management information DMI2 of the second data, will not all occupy the sky to the first redundancy ratio special zone SBA1 Between.Opposite, since third data D3 is incompressible data, size is 4096 bytes, therefore third data D3 lump-sum numbers According to can be stored in the second data bit area DBA2 of the second physical procedures unit, and with third data D3 relevant Three data management information DMI3 are stored in the second redundancy ratio special zone SBA2 of the second physical procedures unit.That is, this Invention can allow the data management information of corresponding compressed data be stored in data ratio together with the compressed data corresponding to it In special zone, the space occupied to redundancy ratio special zone will not be gone to.Thus, more can be stored in a physical procedures unit When compressed data, it can also make the redundancy ratio special zone of physical procedures unit can be with retaining space to store other information.

Figure 10 is with unpacked data according to storage compressed data shown by exemplary embodiment of the present invention in multiple physics journeys The schematic diagram of another example of sequence unit.

Please refer to Figure 10, for example, third physical procedures unit is divided into third data bit area DBA3 and Triple redundance bit area SBA3, the wherein size of third data bit area DBA3 are 4096 bytes.4th physical procedures unit quilt It is divided into the 4th data bit area DBA4 and the 4th redundancy ratio special zone SBA4, wherein the size of the 4th data bit area DBA4 is 4096 bytes.5th physical procedures unit has been divided the 5th data bit area DBA5 and the 5th redundancy ratio special zone SBA5, In the 5th data bit area DBA5 size be 4096 bytes.Here, the 4th data RD4 is compressible data, and compressed As the 4th compressed data CD4, wherein the size of the 4th compressed data CD4 is 3064 bytes.5th data RD5 is compressible number According to, and have been compressed into as the 5th compressed data CD5, wherein the size of the 5th compressed data CD5 is 2040 bytes.6th data D6 is incompressible data, and size is 4096 bytes.Also, the 7th data D7 is incompressible data, size 3072 Byte.

In Fig. 10, there are two error checking and schools for the third data bit area DBA3 storages of third physical procedures unit Code frame, one is the 4th error checking and correcting code frame ECCF4, and size is third error checking and correcting code frame length ECCF3 (that is, 3072 bytes)；The other is the 5th error checking and correcting code frame ECCF5, size be the first error checking with Correcting code frame ECCF1 length (that is, 1024 bytes).4th error checking includes the 4th compressed data CD4 with correcting code frame ECCF4 With the 4th data management information DMI4, the 5th error checking and first that correcting code frame ECCF5 includes the 5th compressed data CD5 Part.Since the 5th compressed data CD5 cannot be stored all in third data bit area DBA3, therefore the 5th compressed data CD5 can be divided into two parts.First part (that is, size is the first half of 1024 bytes) quilt of 5th compressed data CD5 It is divided into the 5th error checking and correcting code frame ECCF5, and is connected at the 4th error checking and quilt after correcting code frame ECCF4 It is stored in third data bit area DBA3.The second part of 5th compressed data CD5 is (that is, size is the later half of 1016 bytes Portion) with the 5th data management information DMI5 of corresponding 5th data RD5 it is planned as the 6th error checking and correcting code frame ECCF6, and the 6th error checking is stored in the 4th data bit of the 4th physical procedures unit with correcting code frame ECCF6 In area DBA4, wherein the size of the 6th error checking and correcting code frame ECCF6 are the first error checking and correcting code frame ECCF1 long It spends (that is, 1024 bytes).

As described above, the 4th data bit area DBA4 of the 4th physical procedures unit has been stored with the 6th error checking With correcting code frame ECCF6, therefore when memorizer control circuit unit 104 (or memory management circuitry 202) to store it is incompressible The 6th data D6 when, since the 6th data D6 cannot be stored all into the 4th data bit area DBA4, therefore the 6th data D6 can be divided into two parts.First part's (that is, size is the first half of 3072 bytes) of 6th data D6 is divided into 7th error checking and correcting code frame ECCF7 and being connected at after the 6th error checking and correcting code frame ECCF6 is stored in In 4th data bit area DBA4, wherein the size of the 7th error checking and correcting code frame ECCF7 are third error checking and school Code frame ECCFF3 length.Then, since the 6th data D6 is stored in the 4th physical procedures unit, memorizer control circuit Unit 104 (or memory management circuitry 202) can store the 6th data management information DMI6 to the 4th of corresponding 6th data D6 In 4th redundancy ratio special zone SBA4 of physical procedures unit.And the second part of the 6th data D6 is (that is, size is 1024 words The second part of section) it is planned as the 8th error checking and correcting code frame ECCF8, and the 8th error checking and correcting code frame ECCF8 is stored in the 5th data bit area DBA5 of the 5th physical procedures unit, wherein the 8th error checking and correction The size of code frame ECCF8 is the first error checking and correcting code frame ECCF1 length.

It is noted that in another exemplary embodiment, memorizer control circuit unit 104 (or memory management electricity Road 202) can the first data management information DMI1 first be generated according to First Transition data TD1, and according to First Transition data The size summation of TD1 and the first data management information DMI1 determines to store First Transition data TD1 and the first data pipe The size of the first error checking for managing information DMI1 and correcting code frame ECCF1 are which error checking and correcting code frame length, and And data PD1 is filled up to fill up unfilled space with first.For example, if the size of First Transition data TD1 is 2000 bytes, the size of the first data management information DMI1 are 10 bytes, then (or the memory of memorizer control circuit unit 104 Management circuit 202) First Transition data TD1 and the first data management information DMI1 can be divided as the first error checking and correcting code Frame ECCF1, size is the second error checking and correcting code frame ECCF2 length (that is, 2048 bytes), and it is 38 that size, which is added, The first of byte (that is, 2048-2000-10=38) fills up data PD1 in the first error checking and correcting code frame ECCF1.

Figure 11 is according to the first exemplary embodiment of the invention, shown data managing method flow chart.

1 is please referred to Fig.1, in step S1101, memorizer control circuit unit 104 (or memory management circuitry 202) will Each physical procedures dividing elements are data bit area and redundancy ratio special zone.In step S1103, memorizer control circuit list First 104 (or memory management circuitries 202) receive the first data RD1 of the first write instruction and corresponding first write instruction, Then in step S1105, memorizer control circuit unit 104 (or memory management circuitry 202) is according to the first write instruction The first data management information DMI1 of first data RD1 corresponding with the first data RD1 generations, and in step S1107, storage Device control circuit unit 104 (or memory management circuitry 202) judges whether the first data RD1 is compressible.

If in step S1107, memorizer control circuit unit 104 (or memory management circuitry 202) identification first When data RD1 can be compressed, in step S1109, memorizer control circuit unit 104 (or memory management circuitry 202) meeting Designation date compression/decompression circuit 214 compresses the first data RD1 to generate the first compressed data CD1, and memory controls Circuit unit 104 (or memory management circuitry 202) will produce the first data compression information of corresponding first data RD1, and By the first physics journey among the first compressed data CD1 and the first data management information DMI1 sequencing to physical procedures unit First data bit area DBA1 of sequence unit.Then, in step S1111, memorizer control circuit unit 104 (or storage Device manages circuit 202) the first data RD1 can be compressed information programme to the first redundant bit of the first physical procedures unit Area SBA1 terminates the flow of entire data managing method.

If in step S1107, memorizer control circuit unit 104 (or memory management circuitry 202) identification first When data RD1 not can be compressed, in step S1113, memorizer control circuit unit 104 (or memory management circuitry 202) It will produce the first data RD1 compression information of corresponding first data RD1, and by the first data RD1 sequencing to the first object Manage the first data bit area DBA1 of programmed cell.Then in step S1115, memorizer control circuit unit 104 (or deposit Reservoir manages circuit 202) the first data RD1 is compressed into information and the first data management information DMI1 sequencing to the first physics journey First redundancy ratio special zone SBA1 of sequence unit, terminates the flow of entire data managing method.

[the second exemplary embodiment]

In the second exemplary embodiment, the structure of hardware is similar, but used data managing method can not Together.It is just explained below with the first exemplary embodiment difference for the second exemplary embodiment.

Figure 12 A~F are according to storage compressed data showing in physical procedures unit shown by exemplary embodiment of the present invention It is intended to.

Please refer to Figure 12 A, for example, memorizer control circuit unit 104 (or memory management circuitry 202) receives big Small is the compressible first data RD1 of 4096 bytes, and corresponding first data RD1, memorizer control circuit unit 104 (or memory management circuitry 202) indicates that error checking generates the first error checking and correcting code with correcting circuit 212.Then, First data RD1 is collapsed into First Transition data by memorizer control circuit unit 104 (or memory management circuitry 202) TD1.It is 2000bytes in the size of this First Transition data TD1, is more than the first default reduction length and is preset less than second Reduction length.After compressing the first data RD1, a first data RD1 compression information (not shown) is produced, wherein first Data RD1 compression information records indicate the first data RD1 compressed information, and also have recorded the first data RD1 compressions At the compression ratio of First Transition data TD1.

Figure 12 B are please referred to, unlike the first exemplary embodiment, since the size of First Transition data TD1 is more than the One default reduction length and it is less than the second default reduction length, (or the memory management circuitry of memorizer control circuit unit 104 202) size of corresponding second default reduction length, the data bit area DBA in the first physical procedures unit divide first Data bit area DBA1, then the first data bit area DBA1 is divided into the first user data field UDA1 and the first management information area MIA1, so that the size of the first user data field UDA1 is the second default reduction length, and the first management information area MIA1 Size is 8 bytes.It is noted that the size of above-mentioned first management information area MIA1 can be set according to demand, the present invention It is not limited to this.

Figure 12 C and Figure 12 D are please referred to, since the size of First Transition data TD1 is less than the first user data field UDA1, Additional one first of memorizer control circuit unit 104 (or memory management circuitry 202) fills up data PD1 in First Transition number After TD1, become the first compressed data CD1, so that the size of the first compressed data CD1 is equal to the first user data field The size of UDA1.Meanwhile memorizer control circuit unit 104 (or memory management circuitry 202) can record first and fill up data The size of PD1 is with address in the first data RD1 compression information.

Figure 12 E and Figure 12 F are please referred to, memorizer control circuit unit 104 (or memory management circuitry 202) will be produced The first compressed data CD1 be stored in the first user data field UDA1, and will corresponding first data RD1 the first data Management information DMI1 (for example, the first error checking and correcting code or logical subunit address of corresponding first data RD1) is deposited It is stored in the first management information area MIA1.Then, memorizer control circuit unit 104 (or memory management circuitry 202) can incite somebody to action The first data RD1 of corresponding first data RD1 compresses information storage to the first redundancy ratio special zone SBA1.

Figure 13 is according to storage unpacked data shown by exemplary embodiment of the present invention in the signal of physical procedures unit Figure.

Please refer to Figure 13, it is assumed that the compressions of the first compressed data CD1 and second have been stored in the first physical procedures unit Under data CD2, memorizer control circuit unit 104 (or memory management circuitry 202) receive size be 4096 bytes can not The third data D3 of compression, wherein third data D3 are incompressible data, size 4096bytes, and the first physics Programmed cell does not have space that can store third data D3.Due to the second physics after the first physical procedures unit that sorts It is 4096 bytes that programmed cell, which has the data bit area of blank, size, therefore, memorizer control circuit unit 104 (or Memory management circuitry 202) it can be in the third that the data bit Division size of the second physical procedures unit is 4096 bytes Third data D3 lump-sums data are all stored in the third data bit of the second physical procedures unit by data bit area DBA3 In area DBA3, and the third data management information DMI3 of corresponding third data D3 and third data compression information are stored in the In second redundancy ratio special zone SBA2 of two physical procedures units.

Figure 14 is according to the second exemplary embodiment of the invention, shown data managing method flow chart.

4 are please referred to Fig.1, in step S1401, memorizer control circuit unit 104 (or memory management circuitry 202) will Each physical procedures unit is at least divided into a data bit area and a redundancy ratio special zone.Then, in step S1403 In, memorizer control circuit unit 104 (or memory management circuitry 202) receives the first write instruction and corresponding first write-in First data RD1 of instruction, wherein the first data RD1 is compressible data.Then, in step S1405, memory control electricity (or memory management circuitry 202) designation date of road unit 104 compression/decompression circuit 214 is by the first data RD1 boil down tos One compressed data CD1, and the first data RD1 compression information of corresponding first data RD1 is generated, wherein the first data RD1 compressions The first data RD1 of information record instruction compressed information and has recorded the compression ratio of corresponding first data RD1.Then in step In rapid S1407, memorizer control circuit unit 104 (or memory management circuitry 202) is by the among physical procedures unit First data bit area DBA1 of one physical procedures unit is divided into the first user data field UDA1 and the first management information Area MIA1.Then in step S1409, memorizer control circuit unit 104 (or memory management circuitry 202) is compressed first Data CD1 sequencing is to the first user data field UDA1, by the first data management information DMI1 of corresponding first data RD1 In sequencing to the first management information area MIA1, and the first data RD1 is compressed into information programme to the first physical procedures First redundancy ratio special zone SBA1 of unit, terminates the flow of entire data managing method.

It is worth noting that, the information that above-mentioned data management information/data management area or redundancy ratio special zone are stored is only It is used to illustrate the invention, is not used in the restriction present invention.

In conclusion the present invention can allow the data management information of corresponding compressed data with its corresponding to compression number According to being stored in together in data bit area, the space occupied to redundancy ratio special zone will not be gone to.Thus, can be in a physics When programmed cell stores more compressed datas, the redundancy ratio special zone of physical procedures unit can also be allow to retain sky Between to store other information, and then promote memory storage apparatus space service efficiency and effectively management can compress number According to relevant information.

Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：Its according to So can with technical scheme described in the above embodiments is modified, either to which part or all technical features into Row equivalent replacement；And these modifications or replacements, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution The range of scheme.

Claims (24)

1. a kind of data managing method, which is characterized in that be used for a rewritable non-volatile memory module, wherein this can be answered Formula non-volatile memory module is write comprising multiple physical erase units and multiple logic units are to map at least part of be somebody's turn to do A little physical erase units, wherein each physical erase unit has multiple physical procedures units, which includes：

It is a data bit area and a redundancy ratio special zone by each of physical procedures dividing elements；

Receive one first data of one first write instruction and corresponding first write instruction；

According to one first data management information of first write instruction, first data corresponding with the first data generation；

Judge whether first data are compressible, and generates one first data pressure of corresponding first data according to judging result Contracting information；

If first data are compressible, first data are compressed to generate one first compressed data, this first is compressed Data and 1 among the one first data management information sequencing to those physical procedures units of corresponding first data One first data bit area of one physical procedures unit, and by the first data compression information sequencing to first physics One first redundancy ratio special zone of programmed cell；And

If first data are incompressible, by first Data programming to the first physical procedures unit this One data bit area, and by first data compression information and the first data management information sequencing to the first physics journey The first redundancy ratio special zone of sequence unit.

2. data managing method according to claim 1, which is characterized in that first write instruction instruction first counts this According to storing to one first logical subunit, and it is above-mentioned according to first write instruction it is corresponding with the first data generation this first The step of first data management information of data includes：

One first data error check caused by corresponding first data is integrated into first data management letter with correcting code In breath；And

The address of first logical subunit corresponding to first data is integrated into first data management information.

3. data managing method according to claim 1, which is characterized in that above-mentioned generation correspond to first data this The step of one data compression information includes：

The integrated instruction whether compressed information of first data is into first data compression information；And

If first data are compressible, a compression ratio of corresponding first data is integrated into first data compression information In.

4. data managing method according to claim 2, which is characterized in that further include：

If first data are compressible, compressing first data becomes a First Transition data；

Judge the size of the First Transition data；

If the size of the First Transition data is less than or equal to one first default reduction length, which is added One first, which fills up data, becomes first compressed data, so that the size of first compressed data is equal to the first default compression length Degree, and first compressed data and first data management information are divided into one first error checking and correcting code frame, wherein First error checking and the size of correcting code frame are equal to one first error checking and correcting code frame length；

If the size of the First Transition data is more than the first default reduction length and is less than one second default reduction length, will The First Transition data, which are added one second, which fills up data, becomes first compressed data, so that the size etc. of first compressed data In the second default reduction length, and first compressed data and first data management information are divided into first mistake and examined Look into correcting code frame, wherein the size of first error checking and correcting code frame is equal to one second error checking and correcting code frame is long Degree；

If the size of the First Transition data is more than the second default reduction length and presets reduction length less than a third, will A third, which is added, in the First Transition data, which fills up data, becomes first compressed data, so that the size etc. of first compressed data Reduction length is preset in the third, and first compressed data and first data management information are divided into first mistake and examined Look into correcting code frame, wherein the size of first error checking and correcting code frame is equal to a third error checking and correcting code frame is long Degree；And

It presets reduction length if the size of the First Transition data is more than the third and is less than one the 4th default reduction length, it will The First Transition data, which are added one the 4th, which fills up data, becomes first compressed data, so that the size etc. of first compressed data In the 4th default reduction length, and first compressed data and first data management information are divided into first mistake and examined Look into correcting code frame, wherein the size of first error checking and correcting code frame is equal to one the 4th error checking and correcting code frame is long Degree；And

By first error checking and correcting code frame sequencing to the first data bit area.

5. data managing method according to claim 4, which is characterized in that further include：

The size of first logical subunit and the size of the first physical procedures unit are a transmission unit size, wherein should Transmission unit size is 4096 bytes；

The size of first error checking and correcting code frame length is a quarter of the size of the first physical procedures unit；

The size of second error checking and correcting code frame length is the half of the size of the first physical procedures unit；

The size of the third error checking and correcting code frame length is 3/4ths of the size of the first physical procedures unit； And

The size of 4th error checking and correcting code frame length is the size of the first physical procedures unit.

6. data managing method according to claim 4, which is characterized in that further include：

The integrated corresponding First Transition data this first fill up data, this second fill up data, the third fills up data or should 4th fills up the information of the address of data and size into first data management information.

7. a kind of data managing method is used for a rewritable non-volatile memory module, which is characterized in that the duplicative Non-volatile memory module is comprising multiple physical erase units and multiple logic units are to map those at least part of objects Erased cell is managed, wherein each physical erase unit has multiple physical procedures units, which includes：

Each of physical procedures unit is at least divided into a data bit area and a redundancy ratio special zone；

One first data are received, wherein first data are a compressible data；

It is one first compressed data by first data compression, and generates the one first data compression letter of corresponding first data Breath, wherein indicate the whether compressed information of first data and a compression ratio of corresponding first data be integrated into this first In data compression information；

First data bit zoning of one first physical procedures unit among those physical procedures units is divided into one One user data field and one first management information area；

By the first compressed data sequencing to the first user data field, by one first data pipe of corresponding first data It manages in information programme to first management information area, and by the first data compression information sequencing to the first physics journey One first redundancy ratio special zone of sequence unit.

8. data managing method according to claim 7, which is characterized in that further include：

One second data are received, wherein second data are an incompressible data；And

By a data of one second physical procedures unit among second Data programming to those physical procedures units Bit area, by one second data management information of corresponding second data and one second data compression information sequencing to this second One redundancy ratio special zone of physical procedures unit, wherein indicating that second data are that the information of the incompressible data is integrated into In second data compression information.

9. a kind of memorizer control circuit unit, for controlling a rewritable non-volatile memory module, which is characterized in that The memorizer control circuit unit includes：

One host interface is electrically connected to a host system；

One memory interface is electrically connected to the rewritable non-volatile memory module, and the wherein duplicative is non- Volatile storage module is comprising multiple physical erase units and multiple logic units are to map those at least part of physics Erased cell, wherein each physical erase unit has multiple physical procedures units；

One memory management circuitry is electrically connected to the host interface and the memory interface, and configures multiple logic units To map those at least part of physical erase units；And

One data compression/decompression contracting circuit is electrically connected the memory management circuitry, and to be compressed or be decompressed to data Contracting operation,

The wherein memory management circuitry is being a data bit area and one superfluous by each of physical procedures dividing elements Remaining bit area,

Wherein the memory management circuitry is also receiving the one the of one first write instruction and corresponding first write instruction One data,

Wherein the memory management circuitry is also to according to first write instruction, first number corresponding with the first data generation According to one first data management information,

The wherein memory management circuitry also to judge whether first data are compressible, and according to judging result generate pair Should the first data one first data compression information,

If wherein first data be it is compressible, the memory management circuitry also to indicate the data compression/decompression contract Circuit compression first data are to generate one first compressed data, and the memory management circuitry is also assigning an instruction sequence extremely The rewritable non-volatile memory module is with by one first data pipe of first compressed data and corresponding first data One first data bit area of one first physical procedures unit among information programme to those physical procedures units is managed, And by the one first redundancy ratio special zone of the first data compression information sequencing to the first physical procedures unit,

If wherein first data be it is incompressible, the memory management circuitry also to assign an instruction sequence to this can Manifolding formula non-volatile memory module with by first Data programming to the first physical procedures unit this first number According to bit area, and by first data compression information and the first data management information sequencing to first physical procedures The first redundancy ratio special zone of unit.

10. memorizer control circuit unit according to claim 9, which is characterized in that first write instruction instruction will First data are stored to one first logical subunit, and are generated according to first write instruction and first data above-mentioned In the running of first data management information of corresponding first data, the memory management circuitry will be will correspond to first number It is integrated into first data management information according to generated 1 first data error check and correcting code,

Wherein the memory management circuitry is also integrating the address of first logical subunit corresponding to first data Into in first data management information.

11. memorizer control circuit unit according to claim 9, which is characterized in that above-mentioned generation correspond to this first In the running of first data compression information of data, whether which also indicates first data to integrated Compressed information into first data compression information,

If wherein first data are compressible, the memory management circuitry is also to the one of integrated corresponding first data Compression ratio is into first data compression information.

12. memorizer control circuit unit according to claim 10, which is characterized in that further include：

If first data are compressible, data compression/decompression contracting circuit compression first data are as one first mistake Cross data,

The wherein memory management circuitry also to judge the size of the First Transition data,

If wherein the size of the First Transition data is less than or equal to one first default reduction length, the memory management circuitry Also become first compressed data data are filled up in First Transition data addition one first, so that first compressed data Size be equal to the first default reduction length, and first compressed data and first data management information are divided into one the One error checking and correcting code frame, wherein first error checking and the size of correcting code frame are equal to one first error checking and school Code frame length,

If wherein the size of the First Transition data is more than the first default reduction length and less than one second default compression length Degree, the memory management circuitry also become the first compression number data are filled up in First Transition data addition one second According to so that the size of first compressed data be equal to the second default reduction length, and by first compressed data and this first Data management information is divided into first error checking and correcting code frame, the wherein size of first error checking and correcting code frame Equal to one second error checking and correcting code frame length,

If wherein the size of the First Transition data is more than the second default reduction length and less than the default compression length of a third Degree, the memory management circuitry also fill up data as the first compression number a third is added in the First Transition data According to so that the size of first compressed data be equal to the third preset reduction length, and by first compressed data and this first Data management information is divided into first error checking and correcting code frame, the wherein size of first error checking and correcting code frame Equal to a third error checking and correcting code frame length,

If wherein the size of the First Transition data is more than the third and presets reduction length and preset compression length less than one the 4th Degree, the memory management circuitry also become the first compression number data are filled up in First Transition data addition one the 4th According to so that the size of first compressed data be equal to the 4th default reduction length, and by first compressed data and this first Data management information is divided into first error checking and correcting code frame, the wherein size of first error checking and correcting code frame Equal to one the 4th error checking and correcting code frame length,

Wherein the memory management circuitry also to assign an instruction sequence to the rewritable non-volatile memory module with By first error checking and correcting code frame sequencing to the first data bit area.

13. memorizer control circuit unit according to claim 12, which is characterized in that further include：

The size of first logical subunit and the size of the first physical procedures unit are a transmission unit size, wherein should Transmission unit size is 4096 bytes；

The size of first error checking and correcting code frame length is a quarter of the size of the first physical procedures unit；

The size of second error checking and correcting code frame length is the half of the size of the first physical procedures unit；

The size of the third error checking and correcting code frame length is 3/4ths of the size of the first physical procedures unit； And

The size of 4th error checking and correcting code frame length is the size of the first physical procedures unit.

14. memorizer control circuit unit according to claim 12, which is characterized in that further include：

The memory management circuitry also to the integrated corresponding First Transition data this first fill up data, this second fill up several Data are filled up according to, the third or the 4th fill up the address of data and the information of size into first data management information.

15. a kind of memorizer control circuit unit, for controlling a rewritable non-volatile memory module, feature exists In the memorizer control circuit unit includes：

One host interface is electrically connected to a host system；

One memory interface is electrically connected to the rewritable non-volatile memory module, and the wherein duplicative is non- Volatile storage module is comprising multiple physical erase units and multiple logic units are to map those at least part of physics Erased cell, wherein each physical erase unit has multiple physical procedures units；

One memory management circuitry is electrically connected to the host interface and the memory interface, and configures multiple logic units To map those at least part of physical erase units；And

One data compression/decompression contracting circuit is electrically connected the memory management circuitry, and to be compressed or be decompressed to data Contracting operation,

Wherein the memory management circuitry to by each of physical procedures unit be at least divided into a data bit area with One redundancy ratio special zone,

The wherein memory management circuitry is to receive one first data, and wherein first data are a compressible data,

Wherein the memory management circuitry to indicate the data compression/decompression contracting circuit by first data compression be one first Compressed data, and the memory management circuitry generates one first data compression information of corresponding first data, wherein indicating The whether compressed information of first data is integrated into a compression ratio of corresponding first data by the memory management circuitry In first data compression information,

Wherein the memory management circuitry is to by one first physical procedures unit among those physical procedures units First data bit zoning is divided into one first user data field and one first management information area,

Wherein the memory management circuitry to assign an instruction sequence to the rewritable non-volatile memory module with will The first compressed data sequencing is to the first user data field, by one first data management information of corresponding first data In sequencing to first management information area, and by the first data compression information sequencing to the first physical procedures list First redundancy ratio special zone of member.

16. memorizer control circuit unit according to claim 15, which is characterized in that further include：

The memory management circuitry is also to receive one second data, and wherein second data are an incompressible data,

Wherein the memory management circuitry to assign an instruction sequence to the rewritable non-volatile memory module with will One data bit area of one second physical procedures unit in second Data programming to those physical procedures units, will One second data management information of corresponding second data and one second data compression information sequencing are to second physical procedures Change a redundancy ratio special zone of unit, wherein indicating that the information that second data are the incompressible data is electric by the memory management Road is integrated into second data compression information.

17. a kind of memory storage apparatus, which is characterized in that including：

One connecting interface unit, is electrically connected to a host system；

One rewritable non-volatile memory module, wherein the rewritable non-volatile memory module have multiple physics Erased cell and multiple logic units are to map those at least part of physical erase units, wherein each physical erase unit With multiple physical procedures units；And

One memorizer control circuit unit is electrically connected to the connecting interface unit and the rewritable non-volatile memory mould Block, and configure multiple logic units to map those at least part of physical erase units, the memorizer control circuit unit To be a data bit area and a redundancy ratio special zone by each of physical procedures dividing elements,

Wherein the memorizer control circuit unit is also receiving one first write instruction and corresponding first write instruction One first data,

Wherein the memorizer control circuit unit also to according to first write instruction it is corresponding with the first data generation this One first data management information of one data,

Wherein the memorizer control circuit unit is also to judge whether first data are compressible, and is produced according to judging result One first data compression information of raw corresponding first data,

If wherein first data are compressible, the memorizer control circuit unit is also compressing first data to produce Raw one first compressed data, extremely by first compressed data and one first data management information sequencing of corresponding first data One first data bit area of one first physical procedures unit in those physical procedures units, and by first data Compress information programme to one first redundancy ratio special zone of the first physical procedures unit,

If wherein first data are incompressible, the memorizer control circuit unit is also to by first data program Change to the first data bit area of the first physical procedures unit, and by first data compression information and this first number According to the first redundancy ratio special zone of management information sequencing to the first physical procedures unit.

18. memory storage apparatus according to claim 17, which is characterized in that first write instruction instruction by this One data are stored to one first logical subunit, and above-mentioned corresponding with the first data generation according to first write instruction In the running of first data management information of first data, the memorizer control circuit unit also to will correspond to this first One first data error check caused by data is integrated into correcting code in first data management information,

Wherein the memorizer control circuit unit is also to by the address of first logical subunit corresponding to first data It is integrated into first data management information.

19. memory storage apparatus according to claim 17, which is characterized in that correspond to first data in above-mentioned generation First data compression information running in, the memorizer control circuit unit also to record indicate first data whether Compressed information in first data compression information,

If wherein first data are compressible, the memorizer control circuit unit is also to integrated corresponding first data A compression ratio into first data compression information.

20. memory storage apparatus according to claim 18, which is characterized in that further include：

If first data are compressible, the memorizer control circuit cell compression first data become a First Transition Data,

The wherein memorizer control circuit unit also to the size for judging the First Transition data,

If wherein the size of the First Transition data is less than or equal to one first default reduction length, the memorizer control circuit Unit also becomes first compressed data data are filled up in First Transition data addition one first, so that first compression The size of data is equal to the first default reduction length, and first compressed data and first data management information are divided into One first error checking and correcting code frame, wherein first error checking and the size of correcting code frame are equal to one first error checking With correcting code frame length,

If wherein the size of the First Transition data is more than the first default reduction length and less than one second default compression length Degree, the memorizer control circuit unit also become first compression data are filled up in First Transition data addition one second Data so that the size of first compressed data is equal to the second default reduction length, and by first compressed data and this One data management information is divided into first error checking and correcting code frame, and wherein first error checking and correcting code frame is big It is small to be equal to one second error checking and correcting code frame length,

If wherein the size of the First Transition data is more than the second default reduction length and less than the default compression length of a third Degree, the memorizer control circuit unit also fill up data as first compression a third is added in the First Transition data Data so that the size of first compressed data is equal to the third and presets reduction length, and by first compressed data and this One data management information is divided into first error checking and correcting code frame, and wherein first error checking and correcting code frame is big It is small to be equal to a third error checking and correcting code frame length,

If wherein the size of the First Transition data is more than the third and presets reduction length and preset compression length less than one the 4th Degree, the memorizer control circuit unit also become first compression data are filled up in First Transition data addition one the 4th Data so that the size of first compressed data is equal to the 4th default reduction length, and by first compressed data and this One data management information is divided into first error checking and correcting code frame, and wherein first error checking and correcting code frame is big It is small to be equal to one the 4th error checking and correcting code frame length,

Wherein the memorizer control circuit unit is also to by first error checking and the sequencing of correcting code frame to first number According to bit area.

21. memory storage apparatus according to claim 20, which is characterized in that further include：

The size of first logical subunit and the size of the first physical procedures unit are a transmission unit size, wherein should Transmission unit size is 4096 bytes；

The size of first error checking and correcting code frame length is a quarter of the size of the first physical procedures unit；

The size of second error checking and correcting code frame length is the half of the size of the first physical procedures unit；

The size of the third error checking and correcting code frame length is 3/4ths of the size of the first physical procedures unit； And

The size of 4th error checking and correcting code frame length is the size of the first physical procedures unit.

22. memory storage apparatus according to claim 20, which is characterized in that further include：

The memorizer control circuit unit also first fills up that data, this second fills out to this of the integrated corresponding First Transition data Complement fills up data according to, the third or the 4th fills up the address of data and the information of size into first data management information In.

23. a kind of memory storage apparatus, which is characterized in that including：

One connecting interface unit, is electrically connected to a host system；

One rewritable non-volatile memory module, wherein the rewritable non-volatile memory module have multiple physics Erased cell and multiple logic units are to map those at least part of physical erase units, wherein each physical erase unit With multiple physical procedures units；And

One memorizer control circuit unit is electrically connected to the connecting interface unit and the rewritable non-volatile memory mould Block, and configure multiple logic units to map those at least part of physical erase units, the memorizer control circuit unit To be a data bit area and a redundancy ratio special zone by each of physical procedures dividing elements,

The wherein memorizer control circuit unit is also to receive one first data, and wherein first data are a compressible number According to,

Wherein the memorizer control circuit unit is also being one first compressed data, and the storage by first data compression Device control circuit unit generates one first data compression information of corresponding first data, wherein indicate first data whether by The information of compression is integrated into the first data pressure with a compression ratio of corresponding first data by the memorizer control circuit unit In contracting information,

Wherein the memorizer control circuit unit is also to by one first physical procedures among those physical procedures units First data bit zoning of unit is divided into one first user data field and one first management information area,

The wherein memorizer control circuit unit also to by the first compressed data sequencing to the first user data field, It first is counted by the one first data management information sequencing to first management information area of corresponding first data, and by this According to compression information programme to the first redundancy ratio special zone of the first physical procedures unit.

24. memory storage apparatus according to claim 23, which is characterized in that further include：

The memorizer control circuit unit is also to receive one second data, and wherein second data are an incompressible data,

Wherein the memorizer control circuit unit is also to will be among second Data programming to those physical procedures units One second physical procedures unit a data bit area, will corresponding second data one second data management information and one Second data compression information sequencing is to a redundancy ratio special zone of the second physical procedures unit, wherein indicating second data It is integrated into second data compression information by the memorizer control circuit unit for the information of the incompressible data.