CN105278192B - Pixel-driving circuit, array substrate and liquid crystal display panel - Google Patents
Pixel-driving circuit, array substrate and liquid crystal display panel Download PDFInfo
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- CN105278192B CN105278192B CN201510781034.3A CN201510781034A CN105278192B CN 105278192 B CN105278192 B CN 105278192B CN 201510781034 A CN201510781034 A CN 201510781034A CN 105278192 B CN105278192 B CN 105278192B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Optics & Photonics (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
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- Liquid Crystal Display Device Control (AREA)
Abstract
A kind of pixel-driving circuit of present invention offer, array substrate and liquid crystal display panel.Row control separated time (40) is respectively set with the second controlling bus (20), corresponding each row pixel unit (5) in pixel-driving circuit first controlling bus of setting (10), corresponding each row pixel unit (5) is respectively set forward direction and controls thin film transistor (TFT) (T5) and Reverse Turning Control thin film transistor (TFT) (T6)；When forward scan, first controlling bus (10) provides high potential, and the second controlling bus (20) provides low potential；For line n m row pixel unit (5), the grid of third thin film transistor (TFT) (T3) is electrically connected the row control separated time (40) for corresponding to line n pixel unit (5) setting, source electrode is electrically connected time area's pixel electrode (52), drain electrode is electrically connected one end that charge shares capacitance (C1)；It can realize and carry out colour cast compensation in forward scan driving and reverse scan driving, promote the display quality of liquid crystal display panel.
Description
Technical field
The present invention relates to a kind of technical field of liquid crystal display more particularly to pixel-driving circuit, array substrate and liquid crystal surfaces
Plate.
Background technology
Liquid crystal display (Liquid Crystal Display, LCD) be most widely used flat-panel monitor it
One, liquid crystal display panel is the core component of liquid crystal display.Liquid crystal display panel is typically by a colored filter substrate (Color
Filter, CF), a thin-film transistor array base-plate (Thin Film Transistor Array Substrate, TFT
Array Substrate) and the liquid crystal layer (Liquid Crystal Layer) that is configured between two substrates constituted.Generally
Pixel electrode, public electrode are respectively set in array substrate, colored filter substrate.When voltage is applied to pixel electrode and public affairs
Common electrode will generate electric field in the liquid crystal layer, which determines the orientation of liquid crystal molecule, so as to adjust liquid crystal layer is incident on
Light polarization, make liquid crystal display panel show image.
Industry develops a kind of referred to as macromolecule stabilization vertical orientation (Polymer Stabilized at present
Vertical Alignment, PSVA) technology, accordingly there are PSVA type liquid crystal display panels.PSVA technologies are in liquid crystal material
It the monomeric compound (Monomer) of middle incorporation debita spissitudo and shakes uniform；Then, mixed liquid crystal material is placed in and is added
Tropisms (Isotropy) state such as it is heated up on hot device, when temperature is down to room temperature, liquid crystal compound can return to nematic
(Nematic) state；Then, liquid crystal compound is injected between array substrate and colored filter substrate and applies voltage；
When application voltage makes Liquid Crystal Molecules Alignment stablize, then allow monomeric compound that polymerization occurs using the mode of ultraviolet light or heating anti-
Polymeric layer should be formed, thus achievees the purpose that carry out stable alignment to liquid crystal molecule.
As shown in Figure 1, in order to increase visual angle, pixel electrode is usually designed as " rice " font structure by the prior art.Pixel
Electrode includes the horizontal trunk 200 of the vertical trunk 100 and strip of strip, and vertical trunk 100 and 200 center of horizontal trunk are hung down
Straight intersection, so-called center, which intersects vertically, refers to that vertical trunk 100 and horizontal trunk 200 are mutually perpendicular to, and the two is by entire pixel
Electrode area is divided into 4 regions (domain).Each pixel electrode area by with vertical trunk 100 or horizontal trunk
200 in ± 45 °, ± 135 ° angles the tiling composition of strip branch (Slit) 300, each strip branch 300 and vertical trunk 100 and
Horizontal trunk 200 is in the same plane, is formed above and below shown in FIG. 1 and the pixel of " rice " font of the equal mirror symmetry in left and right is electric
Pole structure.
The pixel electrode structure of this " rice " font, because the strip branch 300 in each pixel electrode area leads with vertical
Dry 100 is identical with the angle of horizontal trunk 200, can there is certain visual color or vision colour cast, the penetrance of liquid crystal display panel
Also can decline.
In order to improve visual color or vision colour cast, a pixel unit can be divided into primary area and time area by the prior art,
One independent primary area pixel electrode is set in primary area, independent secondary area's pixel electrode, primary area pixel are set in secondary area
Electrode is all made of above-mentioned " rice " font structure as shown in Figure 1 with time area's pixel electrode and designs.As shown in Fig. 2, existing setting
Include the multiple pixel units 500 arranged in array, correspond to line n from bottom to top in the pixel-driving circuit in array substrate
The horizontally extending nth bar controlling grid scan line G (n) of pixel unit setting, corresponding m row pixel units are set from left to right
The m data line D (m), n and the m that vertically extend set is positive integer.Each pixel unit includes the first film
Transistor T1, the second thin film transistor (TFT) T2, third thin film transistor (TFT) T3, primary area pixel electrode 501, secondary area's pixel electrode 502 and
One charge shares capacitance C1.For line n m row pixel unit 500, the grid of the first film transistor T1 is electrically connected
Nth bar controlling grid scan line G (n), source electrode are electrically connected m data line D (m), drain electrode is electrically connected primary area pixel electrode 501,
The grid of the second thin film transistor (TFT) T2 is electrically connected nth bar controlling grid scan line G (n), source electrode is electrically connected m data lines
D (m), drain electrode are electrically connected time area's pixel electrode 502, and the grid of the third thin film transistor (TFT) T3 is electrically connected corresponding to next
(n+1)th controlling grid scan line G (n+1) of row pixel unit 500, source electrode are electrically connected time area's pixel electrode 502, drain electrode electrically connects
One end that charge shares capacitance C1 is connect, the other end that charge shares capacitance C1 accesses common voltage.
Pixel-driving circuit shown in Fig. 2 is only applicable to simple scanning, i.e. gated sweep signal provides line by line from bottom to top,
When scanning is to line n pixel unit 500, nth bar controlling grid scan line G (n) transmits high potential signal, line n pixel unit 500
All first film transistor T1 and the second thin film transistor (TFT) T2 is opened, third thin film transistor (TFT) T3 is closed, line n m row
Primary area pixel electrode 501 in pixel unit 500 is charged to identical voltage with time area's pixel electrode 502；And then, it scans
When to the (n+1)th row pixel unit 500, (n+1)th controlling grid scan line G (n+1) transmits high potential signal, line n pixel unit 500
All first film transistor T1 and the second thin film transistor (TFT) T2 is closed, third thin film transistor (TFT) T3 is opened, line n m row
Charge in pixel unit 500 shares capacitance C1 and drags down time voltage of area's pixel electrode 502 so that primary area pixel electrode 501 with
The voltage of secondary area's pixel electrode 502 is different, and then eliminates the color offset phenomenon that liquid crystal display panel is generated by visual angle difference.
And work as reverse scanning, i.e., when gated sweep signal provides line by line from top to bottom, in line n m row pixel unit 500
Primary area pixel electrode 501 it is identical as time area's 502 charged voltage holding of pixel electrode, can not achieve colour cast and compensate.
Invention content
The purpose of the present invention is to provide a kind of pixel-driving circuits, equal when forward scan driving and reverse scan drive
It can realize the function of colour cast compensation.
The present invention also aims to provide a kind of array substrate, the equal energy when forward scan driving and reverse scan drive
The function of enough realizing colour cast compensation, to promote the display quality of liquid crystal display panel.
The purpose of the present invention is to provide a kind of liquid crystal display panel again, the equal energy when forward scan driving and reverse scan drive
The function of enough realizing colour cast compensation, has good display quality.
To achieve the above object, present invention firstly provides a kind of pixel-driving circuit, include arrange in array it is multiple
Pixel unit, the horizontally extending nth bar controlling grid scan line for corresponding to the setting of line n pixel unit from top to bottom, certainly a left side
To the setting of right correspondence m row pixel units the m data lines vertically extended, one article vertically extend the
One controlling bus, second controlling bus vertically extended, corresponding each row pixel unit be respectively set along level
The forward direction that control separated time, corresponding each row pixel unit are respectively set of going of direction extension controls thin film transistor (TFT) and corresponds to each
The Reverse Turning Control thin film transistor (TFT) that row pixel unit is respectively set, n and m is positive integer；
Each pixel unit includes first film transistor, the second thin film transistor (TFT), third thin film transistor (TFT), primary area picture
Plain electrode, secondary area's pixel electrode and charge share capacitance；For line n m row pixel units, the first film transistor
Grid be electrically connected nth bar controlling grid scan line, source electrode is electrically connected m data lines, drain electrode is electrically connected primary area pixel electricity
Pole, the grid of second thin film transistor (TFT) is electrically connected nth bar controlling grid scan line, source electrode is electrically connected m data lines, leakage
Pole is electrically connected time area's pixel electrode, and the grid electric connection of the third thin film transistor (TFT) is set corresponding to line n pixel unit
Row control separated time, the source electrode set are electrically connected time area's pixel electrode, drain electrode is electrically connected one end that charge shares capacitance, and charge is total
Enjoy the other end access common voltage of capacitance；
For line n pixel unit, the grid of the positive control thin film transistor (TFT) is electrically connected the first controlling bus, source
Pole is electrically connected (n+1)th controlling grid scan line corresponding to next line pixel unit, and drain electrode, which is electrically connected, corresponds to line n pixel
The grid of the row control separated time of unit setting, the Reverse Turning Control thin film transistor (TFT) is electrically connected the second controlling bus, source electrode electricity
Property connection corresponding to lastrow pixel unit (n-1)th controlling grid scan line, drain electrode be electrically connected correspond to line n pixel unit
The row control separated time of setting；
When forward scan, first controlling bus provides high potential, and the second controlling bus provides low potential；Reverse scan
When, first controlling bus provides low potential, and the second controlling bus provides high potential.
When forward scan, the positive control thin film transistor (TFT) is opened；When forward scan is to line n pixel unit, n-th
Controlling grid scan line transmits high potential signal, all first film transistors and the second thin film transistor (TFT) of line n pixel unit
It opens, third thin film transistor (TFT) is closed, the primary area pixel electrode in line n m row pixel units and time area's pixel electrode quilt
Charge to identical voltage；When forward scan is to the (n+1)th row pixel unit, (n+1)th controlling grid scan line transmits high potential letter
Number, all first film transistors of the (n+1)th row pixel unit and the second thin film transistor (TFT) open to primary area pixel electrode with
While secondary area's pixel electrode charging, the positive control thin film transistor (TFT) for corresponding to the setting of line n pixel unit is connected to (n+1)th
Controlling grid scan line controls separated time with the row corresponding to the setting of line n pixel unit so that corresponds to the setting of line n pixel unit
Row control separated time transmits high potential signal, and all third thin film transistor (TFT)s of line n pixel unit are opened, line n m row pixels
Charge in unit shares capacitance and drags down time voltage of area's pixel electrode so that the voltage of secondary area's pixel electrode is less than primary area pixel
The voltage of electrode.
When reverse scan, the Reverse Turning Control thin film transistor (TFT) is opened；When reverse scan is to line n pixel unit, n-th
Controlling grid scan line transmits high potential signal, all first film transistors and the second thin film transistor (TFT) of line n pixel unit
It opens, third thin film transistor (TFT) is closed, the primary area pixel electrode in line n m row pixel units and time area's pixel electrode quilt
Charge to identical voltage；When reverse scan is to the (n-1)th row pixel unit, (n-1)th controlling grid scan line transmits high potential letter
Number, all first film transistors of the (n-1)th row pixel unit and the second thin film transistor (TFT) open to primary area pixel electrode with
While secondary area's pixel electrode charging, the Reverse Turning Control thin film transistor (TFT) for corresponding to the setting of line n pixel unit is connected to (n-1)th
Controlling grid scan line controls separated time with the row corresponding to the setting of line n pixel unit so that corresponds to the setting of line n pixel unit
Row control separated time transmits high potential signal, and all third thin film transistor (TFT)s of line n pixel unit are opened, line n m row pixels
Charge in unit shares capacitance and drags down time voltage of area's pixel electrode so that the voltage of secondary area's pixel electrode is less than primary area pixel
The voltage of electrode.
The primary area pixel electrode is " rice " font structure with time area's pixel electrode, and material is ITO.
The present invention also provides a kind of array substrates, and it includes in array to have pixel-driving circuit, the pixel-driving circuit
Multiple pixel units of formula arrangement, the horizontally extending nth bar grid for corresponding to the setting of line n pixel unit from top to bottom
Scan line, the m data lines vertically extended for corresponding to the setting of m row pixel units from left to right, one article along vertical
First controlling bus of direction extension, second controlling bus vertically extended, corresponding each row pixel unit difference
The positive control film crystal that horizontally extending row control separated time, the corresponding each row pixel unit being arranged are respectively set
The Reverse Turning Control thin film transistor (TFT) that pipe and corresponding each row pixel unit are respectively set, n and m is positive integer；
Each pixel unit includes first film transistor, the second thin film transistor (TFT), third thin film transistor (TFT), primary area picture
Plain electrode, secondary area's pixel electrode and charge share capacitance；For line n m row pixel units, the first film transistor
Grid be electrically connected nth bar controlling grid scan line, source electrode is electrically connected m data lines, drain electrode is electrically connected primary area pixel electricity
Pole, the grid of second thin film transistor (TFT) is electrically connected nth bar controlling grid scan line, source electrode is electrically connected m data lines, leakage
Pole is electrically connected time area's pixel electrode, and the grid electric connection of the third thin film transistor (TFT) is set corresponding to line n pixel unit
Row control separated time, the source electrode set are electrically connected time area's pixel electrode, drain electrode is electrically connected one end that charge shares capacitance, and charge is total
Enjoy the other end access common voltage of capacitance；
For line n pixel unit, the grid of the positive control thin film transistor (TFT) is electrically connected the first controlling bus, source
Pole is electrically connected (n+1)th controlling grid scan line corresponding to next line pixel unit, and drain electrode, which is electrically connected, corresponds to line n pixel
The grid of the row control separated time of unit setting, the Reverse Turning Control thin film transistor (TFT) is electrically connected the second controlling bus, source electrode electricity
Property connection corresponding to lastrow pixel unit (n-1)th controlling grid scan line, drain electrode be electrically connected correspond to line n pixel unit
The row control separated time of setting；
When forward scan, first controlling bus provides high potential, and the second controlling bus provides low potential；Reverse scan
When, first controlling bus provides low potential, and the second controlling bus provides high potential.
When forward scan, the positive control thin film transistor (TFT) is opened；When forward scan is to line n pixel unit, n-th
Controlling grid scan line transmits high potential signal, all first film transistors and the second thin film transistor (TFT) of line n pixel unit
It opens, third thin film transistor (TFT) is closed, the primary area pixel electrode in line n m row pixel units and time area's pixel electrode quilt
Charge to identical voltage；When forward scan is to the (n+1)th row pixel unit, (n+1)th controlling grid scan line transmits high potential letter
Number, all first film transistors of the (n+1)th row pixel unit and the second thin film transistor (TFT) open to primary area pixel electrode with
While secondary area's pixel electrode charging, the positive control thin film transistor (TFT) for corresponding to the setting of line n pixel unit is connected to (n+1)th
Controlling grid scan line controls separated time with the row corresponding to the setting of line n pixel unit so that corresponds to the setting of line n pixel unit
Row control separated time transmits high potential signal, and all third thin film transistor (TFT)s of line n pixel unit are opened, line n m row pixels
Charge in unit shares capacitance and drags down time voltage of area's pixel electrode so that the voltage of secondary area's pixel electrode is less than primary area pixel
The voltage of electrode.
When reverse scan, the Reverse Turning Control thin film transistor (TFT) is opened；When reverse scan is to line n pixel unit, n-th
Controlling grid scan line transmits high potential signal, all first film transistors and the second thin film transistor (TFT) of line n pixel unit
It opens, third thin film transistor (TFT) is closed, the primary area pixel electrode in line n m row pixel units and time area's pixel electrode quilt
Charge to identical voltage；When reverse scan is to the (n-1)th row pixel unit, (n-1)th controlling grid scan line transmits high potential letter
Number, all first film transistors of the (n-1)th row pixel unit and the second thin film transistor (TFT) open to primary area pixel electrode with
While secondary area's pixel electrode charging, the Reverse Turning Control thin film transistor (TFT) for corresponding to the setting of line n pixel unit is connected to (n-1)th
Controlling grid scan line controls separated time with the row corresponding to the setting of line n pixel unit so that corresponds to the setting of line n pixel unit
Row control separated time transmits high potential signal, and all third thin film transistor (TFT)s of line n pixel unit are opened, line n m row pixels
Charge in unit shares capacitance and drags down time voltage of area's pixel electrode so that the voltage of secondary area's pixel electrode is less than primary area pixel
The voltage of electrode.
The primary area pixel electrode is " rice " font structure with time area's pixel electrode, and material is ITO.
The present invention provides a kind of liquid crystal display panel again, including array substrate, colored filter substrate and the configuration being oppositely arranged
PSVA liquid crystal layers between array substrate and colored filter substrate；The PSVA liquid crystal layers include polymeric layer and are scattered in
Liquid crystal in the polymeric layer；The array substrate is the array substrate that aforementioned present invention provides.
Beneficial effects of the present invention：A kind of pixel-driving circuit, array substrate and liquid crystal display panel provided by the invention, setting
Row control separated time, corresponding each row pixel list is respectively set with the second controlling bus, corresponding each row pixel unit in first controlling bus
Positive control thin film transistor (TFT) and Reverse Turning Control thin film transistor (TFT) is respectively set in member, for line n m row pixel units, setting
The grid of third thin film transistor (TFT) is electrically connected corresponding to going for line n pixel unit setting controls separated time, source electrode is electrically connected
Secondary area's pixel electrode, drain electrode are electrically connected one end that charge shares capacitance；When forward scan, first controlling bus provides
High potential, the second controlling bus provide low potential, and forward direction control thin film transistor (TFT) is opened, the master in line n m row pixel units
After area's pixel electrode is first charged to identical voltage with time area's pixel electrode, the scanning of the (n+1)th row pixel unit is then carried out,
It is connected to (n+1)th controlling grid scan line corresponding to the positive control thin film transistor (TFT) of line n pixel unit setting and corresponds to line n
The row control separated time of pixel unit setting so that the row control separated time for corresponding to the setting of line n pixel unit transmits high potential letter
Number, all third thin film transistor (TFT)s of line n pixel unit are opened, and the charge in line n m row pixel units is shared capacitance and drawn
The voltage of low order area pixel electrode so that the voltage of secondary area's pixel electrode is less than the voltage of primary area pixel electrode；Work as reverse scan
When, first controlling bus provides low potential, and the second controlling bus provides high potential, and Reverse Turning Control thin film transistor (TFT) is opened,
After primary area pixel electrode in line n m row pixel units is first charged to identical voltage with time area's pixel electrode, then into
The scanning of row the (n-1)th row pixel unit corresponds to the Reverse Turning Control thin film transistor (TFT) connection (n-1)th of line n pixel unit setting
Controlling grid scan line with corresponding to the row control separated time of line n pixel unit setting so that correspond to line n pixel unit and be arranged
Row control separated time transmit high potential signal, all third thin film transistor (TFT)s of line n pixel unit are opened, line n m row pictures
Charge in plain unit shares capacitance and drags down time voltage of area's pixel electrode so that the voltage of secondary area's pixel electrode is less than primary area picture
The voltage of plain electrode；Colour cast compensation can be carried out in forward scan driving and reverse scan driving by realizing, and promote liquid crystal
The display quality of panel.
Description of the drawings
For further understanding of the features and technical contents of the present invention, it please refers to below in connection with the detailed of the present invention
Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
In attached drawing,
Fig. 1 is the structural schematic diagram of existing " rice " font pixel electrode；
Fig. 2 is the circuit diagram of existing pixel-driving circuit；
Fig. 3 is the circuit diagram of the pixel-driving circuit of the present invention；
Fig. 4 is the cross-sectional view of the liquid crystal display panel of the present invention.
Specific implementation mode
Further to illustrate the technological means and its effect of the invention taken, below in conjunction with the preferred implementation of the present invention
Example and its attached drawing are described in detail.
Include the multiple pixel lists arranged in array referring to Fig. 3, present invention firstly provides a kind of pixel-driving circuit
Member 5, the horizontally extending nth bar controlling grid scan line G (n) for corresponding to the setting of line n pixel unit 5 from top to bottom, certainly a left side
To right correspondence m row pixel unit 5 setting the m data line D (m) vertically extended, one article vertically prolong
The second controlling bus 20 that the first controlling bus 10, one stretched vertically extends, corresponding each row pixel unit 5 are set respectively
The positive control film crystal that horizontally extending row control separated time 40, the corresponding each row pixel unit 5 set are respectively set
Reverse Turning Control the thin film transistor (TFT) T6, n and m that pipe T5 and corresponding each row pixel unit 5 are respectively set are positive integer.
Each pixel unit 5 includes first film transistor T1, the second thin film transistor (TFT) T2, third thin film transistor (TFT)
T3, primary area pixel electrode 51, secondary area's pixel electrode 52 and charge share capacitance C1.For line n m row pixel unit 5, institute
The grid for stating first film transistor T1 is electrically connected nth bar controlling grid scan line G (n), source electrode is electrically connected m data lines D
(m), drain electrode is electrically connected primary area pixel electrode 51, and the grid of the second thin film transistor (TFT) T2 is electrically connected nth bar grid and sweeps
Retouch line G (n), source electrode is electrically connected m data line D (m), drain electrode is electrically connected time area's pixel electrode 52, the third film
The grid of transistor T3 is electrically connected row control separated time 40, the source electrode being arranged corresponding to line n pixel unit 5 and is electrically connected secondary area
Pixel electrode 52, drain electrode are electrically connected one end that charge shares capacitance C1, and the other end that charge shares capacitance C1 accesses common electrical
Pressure.
For line n pixel unit 5, the grid of the positive control thin film transistor (TFT) T5 is electrically connected the first controlling bus
10, source electrode is electrically connected (n+1)th controlling grid scan line G (n+1) corresponding to next line pixel unit 5, drain electrode electric connection pair
It should be electrically connected the in the row control separated time 40 that line n pixel unit 5 is arranged, the grid of the Reverse Turning Control thin film transistor (TFT) T6
Two controlling bus 20, source electrode are electrically connected (n-1)th controlling grid scan line G (n-1) corresponding to lastrow pixel unit 5, drain electrode
It is electrically connected and corresponds to the row control separated time 40 that line n pixel unit 5 is arranged.
The pixel-driving circuit of the present invention can realize that colour cast compensates when forward scan driving and reverse scan drive
Function.
Specifically, when gated sweep signal provides line by line from top to bottom, forward scan driving, first control are carried out
Bus 10 provides high potential, and the second controlling bus 20 provides low potential, and the positive control thin film transistor (TFT) T5 is opened.Work as forward direction
When scanning line n pixel unit 5, nth bar controlling grid scan line G (n) transmits high potential signal, and line n pixel unit 5 owns
First film transistor T1 is opened with the second thin film transistor (TFT) T2, and third thin film transistor (TFT) T3 is closed, line n m row pixels
Primary area pixel electrode 51 in unit 5 is charged to identical voltage with time area's pixel electrode 52；When forward scan to the (n+1)th row
When pixel unit 5, (n+1)th controlling grid scan line G (n+1) transmission high potential signal, all the first of the (n+1)th row pixel unit 5
Thin film transistor (TFT) T1 and the second thin film transistor (TFT) T2 is opened to the same of primary area pixel electrode 51 and 52 charging of time area pixel electrode
When, correspond to the positive control thin film transistor (TFT) T5 that line n pixel unit 5 is arranged and is connected to (n+1)th controlling grid scan line G (n+1)
With the row control separated time 40 being arranged corresponding to line n pixel unit 5 so that correspond to the row control that line n pixel unit 5 is arranged
Separated time 40 transmits high potential signal, and all third thin film transistor (TFT) T3 of line n pixel unit 5 are opened, line n m row pixels
Charge in unit 5 shares capacitance C1 and drags down time voltage of area's pixel electrode 52 so that the voltage of secondary area's pixel electrode 52 is less than
The voltage of primary area pixel electrode 51, the colour cast generated by panel visual angle difference to compensation.
When gated sweep signal provides line by line from bottom to top, reverse scan driving, first controlling bus 10 are carried out
Low potential is provided, the second controlling bus 20 provides high potential, and the Reverse Turning Control thin film transistor (TFT) T6 is opened.When reverse scan is arrived
When line n pixel unit 5, nth bar controlling grid scan line G (n) transmits high potential signal, and all the first of line n pixel unit 5 are thin
Film transistor T1 is opened with the second thin film transistor (TFT) T2, and third thin film transistor (TFT) T3 is closed, in line n m row pixel unit 5
Primary area pixel electrode 51 be charged to identical voltage with time area pixel electrode 52；When reverse scan to the (n-1)th row pixel list
When member 5, (n-1)th controlling grid scan line G (n-1) transmits high potential signal, and all the first films of the (n-1)th row pixel unit 5 are brilliant
It is corresponding while body pipe T1 and the second thin film transistor (TFT) T2 is opened to primary area pixel electrode 51 with 52 charging of pixel electrode of secondary area
It is connected to (n-1)th controlling grid scan line G (n-1) in the Reverse Turning Control thin film transistor (TFT) T6 that line n pixel unit 5 is arranged and corresponds to
The row control separated time 40 that line n pixel unit 5 is arranged so that correspond to the row control separated time 40 that line n pixel unit 5 is arranged and pass
High potential signal is passed, all third thin film transistor (TFT) T3 of line n pixel unit 5 are opened, in line n m row pixel unit 5
Charge shares capacitance C1 and drags down time voltage of area's pixel electrode 52 so that the voltage of secondary area's pixel electrode 52 is less than primary area pixel electricity
The voltage of pole 51, the colour cast generated by panel visual angle difference to compensation.
Further, the primary area pixel electrode 51 and time area's pixel electrode 52 are " rice " font structure.Please refer to figure
1, the primary area pixel electrode 51 of " rice " font structure includes the vertical trunk 100 and strip of strip with time area pixel electrode 52
Horizontal trunk 200, and vertical trunk 100 and 200 center of horizontal trunk intersect vertically, it refers to vertical master that so-called center, which intersects vertically,
Dry 100 and horizontal trunk 200 be mutually perpendicular to, and entire pixel electrode area is divided into 4 regions by the two.Each pixel electricity
Polar region domain is all formed by tiling in the strip branch 300 of ± 45 °, ± 135 ° angles with vertical trunk 100 or horizontal trunk 200,
Each strip branch 300 and vertical trunk 100 and horizontal trunk 200 are in the same plane, form shown in FIG. 1 upper and lower and left and right
The pixel electrode structure of " rice " font of equal mirror symmetry.
The primary area pixel electrode 51 and 52 material of time area pixel electrode be tin indium oxide (Indium Tin Oxide,
ITO) film.
The present invention also provides a kind of array substrates, with above-mentioned pixel-driving circuit as shown in Figure 3, in forward direction
Turntable driving and reverse scan can realize the function of colour cast compensation when driving, promote the display quality of liquid crystal display panel, herein
Repeated description no longer is carried out to pixel-driving circuit.
Referring to Fig. 4, the present invention provides a kind of liquid crystal display panel again, including be oppositely arranged array substrate 1, colored filter
Substrate 2 and the PSVA liquid crystal layers 3 being configured between array substrate 1 and colored filter substrate 2.The PSVA liquid crystal layers 3 include
Polymeric layer 31 and the liquid crystal 32 being scattered in the polymeric layer 31 carry out stabilization to liquid crystal 32 by the polymeric layer 31 and match
To without traditional alignment film is arranged on the opposed inside surface of array substrate 1 and colored filter substrate 2.It is described
Array substrate 1 has above-mentioned pixel-driving circuit as shown in Figure 3, to equal when forward scan driving and reverse scan drive
It can realize the function of colour cast compensation so that liquid crystal display panel has good display quality, herein no longer to pixel-driving circuit
Carry out repeated description.
In conclusion pixel-driving circuit, array substrate and the liquid crystal display panel of the present invention, the first controlling bus of setting and the
Row control separated time is respectively set in two controlling bus, corresponding each row pixel unit, positive control is respectively set in corresponding each row pixel unit
Third thin film transistor (TFT) is arranged for line n m row pixel units in made membrane transistor and Reverse Turning Control thin film transistor (TFT)
Grid is electrically connected and controls separated time corresponding to going for line n pixel unit setting, source electrode is electrically connected secondary area pixel electrode, drain electrode
It is electrically connected one end that charge shares capacitance；When forward scan, first controlling bus provides high potential, and the second control is total
Line provides low potential, and forward direction control thin film transistor (TFT) is opened, the primary area pixel electrode in line n m row pixel units and time area
After pixel electrode is first charged to identical voltage, the scanning of the (n+1)th row pixel unit is then carried out, corresponds to line n pixel
The positive control thin film transistor (TFT) of unit setting is connected to (n+1)th controlling grid scan line and corresponding to the setting of line n pixel unit
Row control separated time so that the row control separated time for corresponding to the setting of line n pixel unit transmits high potential signal, line n pixel list
All third thin film transistor (TFT)s of member are opened, and the charge in line n m row pixel units shares capacitance and drags down time area's pixel electrode
Voltage so that the voltage of secondary area's pixel electrode be less than primary area pixel electrode voltage；When reverse scan, first control
Bus provides low potential, and the second controlling bus provides high potential, and Reverse Turning Control thin film transistor (TFT) is opened, line n m row pixel lists
After primary area pixel electrode in member is first charged to identical voltage with time area's pixel electrode, the (n-1)th row pixel list is then carried out
Member scanning, correspond to line n pixel unit setting Reverse Turning Control thin film transistor (TFT) be connected to (n-1)th controlling grid scan line with it is right
It should be in the row control separated time that line n pixel unit is arranged so that the row control separated time for corresponding to the setting of line n pixel unit transmits
All third thin film transistor (TFT)s of high potential signal, line n pixel unit are opened, and the charge in line n m row pixel units is total
It enjoys capacitance and drags down time voltage of area's pixel electrode so that the voltage of secondary area's pixel electrode is less than the voltage of primary area pixel electrode；It is real
Colour cast compensation can be carried out in forward scan driving and reverse scan driving by having showed, and promote the display quality of liquid crystal display panel.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology
Other various corresponding change and deformations are made in design, and all these change and distortions should all belong to the appended right of the present invention
It is required that protection domain.
Claims (5)
1. a kind of pixel-driving circuit, which is characterized in that include multiple pixel units (5) arranged in array, from top to bottom
The horizontally extending nth bar controlling grid scan line (G (n)) of corresponding line n pixel unit (5) setting corresponds to from left to right
The m data lines (D (m)) that vertically extend of m row pixel unit (5) setting, one article vertically extend
First controlling bus (10), second controlling bus (20) vertically extended, corresponding each row pixel unit (5) are respectively
The forward direction control that the horizontally extending row being arranged controls separated time (40), corresponding each row pixel unit (5) is respectively set is thin
The Reverse Turning Control thin film transistor (TFT) (T6) that film transistor (T5) and corresponding each row pixel unit (5) are respectively set, n are with m
Positive integer；
Each pixel unit (5) includes first film transistor (T1), the second thin film transistor (TFT) (T2), third thin film transistor (TFT)
(T3), primary area pixel electrode (51), secondary area's pixel electrode (52) and charge share capacitance (C1)；For line n m row pixels
Unit (5), the grid of the first film transistor (T1) is electrically connected nth bar controlling grid scan line (G (n)), source electrode electrically connects
Connect m data lines (D (m)), drain electrode is electrically connected primary area pixel electrode (51), the grid of second thin film transistor (TFT) (T2)
It is electrically connected nth bar controlling grid scan line (G (n)), source electrode is electrically connected m data lines (D (m)), drain electrode is electrically connected time area
Pixel electrode (52), the grid of the third thin film transistor (TFT) (T3), which is electrically connected, corresponds to line n pixel unit (5) setting
Row control separated time (40), source electrode are electrically connected time area's pixel electrode (52), drain electrode is electrically connected charge shares capacitance (C1) one
End, charge share the other end access common voltage of capacitance (C1)；
For line n pixel unit (5), the grid of the positive control thin film transistor (TFT) (T5) is electrically connected the first controlling bus
(10), source electrode is electrically connected (n+1)th controlling grid scan line (G (n+1)) corresponding to next line pixel unit (5), and drain electrode is electrical
Connection corresponds to the row control separated time (40) of line n pixel unit (5) setting, the grid of the Reverse Turning Control thin film transistor (TFT) (T6)
Pole is electrically connected the second controlling bus (20), source electrode electric connection is swept corresponding to (n-1)th grid of lastrow pixel unit (5)
Line (G (n-1)) is retouched, drain electrode is electrically connected the row control separated time (40) for corresponding to line n pixel unit (5) setting；
When forward scan, first controlling bus (10) provides high potential, and the second controlling bus (20) provides low potential；Reversely
When scanning, first controlling bus (10) provides low potential, and the second controlling bus (20) provides high potential；
When forward scan, the positive control thin film transistor (TFT) (T5) is opened；When forward scan is to line n pixel unit (5),
Nth bar controlling grid scan line (G (n)) transmits high potential signal, all first film transistors (T1) of line n pixel unit (5)
It is opened with the second thin film transistor (TFT) (T2), third thin film transistor (TFT) (T3) is closed, the master in line n m row pixel unit (5)
Area's pixel electrode (51) is charged to identical voltage with time area's pixel electrode (52)；When forward scan to the (n+1)th row pixel list
When first (5), (n+1)th controlling grid scan line (G (n+1)) transmission high potential signal, all the first of the (n+1)th row pixel unit (5)
Thin film transistor (TFT) (T1) is opened with the second thin film transistor (TFT) (T2) to primary area pixel electrode (51) and time area's pixel electrode (52)
While charging, the positive control thin film transistor (TFT) (T5) for corresponding to line n pixel unit (5) setting is connected to (n+1)th grid
Scan line (G (n+1)) and the row control separated time (40) corresponding to line n pixel unit (5) setting so that correspond to line n picture
The row control separated time (40) of plain unit (5) setting transmits high potential signal, and all third films of line n pixel unit (5) are brilliant
Body pipe (T3) is opened, and the charge in line n m row pixel unit (5) shares capacitance (C1) and drags down time area's pixel electrode (52)
Voltage so that the voltage of secondary area's pixel electrode (52) is less than the voltage of primary area pixel electrode (51)；
When reverse scan, the Reverse Turning Control thin film transistor (TFT) (T6) is opened；When reverse scan is to line n pixel unit (5),
Nth bar controlling grid scan line (G (n)) transmits high potential signal, all first film transistors (T1) of line n pixel unit (5)
It is opened with the second thin film transistor (TFT) (T2), third thin film transistor (TFT) (T3) is closed, the master in line n m row pixel unit (5)
Area's pixel electrode (51) is charged to identical voltage with time area's pixel electrode (52)；When reverse scan to the (n-1)th row pixel list
When first (5), (n-1)th controlling grid scan line (G (n-1)) transmission high potential signal, all the first of the (n-1)th row pixel unit (5)
Thin film transistor (TFT) (T1) is opened with the second thin film transistor (TFT) (T2) to primary area pixel electrode (51) and time area's pixel electrode (52)
While charging, the Reverse Turning Control thin film transistor (TFT) (T6) for corresponding to line n pixel unit (5) setting is connected to (n-1)th grid
Scan line (G (n-1)) and the row control separated time (40) corresponding to line n pixel unit (5) setting so that correspond to line n picture
The row control separated time (40) of plain unit (5) setting transmits high potential signal, and all third films of line n pixel unit (5) are brilliant
Body pipe (T3) is opened, and the charge in line n m row pixel unit (5) shares capacitance (C1) and drags down time area's pixel electrode (52)
Voltage so that the voltage of secondary area's pixel electrode (52) is less than the voltage of primary area pixel electrode (51).
2. pixel-driving circuit as described in claim 1, which is characterized in that the primary area pixel electrode (51) and time area's pixel
Electrode (52) is " rice " font structure, and material is ITO.
3. a kind of array substrate, which is characterized in that it includes being arranged in array to have pixel-driving circuit, the pixel-driving circuit
Multiple pixel units (5) of cloth, the horizontally extending nth bar grid for corresponding to line n pixel unit (5) setting from top to bottom
Pole scan line (G (n)), the m data lines vertically extended for corresponding to m row pixel unit (5) setting from left to right
(D (m)), first controlling bus (10) vertically extended, second controlling bus vertically extended
(20), the horizontally extending row that corresponding each row pixel unit (5) is respectively set controls separated time (40), corresponding each row pixel
The positive control thin film transistor (TFT) (T5) and corresponding each row pixel unit (5) that unit (5) is respectively set are respectively set reversed
Thin film transistor (TFT) (T6) is controlled, n and m is positive integer；
Each pixel unit (5) includes first film transistor (T1), the second thin film transistor (TFT) (T2), third thin film transistor (TFT)
(T3), primary area pixel electrode (51), secondary area's pixel electrode (52) and charge share capacitance (C1)；For line n m row pixels
Unit (5), the grid of the first film transistor (T1) is electrically connected nth bar controlling grid scan line (G (n)), source electrode electrically connects
Connect m data lines (D (m)), drain electrode is electrically connected primary area pixel electrode (51), the grid of second thin film transistor (TFT) (T2)
It is electrically connected nth bar controlling grid scan line (G (n)), source electrode is electrically connected m data lines (D (m)), drain electrode is electrically connected time area
Pixel electrode (52), the grid of the third thin film transistor (TFT) (T3), which is electrically connected, corresponds to line n pixel unit (5) setting
Row control separated time (40), source electrode are electrically connected time area's pixel electrode (52), drain electrode is electrically connected charge shares capacitance (C1) one
End, charge share the other end access common voltage of capacitance (C1)；
For line n pixel unit (5), the grid of the positive control thin film transistor (TFT) (T5) is electrically connected the first controlling bus
(10), source electrode is electrically connected (n+1)th controlling grid scan line (G (n+1)) corresponding to next line pixel unit (5), and drain electrode is electrical
Connection corresponds to the row control separated time (40) of line n pixel unit (5) setting, the grid of the Reverse Turning Control thin film transistor (TFT) (T6)
Pole is electrically connected the second controlling bus (20), source electrode electric connection is swept corresponding to (n-1)th grid of lastrow pixel unit (5)
Line (G (n-1)) is retouched, drain electrode is electrically connected the row control separated time (40) for corresponding to line n pixel unit (5) setting；
When forward scan, first controlling bus (10) provides high potential, and the second controlling bus (20) provides low potential；Reversely
When scanning, first controlling bus (10) provides low potential, and the second controlling bus (20) provides high potential；
When forward scan, the positive control thin film transistor (TFT) (T5) is opened；When forward scan is to line n pixel unit (5),
Nth bar controlling grid scan line (G (n)) transmits high potential signal, all first film transistors (T1) of line n pixel unit (5)
It is opened with the second thin film transistor (TFT) (T2), third thin film transistor (TFT) (T3) is closed, the master in line n m row pixel unit (5)
Area's pixel electrode (51) is charged to identical voltage with time area's pixel electrode (52)；When forward scan to the (n+1)th row pixel list
When first (5), (n+1)th controlling grid scan line (G (n+1)) transmission high potential signal, all the first of the (n+1)th row pixel unit (5)
Thin film transistor (TFT) (T1) is opened with the second thin film transistor (TFT) (T2) to primary area pixel electrode (51) and time area's pixel electrode (52)
While charging, the positive control thin film transistor (TFT) (T5) for corresponding to line n pixel unit (5) setting is connected to (n+1)th grid
Scan line (G (n+1)) and the row control separated time (40) corresponding to line n pixel unit (5) setting so that correspond to line n picture
The row control separated time (40) of plain unit (5) setting transmits high potential signal, and all third films of line n pixel unit (5) are brilliant
Body pipe (T3) is opened, and the charge in line n m row pixel unit (5) shares capacitance (C1) and drags down time area's pixel electrode (52)
Voltage so that the voltage of secondary area's pixel electrode (52) is less than the voltage of primary area pixel electrode (51)；
When reverse scan, the Reverse Turning Control thin film transistor (TFT) (T6) is opened；When reverse scan is to line n pixel unit (5),
Nth bar controlling grid scan line (G (n)) transmits high potential signal, all first film transistors (T1) of line n pixel unit (5)
It is opened with the second thin film transistor (TFT) (T2), third thin film transistor (TFT) (T3) is closed, the master in line n m row pixel unit (5)
Area's pixel electrode (51) is charged to identical voltage with time area's pixel electrode (52)；When reverse scan to the (n-1)th row pixel list
When first (5), (n-1)th controlling grid scan line (G (n-1)) transmission high potential signal, all the first of the (n-1)th row pixel unit (5)
Thin film transistor (TFT) (T1) is opened with the second thin film transistor (TFT) (T2) to primary area pixel electrode (51) and time area's pixel electrode (52)
While charging, the Reverse Turning Control thin film transistor (TFT) (T6) for corresponding to line n pixel unit (5) setting is connected to (n-1)th grid
Scan line (G (n-1)) and the row control separated time (40) corresponding to line n pixel unit (5) setting so that correspond to line n picture
The row control separated time (40) of plain unit (5) setting transmits high potential signal, and all third films of line n pixel unit (5) are brilliant
Body pipe (T3) is opened, and the charge in line n m row pixel unit (5) shares capacitance (C1) and drags down time area's pixel electrode (52)
Voltage so that the voltage of secondary area's pixel electrode (52) is less than the voltage of primary area pixel electrode (51).
4. array substrate as claimed in claim 3, which is characterized in that the primary area pixel electrode (51) and time area's pixel electrode
(52) it is " rice " font structure, material is ITO.
5. a kind of liquid crystal display panel, which is characterized in that including be oppositely arranged array substrate (1), colored filter substrate (2) and
The PSVA liquid crystal layers (3) being configured between array substrate (1) and colored filter substrate (2)；The PSVA liquid crystal layers (3) include
Polymeric layer (31) and the liquid crystal (32) being scattered in the polymeric layer (31)；The array substrate (1) be claim 3 to
4 any one of them array substrates.
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| CN105609077B (en) * | 2016-01-28 | 2018-03-30 | 深圳市华星光电技术有限公司 | Pixel-driving circuit |
| CN105527737B (en) * | 2016-02-01 | 2019-01-22 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and its driving method |
| CN107068690B (en) * | 2017-03-10 | 2020-02-21 | 京东方科技集团股份有限公司 | Array substrate, pixel electrode charging method of array substrate and display device |
| CN107121862B (en) * | 2017-06-23 | 2020-04-10 | 深圳市华星光电技术有限公司 | Liquid crystal panel and driving display method thereof |
| CN107300815B (en) * | 2017-08-14 | 2020-06-05 | 深圳市华星光电技术有限公司 | Array substrate, liquid crystal display panel and dot inversion driving method thereof |
| CN107703690B (en) | 2017-09-26 | 2020-07-31 | 武汉华星光电技术有限公司 | Array substrate and display panel |
| CN107818770A (en) * | 2017-10-25 | 2018-03-20 | 惠科股份有限公司 | The drive device and method of display panel |
| CN108169969B (en) * | 2017-12-26 | 2020-09-18 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display panel |
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| CN103777423A (en) * | 2014-01-24 | 2014-05-07 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and pixel structure thereof |
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| CN103777423A (en) * | 2014-01-24 | 2014-05-07 | 深圳市华星光电技术有限公司 | Liquid crystal display panel and pixel structure thereof |
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