CN105262464B - Reduce the circuit and method that the retention time is established needed for chip input port - Google Patents
Reduce the circuit and method that the retention time is established needed for chip input port Download PDFInfo
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Abstract
The present invention relates to the circuit and method that the retention time is established needed for reduction chip input port, including differential receiver, single ended receiver, clock switch circuit, variable delay unit and input signal sample circuit, single ended receiver and variable delay unit are sequentially connected on signal path, differential receiver and clock switch circuit are sequentially connected and are located at clock path, the output terminal of clock switch circuit is connected with input signal sample circuit, further includes positive clock redundancy unit, reverse clock redundancy unit and decision circuitry.The present invention samples positive clock signal vclk and reverse clock vclk_n using the clk_latch of clock path and sampled result is carried out to judge the delay cell on automatic regulating signal path respectively.Solve the settling time of existing chip and the retention time is vulnerable to the technical problem of influence, the settling time and retention time that the present invention can be optimal with adjust automatically internal latency.
Description
Technical field
The present invention relates to semiconductor chip design field, and in particular to one kind, which reduces to establish needed for chip input port, to be kept
The circuit and method of time
Background technology
Computer and various electronic equipments are widely used in the various aspects of the modern life, to semiconductor chip demand
It is increasing.People are getting faster rate request, and chip clock is with regard to less and less, and system gives building for chip input port
The vertical and retention time is less and less.This just needs to design smaller foundation and the chip of retention time.
As shown in Figure 1, settling time (setup time) referred to before clock signal chip rising edge arrives, input letter
Number stablize the constant time, if settling time is inadequate, input signal cannot be properly received in this clock by chip；
Retention time (hold time) refers to that after clock signal chip rising edge arrives input signal is stablized constant
Time, if the retention time is inadequate, input signal cannot be equally properly received in this clock by chip.
As shown in Fig. 2, Modern High-Speed clock signal chip is usually all differential signal (vclk/vclk_n), and need to adopt
The input signal of sample is all single-ended signal (usually with certain reference potential vref multilevel iudges just).So so that reference potential
Shake, which occurs, for vref can cause input signal delay to change, so as to cause the retention time of establishing of chip needs to become
Change.As shown in figure 3, including differential receiver, single ended receiver, clock switch circuit, variable delay unit and sample circuit,
Single ended receiver and variable delay are located at signal path, and differential receiver and clock switch circuit are located at clock path.Difference connects
The input terminal for receiving device receives differential signal (vclk/vclk_n), and output clock signal clk_i enters in clock switch circuit output
Portion sampling clock clk_latch, sample circuit adopt input signal under the triggering of internal sampling clock clk_latch
Sample.Differential clock signal and single ended signal need different interior receivers, along with chip operating temperature, process industry with
And operating voltage etc. can all influence the settling time and retention time of chip.Variable delay unit is in product design or life
The production stage mixes up, and can not be automatically adjusted according to application.
The content of the invention
It is vulnerable to the technical problem of influence to solve the settling time of existing chip and retention time, the present invention provides
It is a kind of to reduce the circuit and method that the retention time is established needed for chip input port.
The technical solution of the present invention：
A kind of reduce establishes the circuit of retention time needed for chip input port, including differential receiver, single ended receiver,
Clock switch circuit, variable delay unit and input signal sample circuit, single ended receiver and variable delay unit connect successively
Connect on signal path, differential receiver and clock switch circuit are sequentially connected and are located at clock path, the clock switch
The output terminal of circuit is connected with input signal sample circuit, is in place of its special system：Further include positive clock redundancy unit, anti-
To clock redundancy unit and decision circuitry,
The forward direction clock redundancy unit be used to receive positive clock signal vclk and after delay adjusts
Sampled under the triggering of internal sample clock clk_latch, export sampled result clk_sig_o to decision circuitry；
The reversely clock redundancy unit is used to receive reverse clock signal vclk_n and after delay adjusts
Sampled under the triggering of internal sampling clock clk_latch, export sampled result clk_n_sig_o to decision circuitry；
The decision circuitry is according to the sampled result clk_sig_o and the same steps of sampled result clk_n_sig_o received
The reverse clock in variable delay unit and reverse clock redundancy unit in whole variable delay unit, positive clock redundancy unit
Variable delay unit, until sampled result clk_sig_o and sampled result clk_n_sig_o is overturn.
Above-mentioned forward direction clock redundancy unit includes sequentially connected positive clock single ended receiver, positive clock variable delay
Unit and positive clock sampling circuit, the input terminal of the forward direction clock single ended receiver receive positive clock signal vclk, just
To clock sampling circuit output sampled result clk_sig_o to decision circuitry, output terminal and the forward direction of the clock switch circuit
Clock sampling circuit connects.
Above-mentioned reversely clock redundancy unit includes sequentially connected reversely clock single ended receiver, reverse clock variable delay
Unit and reverse clock sampling circuit, the input terminal of the reversely clock single ended receiver receive reverse clock signal vclk_n,
Reverse clock sampling circuit output sampled result clk_n_sig_o is to decision circuitry；The output terminal of the clock switch circuit with
Reverse clock sampling circuit connection.
A kind of to reduce the circuit that the retention time is established needed for chip input port, it is characterized in that：Connect including difference
Receive device, single ended receiver, clock switch circuit, input signal sample circuit, clock variable delay unit, positive clock redundancy list
First, reverse clock redundancy unit and decision circuitry,
Single ended receiver and input signal sample circuit are sequentially connected and on signal paths, differential receiver, clock
Variable delay unit and clock switch circuit are sequentially connected and are located at clock path, the output terminal of the clock switch circuit with it is defeated
Enter signal sample circuit connection,
The forward direction clock redundancy unit is used under the triggering of internal sampling clock clk_latch to positive clock signal
Vclk is sampled, and exports sampled result clk_sig_o to decision circuitry；
The reversely clock redundancy unit is used under the triggering of internal sampling clock clk_latch to reverse clock signal
Vclk_n is sampled, and exports sampled result clk_n_sig_o to decision circuitry；
When the decision circuitry is adjusted according to the sampled result clk_sig_o and sampled result clk_n_sig_o received
Clock variable delay unit, until sampled result clk_sig_o and sampled result clk_n_sig_o changes.
Above-mentioned forward direction clock redundancy unit includes sequentially connected positive clock single ended receiver and positive clock sampling electricity
Road, the input terminal of the forward direction clock single ended receiver receive positive clock signal vclk, and positive clock sampling circuit output is adopted
Sample result clk_sig_o is connected to decision circuitry, the output terminal of the clock switch circuit with positive clock sampling circuit.
Above-mentioned reversely clock redundancy unit includes the sequentially connected reversely reverse clock sampling circuit of clock single ended receiver,
The input terminal of the reversely clock single ended receiver receives reverse clock signal vclk_n, reverse clock sampling circuit output sampling
As a result clk_n_sig_o is to decision circuitry；The output terminal of the clock switch circuit is connected with reverse clock sampling circuit.
Reduce the method that the retention time is established needed for chip input port, comprise the following steps：
1】By the variable delay of variable delay unit, positive clock variable delay unit and reverse clock variable delay unit
It is arranged to minimum value；
2】Power on sampling：
Positive clock signal vclk is received and is touched after delay adjusts in internal sampling clock clk_latch
Give and sampled, export sampled result clk_sig_o to decision circuitry；
Reverse clock signal vclk_n is received at the same time and after delay adjusts in internal sampling clock clk_
Sampled under the triggering of latch, export sampled result clk_n_sig_o to decision circuitry；
3】Judgement adjustment is carried out based on sampled result：
According to the sampled result clk_sig_o and sampled result clk_n_sig_o synchronous adjustment variable delay lists received
The reverse clock variable delay list in variable delay unit and reverse clock redundancy unit in member, positive clock redundancy unit
Member, until sampled result clk_sig_o and sampled result clk_n_sig_o is overturn.
Reduce the method that the retention time is established needed for chip input port, comprise the following steps：
1】The variable delay of clock variable delay unit is arranged to minimum value；
2】Power on sampling：
Positive clock signal vclk is received and is sampled under the triggering of internal sampling clock clk_latch,
Sampled result clk_sig_o is exported to decision circuitry；
Reverse clock signal vclk_n is received and is carried out under the triggering of internal sampling clock clk_latch at the same time
Sampling, exports sampled result clk_n_sig_o to decision circuitry；
3】Judgement adjustment is carried out based on sampled result：
According to receive sampled result clk_sig_o and sampled result clk_n_sig_o adjustment clock path in when
Clock variable delay unit, until sampled result clk_sig_o and sampled result clk_n_sig_o is overturn.
Advantage for present invention：
1st, the settling time and retention time that the present invention can be optimal with adjust automatically internal latency.
2nd, the present invention samples positive clock signal (vclk) and reverse clock respectively using the clk_latch of clock path
(vclk_n) sampled result is carried out judging the delay cell on automatic regulating signal path.Since the design of the present invention need not
System provides extra function (as long as having clock), and self-adjusting can be realized in chip power up can also be empty in chip
Realized under not busy state.
3rd, the present invention is another reduces the mode that the retention time is established needed for chip input port, when variable delay is placed on
On clock path, its added advantage is can to reduce the number of variable delay, so as to optimize the area of chip.
Brief description of the drawings
Fig. 1 is the definition procedure schematic diagram of settling time and retention time；
Fig. 2 is differential clocks to the settling time of single ended signal and the time diagram of retention time；
Fig. 3 is existing chip receiver and sample circuit structure diagram；
Fig. 4 reduces input port for the present invention to be needed to establish the interface circuit schematic diagram of retention time；
Fig. 5 is decision circuitry course of work schematic diagram；
Interface circuit schematic diagram of another variable delay of Fig. 6 present invention in clock path.
Embodiment
Positive clock signal (vclk) and reverse clock are sampled respectively using the clk_latch of clock path as shown in Figure 4
(vclk_n) sampled result is carried out judging the delay cell on automatic regulating signal path.Since the design of the present invention need not
System provides extra function (as long as having clock), and self-adjusting can be realized in chip power up can also be empty in chip
Realized under not busy state.
Concrete structure is embodied as：The circuit of retention time is established needed for a kind of reduction chip input port, including difference connects
Receive device, single ended receiver, clock switch circuit, variable delay unit and input signal sample circuit, single ended receiver and can
Become delay cell to be sequentially connected on signal path, differential receiver and clock switch circuit are sequentially connected and are located at clock road
Footpath, the output terminal of clock switch circuit are connected with input signal sample circuit, further include positive clock redundancy unit, reverse clock
Redundancy unit and decision circuitry, positive clock redundancy unit are used to receiving positive clock signal vclk and passing through delay tune
Sampled after whole under the triggering of internal sampling clock clk_latch, export sampled result clk_sig_o to decision circuitry；
Reverse clock redundancy unit be used to receive reverse clock signal vclk_n and after delay adjusts in internal sample when
Sampled under the triggering of clock clk_latch, export sampled result clk_n_sig_o to decision circuitry；Decision circuitry is according to connecing
Received sampled result clk_sig_o and sampled result clk_n_sig_o synchronous adjustments variable delay unit, positive clock redundancy
The reverse clock variable delay unit in variable delay unit and reverse clock redundancy unit in unit, until sampled result
Clk_sig_o and sampled result clk_n_sig_o change.
General forward direction clock redundancy unit includes sequentially connected positive clock single ended receiver, positive clock variable delay
Unit and positive clock sampling circuit, the input terminal of positive clock single ended receiver receives positive clock signal vclk, when positive
Clock sample circuit exports sampled result clk_sig_o to decision circuitry, the output terminal of clock switch circuit and positive clock sampling
Circuit connects.Reverse clock redundancy unit includes sequentially connected reversely clock single ended receiver, reverse clock variable delay list
First and reverse clock sampling circuit, the input terminal of the reversely clock single ended receiver receive reverse clock signal vclk_n, instead
To clock sampling circuit output sampled result clk_n_sig_o to decision circuitry；The output terminal of clock switch circuit with it is reverse when
Clock sample circuit connects.
Its course of work is：
1st, all signal receiver variable delays are set to minimum value；
2nd, variable delay is increased based on sampled result clk_sig_o/clk_n_sig_o, until sampled result changes,
As shown in Figure 5；
3rd, variable delay size when sampled result is overturn is set prolongs to variable on single ended signal path
Late
This ensures that input signal gives the settling time and retention time of very little in outside, inside also can be by exact
Sampling.So as to achieve the purpose that to reduce the foundation of chip input port needs and retention time.
Same Fig. 4 circuits are that variable delay is placed on signal path, we can also be placed on variable delay on clock road
On footpath, as shown in Figure 6.Its added advantage is can to reduce the number of variable delay, so as to optimize the area of chip.
Claims (8)
1. a kind of reduce establishes the circuit of retention time needed for chip input port, including differential receiver, single ended receiver, when
Clock on-off circuit, variable delay unit and input signal sample circuit, single ended receiver and variable delay unit are sequentially connected
On signal path, differential receiver and clock switch circuit are sequentially connected and are located at clock path, the clock switch electricity
The output terminal on road is connected with input signal sample circuit, it is characterised in that：It is superfluous to further include positive clock redundancy unit, reverse clock
Remaining unit and decision circuitry,
The forward direction clock redundancy unit is used to receive positive clock signal vclk and after delay adjusts in inside
Sampled under the triggering of sampling clock clk_latch, export sampled result clk_sig_o to decision circuitry；
The reversely clock redundancy unit be used to receive reverse clock signal vclk_n and after delay adjusts including
Sampled under the triggering of portion sampling clock clk_latch, export sampled result clk_n_sig_o to decision circuitry；
The decision circuitry can according to the sampled result clk_sig_o and sampled result clk_n_sig_o synchronous adjustments received
The reverse clock become in variable delay unit and reverse clock redundancy unit in delay cell, positive clock redundancy unit is variable
Delay cell, until sampled result clk_sig_o and sampled result clk_n_sig_o is overturn.
2. according to claim 1 reduce the circuit that the retention time is established needed for chip input port, it is characterised in that：Institute
Stating positive clock redundancy unit includes sequentially connected positive clock single ended receiver, positive clock variable delay unit and forward direction
Clock sampling circuit, the input terminal of the forward direction clock single ended receiver receive positive clock signal vclk, positive clock sampling
Circuit output sampled result clk_sig_o is to decision circuitry, the output terminal of the clock switch circuit and positive clock sampling electricity
Road connects.
3. according to claim 1 or 2 reduce the circuit that the retention time is established needed for chip input port, its feature exists
In：The reversely clock redundancy unit includes sequentially connected reversely clock single ended receiver, reverse clock variable delay unit
With reverse clock sampling circuit, the input terminal of the reversely clock single ended receiver receives reverse clock signal vclk_n, reversely
Clk_n_sig_o is to decision circuitry for clock sampling circuit output sampled result；The output terminal of the clock switch circuit with reversely
Clock sampling circuit connects.
4. a kind of reduce the circuit that the retention time is established needed for chip input port, it is characterised in that：Including differential receiver, list
End-receiver, clock switch circuit, input signal sample circuit, clock variable delay unit, positive clock redundancy unit, reversely
Clock redundancy unit and decision circuitry,
Single ended receiver and input signal sample circuit are sequentially connected and on signal path, differential receiver, clock are variable
Delay cell and clock switch circuit are sequentially connected and are located at clock path, and output terminal and the input of the clock switch circuit are believed
The connection of number sample circuit,
The forward direction clock redundancy unit is used under the triggering of internal sampling clock clk_latch to positive clock signal vclk
Sampled, export sampled result clk_sig_o to decision circuitry；
The reversely clock redundancy unit is used under the triggering of internal sampling clock clk_latch to reverse clock signal
Vclk_n is sampled, and exports sampled result clk_n_sig_o to decision circuitry；
The decision circuitry can according to sampled result clk_sig_o and sampled result clk_n_sig_o the adjustment clock received
Become delay cell, until sampled result clk_sig_o and sampled result clk_n_sig_o changes.
5. according to claim 4 reduce the circuit that the retention time is established needed for chip input port, it is characterised in that：Institute
Stating positive clock redundancy unit includes sequentially connected positive clock single ended receiver and positive clock sampling circuit, the forward direction
The input terminal of clock single ended receiver receives positive clock signal vclk, positive clock sampling circuit output sampled result clk_
Sig_o is connected to decision circuitry, the output terminal of the clock switch circuit with positive clock sampling circuit.
6. according to claim 4 or 5 reduce the circuit that the retention time is established needed for chip input port, its feature exists
In：The reversely clock redundancy unit includes the sequentially connected reversely reverse clock sampling circuit of clock single ended receiver, described
The input terminal of reverse clock single ended receiver receives reverse clock signal vclk_n, reverse clock sampling circuit output sampled result
Clk_n_sig_o is to decision circuitry；The output terminal of the clock switch circuit is connected with reverse clock sampling circuit.
7. the method for retention time is established needed for the reduction chip input port of any circuit based on claim 1-3,
Comprise the following steps：
1】The variable delay of variable delay unit, positive clock variable delay unit and reverse clock variable delay unit is set
For minimum value；
2】Power on sampling：
Positive clock signal vclk is received and after delay adjusts under the triggering of internal sampling clock clk_latch
Sampled, export sampled result clk_sig_o to decision circuitry；
Reverse clock signal vclk_n is received at the same time and after delay adjusts internal sampling clock clk_latch's
Sampled under triggering, export sampled result clk_n_sig_o to decision circuitry；
3】Judgement adjustment is carried out based on sampled result：
According to the sampled result clk_sig_o and sampled result clk_n_sig_o synchronous adjustments variable delay unit received, just
The reverse clock variable delay unit in variable delay unit and reverse clock redundancy unit into clock redundancy unit, until
Sampled result clk_sig_o and sampled result clk_n_sig_o are overturn.
8. the method for retention time is established according to needed for the reduction chip input port of any circuit of claim 4-6,
Comprise the following steps：
1】The variable delay of clock variable delay unit is arranged to minimum value；
2】Power on sampling：
Positive clock signal vclk is received and is sampled under the triggering of internal sampling clock clk_latch, is exported
Sampled result clk_sig_o is to decision circuitry；
Reverse clock signal vclk_n is received and is adopted under the triggering of internal sampling clock clk_latch at the same time
Sample, exports sampled result clk_n_sig_o to decision circuitry；
3】Judgement adjustment is carried out based on sampled result：
Clock in sampled result clk_sig_o and sampled result clk_n_sig_o the adjustment clock path received can
Become delay cell, until sampled result clk_sig_o and sampled result clk_n_sig_o is overturn.
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| CN201510785062.2A CN105262464B (en) | 2015-11-16 | 2015-11-16 | Reduce the circuit and method that the retention time is established needed for chip input port |
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| CN105262464B true CN105262464B (en) | 2018-05-08 |
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| CN110033819B (en) * | 2018-01-11 | 2021-03-09 | 中芯国际集成电路制造(上海)有限公司 | SRAM establishment holding time test circuit |
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| CN101996674A (en) * | 2009-08-19 | 2011-03-30 | 瑞萨电子株式会社 | Input interface circuit |
| CN102081965A (en) * | 2011-02-21 | 2011-06-01 | 西安华芯半导体有限公司 | Circuit for generating inner write clock of dynamic random access memory (DRAM) |
| CN102148616A (en) * | 2011-03-31 | 2011-08-10 | 山东华芯半导体有限公司 | Method and system for preventing error locking of DLL (Delay-Locked Loop) |
| CN202488431U (en) * | 2012-03-28 | 2012-10-10 | 北京昆腾微电子有限公司 | Device achieving data synchronization |
| CN205179007U (en) * | 2015-11-16 | 2016-04-20 | 西安紫光国芯半导体有限公司 | Reduce required hold time's of foundation of chip input port circuit |
-
2015
- 2015-11-16 CN CN201510785062.2A patent/CN105262464B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6028816A (en) * | 1996-09-17 | 2000-02-22 | Fujitsu Limited | System configured of synchronous semiconductor device for adjusting timing of each input and semiconductor device used therefor |
| CN101996674A (en) * | 2009-08-19 | 2011-03-30 | 瑞萨电子株式会社 | Input interface circuit |
| CN102081965A (en) * | 2011-02-21 | 2011-06-01 | 西安华芯半导体有限公司 | Circuit for generating inner write clock of dynamic random access memory (DRAM) |
| CN102148616A (en) * | 2011-03-31 | 2011-08-10 | 山东华芯半导体有限公司 | Method and system for preventing error locking of DLL (Delay-Locked Loop) |
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| CN205179007U (en) * | 2015-11-16 | 2016-04-20 | 西安紫光国芯半导体有限公司 | Reduce required hold time's of foundation of chip input port circuit |
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