CN105261618B - Nonvolatile storage location - Google Patents
Nonvolatile storage location Download PDFInfo
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- CN105261618B CN105261618B CN201410240483.2A CN201410240483A CN105261618B CN 105261618 B CN105261618 B CN 105261618B CN 201410240483 A CN201410240483 A CN 201410240483A CN 105261618 B CN105261618 B CN 105261618B
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Abstract
The invention discloses a kind of nonvolatile storage locations, including coupling assembly, first choice transistor, the second selection transistor, the first Floating gate transistor and the second Floating gate transistor.Coupling assembly is formed in the first conductive region.First choice transistor is concatenated with the first Floating gate transistor and the second selection transistor, and first choice transistor, the first Floating gate transistor and the second selection transistor are formed in the second conductive region.Second Floating gate transistor is to be formed in third conductive region, and the first conductive region, the second conductive region and third conductive region are formed in the 4th conductive region.First conductive region, the second conductive region and third conductive region are well, and the 4th conductive region is deep-well.
Description
Technical field
The present invention relates to one kind, and memory cell can be repeatedly written, and especially one kind is based on logic control and can be with one
As Complementary MOS processing procedure compatibility, memory cell can repeatedly be written.
Background technology
As various different circuit unit is often integrated into single integrated circuit, by non-volatility memorizer list
The demand that member is integrated with logic circuit unit also more becomes important.However required for many nonvolatile storage locations are on processing procedure
Stack framework be not compatible with traditional logic gate processing procedure, such as：Only single polycrystalline silicon layer and without special charge fall into
Enter the manufacture of semiconductor of framework.
U.S. Patent number 7,382,658 (hereinafter ' 658), 7,391,647 (hereinafter ' 647), 7,263,001
(hereinafter ' 001), 7,423,903 (hereinafter ' 903), 7,209,392 (hereinafter ' 392) describe different deposit
Storage unit framework, ' 658 describe a kind of p-type access transistor for sharing Floating gate with N-type metal-oxide-semiconductor (MOS) capacitance.
' 647 teach a kind of p-type access transistor with half capacitance of half capacitance of p-type gold oxygen and N-type gold oxygen.' 001 teaches one kind
The p-type access transistor of Floating gate is shared with two half capacitances of p-type gold oxygen.' 903 teach one kind to via channel thermoelectricity
Sub- beam is written the p type field effect transistor of content and a kind of being imitated via the tunneling N-type field come content of erasing of Memory windows
Transistor.' 392 teach a kind of N-type metal-oxide half field effect transistor for sharing Floating gate with p-type metal-oxide half field effect transistor,
Wherein each transistor is all mutually coupled with respective access transistor.
Referring to FIG. 1, the schematic diagram for the nonvolatile storage location that Fig. 1 is introduced for ' 392.It is non-volatile in Fig. 1
Memory cell includes the first p-type MOS transistor T1, the second p-type MOS transistor T2, the first N-type MOS transistor
T3And the second N-type MOS transistor T4.First p-type MOS transistor T1With the first N-type MOS transistor T3It is by controlling
Voltage VSGIt is controlled, to respectively as the second p-type MOS transistor T2With the second N-type MOS transistor T4Access it is brilliant
Body pipe.First p-type MOS transistor T1Input terminal and the first N-type MOS transistor T3Input terminal receive selection line electricity
Press VSL, and the second p-type MOS transistor T2Input terminal and the second N-type MOS transistor T4Input terminal then receive respectively
First bitline voltage VBL1And the second bitline voltage VBL2.Second N-type MOS transistor T4With the second p-type gold oxygen semi-crystal
Pipe T2Shared Floating gate.
Invention content
One embodiment of the invention provides a kind of nonvolatile storage location.Nonvolatile storage location includes coupling
Component, first choice transistor, the second selection transistor, the first Floating gate transistor and the second Floating gate transistor.Coupling
Seaming element is formed in the first conductive region.First choice transistor is brilliant with the first Floating gate transistor and the second selection
Body pipe concatenates, and first choice transistor, the first Floating gate transistor and the second selection transistor are in the second conductive region
Interior formation.Second Floating gate transistor be formed in third conductive region, and the first conductive region, the second conductive region and
Third conductive region is formed in the 4th conductive region.The grid of first Floating gate transistor, the second Floating gate crystal
The grid of pipe and the electrode of coupling assembly are all the single Floating gates being formed by polysilicon.First conductive region, the second conduction
Region and third conductive region are well, and the 4th conductive region is deep-well, and third conductive region around the first conductive region and
Second conductive region.
Description of the drawings
Fig. 1 is the schematic diagram of the nonvolatile storage location of the prior art.
Fig. 2 is the schematic diagram of the nonvolatile storage location of one embodiment of the invention.
Fig. 3 is the line map of Fig. 2 nonvolatile storage locations.
Fig. 4 illustrates the write-in of Fig. 2 and Fig. 3 nonvolatile storage locations in one embodiment of the invention, erases, reads, prohibiting
The voltage arrangement being only written.
Fig. 5 is the oscillogram for forbidding write operation of Fig. 2 and Fig. 3 nonvolatile storage locations.
Fig. 6 is the schematic diagram of the nonvolatile storage location of another embodiment of the present invention.
Fig. 7 is the line map of Fig. 6 nonvolatile storage locations.
Fig. 8 illustrate the write-in of Fig. 6 and Fig. 7 nonvolatile storage locations in another embodiment of the present invention, erase, read,
Forbid the voltage arrangement of write-in.
Fig. 9 is the oscillogram for forbidding write operation of Fig. 6 and Fig. 7 nonvolatile storage locations.
Figure 10 is the schematic diagram of the nonvolatile storage location of another embodiment of the present invention.
Figure 11 is the line map of Figure 10 nonvolatile storage locations.
Figure 12 A-12D are Figure 10 nonvolatile storage locations respectively along straight line A-A ', B-B ', C-C ' and D-D ' cuttings
Sectional view.
Figure 13 illustrates the write-in of Figure 10 and Figure 11 nonvolatile storage locations in another embodiment of the present invention, erases, reads
Take, forbid the voltage arrangement of write-in.
Figure 14 is the oscillogram for forbidding write operation of Figure 10 and Figure 11 nonvolatile storage locations.
Wherein, the reference numerals are as follows：
T1First p-type MOS transistor
T2Second p-type MOS transistor
T3First N-type MOS transistor
T4Second N-type MOS transistor
NMOS N-type MOS transistors
PMOS p-type MOS transistors
VSGControl voltage
VSLSelect line voltage
VBL1First bitline voltage
VBL2Second bitline voltage
40,90,110 nonvolatile storage location
400,900,1100, FG Floating gates
401,901,1101 first grid portion
402,902,1102 second grid portion
421,921,1,121 first diffusion region
422,922,1,122 second diffusion region
461,961,1161 third diffusion region
462,962,1162 the 4th diffusion region
463,963,1163 the 5th diffusion region
464,964,1164 the 6th diffusion region
481,981,1181 the 7th diffusion region
482,982,1182 the 8th diffusion region
471,971,1171, WL character lines
472,972,1172, SG grid selection lines
CL control lines
SL source electrode lines
BL bit lines
EL erases line
NW, 930 wellblocks N
PW, the wellblock PW1, PW2, PW3 P
500,1000,1200 coupling assembly
510 first N-type MOS transistors
520 p-type MOS transistors
530 second N-type MOS transistors
540 third N-type MOS transistors
The first time points of t1
The second time points of t2
T3 third time points
The 4th time points of t4
The 5th time points of t5
The 6th time points of t6
V1 first voltages
V2 second voltages
V3 tertiary voltages
The 4th voltages of V4
The 5th voltages of V5
The 6th voltages of V6
1010,1,210 first Floating gate transistor
1020,1,220 second Floating gate transistor
1030,1230 first choice transistor
1040,1,240 second selection transistor
1130, DNW N-types deep-well area
120 P-type substrates
AA ', BB ', CC ', DD ' straight lines
STI shallow channel isolation layers
Specific implementation mode
It please refers to Fig.2 and Fig. 3.Fig. 2 is the schematic diagram of the nonvolatile storage location 40 of the embodiment of the present invention, non-volatile
Property memory cell 40 when its neighbor memory cell is written, have it is stronger forbid write-in ability.Fig. 3, which is that Fig. 2 is non-, to be waved
The line map of hair property memory cell 40.The nonvolatile storage location 40 of Fig. 2 can be formed in substrate or in substrate, and this
Substrate can be p-type or N-type.Nonvolatile storage location 40 includes Floating gate (FG) 400, character line (WL) 471, grid choosing
Line (SG) 472, control line (CL), source electrode line (SL), bit line (BL) and line of erasing (EL) are selected, and through grid selection line (SG)
472 use come enhance it is aforementioned forbid write-in ability.For using P-type substrate, nonvolatile storage location 40 can be another
Including the first diffusion region 421 and the second diffusion region 422, the first diffusion region 421 and the second diffusion region 422 are in the first conduction
Property the first conductive region on formed, such as the wellblocks N.Third diffusion region 461, the 4th diffusion region 462, the 5th diffusion region 463 and
6th diffusion region 464 can be formed on the second conductive region with the second electric conductivity, such as the wellblocks P.7th diffusion region 481 and
8th diffusion region 482 can be formed on the third conductive region with the first electric conductivity, such as another wellblocks N.Second conductive region
It may be disposed between the first conductive region and third conductive region, i.e., the wellblocks P are may be disposed between two wellblocks N.Yu Benfa
Bright another embodiment, the first conductive region are for the second electric conductivity, and third conductive region is disposed on the first conductive region
And second between conductive region.Floating gate (FG) 400 may include first grid portion 401 and second grid portion 402.First part
It is formed between the first diffusion region 421 and the second diffusion region 422, and second grid portion 402 is formed at the 4th diffusion region 462
And the 5th between diffusion region 463, and extend between the 7th diffusion region 481 and the 8th diffusion region 482.401 He of first grid portion
Second grid portion 402 can be that the polysilicon of same layer is constituted, and can be connected with each other.The area in first grid portion 401 is compared with second
The area of gate portion 402 is big.Character line (WL) 471 and grid selection line (SG) 472 can by with 400 same layer of Floating gate (FG)
Polysilicon forms.Character line (WL) 471 can be formed between third diffusion region 461 and the 4th diffusion region 462, and grid selects
Line (SG) 472 can be formed between the 5th diffusion region 463 and the 6th diffusion region 464.First diffusion region 421 and the second diffusion region
422 can be the diffusion regions N+.Third diffusion region 461, the 4th diffusion region 462, the 5th diffusion region 463 and the 6th diffusion region 464 can be N
+ diffusion region.7th diffusion region 481 and the 8th diffusion region 482 can be the diffusion regions P+.Nonvolatile storage location 40 can utilize single
The complementary oxo half processing procedure of layer polysilicon manufactures.
It please refers to Fig.2 and Fig. 3.Coupling assembly 500 can be the golden oxygen that is made of first grid portion 401 and control line (CL)
Half capacitance or metal-oxide half field effect transistor.Second grid portion 402 can be all the diffusion regions N+ the 4th diffusion region 462 and the 5th expand
Dissipate area 463 and collectively constitute the first N-type MOS transistor 510, and with 482 common groups of the 7th diffusion region 481 and the 8th diffusion region
At p-type MOS transistor 520.Character line (WL) 471 can be with the third diffusion region 461 and the 4th diffusion region that are all the diffusion regions N+
462 collectively constitute the second N-type MOS transistor 530, and grid selection line (SG) 472 can be with the 5th diffusion that is all the diffusion regions N+
Area 463 and the 6th diffusion region 464 collectively constitute third N-type MOS transistor 540.Source electrode line (SL) can be with third diffusion region
461 electrical connections, third diffusion region 461 can be the source electrode of the second N-type MOS transistor 530.Bit line (BL) can expand with the 6th
It dissipates area 464 to be electrically connected, the 6th diffusion region 464 can be the drain of third N-type MOS transistor 540.Erasing line (EL) can be with p-type
7th diffusion region 481 of MOS transistor 520 and the electrical connection of the 8th diffusion region 482.4th diffusion region 462 can be used as the simultaneously
The drain of the source electrode of one N-type MOS transistor 510 and the second N-type MOS transistor 530.5th diffusion region 463 can be simultaneously
As the drain of the first N-type MOS transistor 510 and the source electrode of third N-type MOS transistor 540.First N-type gold oxygen half
Transistor 510 and p-type MOS transistor 520 can be respectively as the first Floating gate transistor and the second Floating gate crystal
Pipe, and the second N-type MOS transistor 530 and third N-type MOS transistor 540 can respectively as first choice transistor and
Second selection transistor.In another embodiment of the present invention, the second Floating gate transistor can be made of half capacitance of golden oxygen.
Fig. 4 illustrates in one embodiment of the invention Fig. 2 and Fig. 3 nonvolatile storage locations 40 in being written, erase, read
Voltage arrangement when taking, forbidding write operation.When write operation, in can be bestowed on control line (CL) and line of erasing (EL) between
Line voltage is controlled between 5 volts to 20 volts of range.In that can bestow the first control voltage in grid selection line (SG), first controls
Voltage processed can be between 1 volt to 5 volts of range.Source electrode line (SL), bit line (BL) and the wellblocks P (PW) can be ground connection.
Character line (WL) can be between the range between 0 volt to 5 volts.In the case where the voltage of above-mentioned write operation arranges, line voltage is controlled
Can via half capacitance 500 of golden oxygen and according to the area ratio of half capacitance of golden oxygen and the first N-type MOS transistor 510 come with suspension joint
400 phase of grid couples.For example, if control line voltage is 6 volts and golden half capacitance of oxygen and the first N-type MOS transistor
510 area ratio is 9:1, then the current potential of Floating gate 400 is 5.4 volts (9/10ths of 6 volts).In write operation
When, electronics tunneling injection can occur for the first N-type MOS transistor 510.And when erasing operation, it is smeared when the voltage that will erase imposes on
Except line (EL), and control line (CL), source electrode line (SL), bit line (BL) and the wellblocks P (PW) be for ground connection when, p-type gold oxygen hemihedral crystal
The tunneling injection of electronics can occur for body pipe 520.Character line (WL) and grid selection line (SG) can be between 0 volt to 5 volts of ranges
Between, voltage of erasing can be between 5 volts to 20 volts of range.Thus, inject Floating gate when write operation
400 electronics can be when erasing operation from 400 tunneling injection of Floating gate.
When read operation, the first control voltage can be bestowed on control line (CL) and line of erasing (EL), in character line
(WL) and in grid selection line (SG) the second control voltage is bestowed, and in bestowing reading voltage on bit line (BL).Second control
Voltage and reading voltage can be between 1 volt to 5 volts of ranges.First control voltage can be between the model of 5 volts of 0 volt
Between enclosing.Source electrode line (SL) and the wellblocks P (PW) can be ground connection.Through the capacitive coupling with half capacitance of golden oxygen, the first of part
Voltage is controlled, such as 9/10ths the first control voltage will couple to Floating gate 400.If non-volatility memorizer 40 by
It erases, then the current potential of Floating gate 400 can be enough that the first N-type MOS transistor 510 is connected.It is applied to ratio due to reading voltage
On special line (BL) and source electrode line (SL) is ground connection, and the first N-type MOS transistor 510 can be flowed through by reading electric current.It is detectd at this time
The reading electric current measured is represented by high potential logic state.It is if non-volatility memorizer 40 has been written into, then floating by injection
Connecing the electronics of grid 400 can be enough to couple the first control voltage to the part of Floating gate 400 and offset, or at least in large quantities
It reduces, thus, which the first N-type MOS transistor 510 can maintain cut-off state, or only conduction ratio in non-volatile holographic storage
What device 40 may detect that when being erased reads the much smaller electric current of electric current.Being detected smaller reading electric current at this time can table
It is shown as low potential logic state.In another embodiment of the present invention, higher reading electric current also can be mapped to low potential logic
State, and lower reading electric current then can be mapped to high logic level.
Referring to FIG. 5, Fig. 5 is the oscillogram for forbidding write operation of Fig. 2 and Fig. 3 nonvolatile storage locations.Fig. 5's
Mode chart illustrates during forbidding write operation, imposes on the control line voltage of control line (CL), imposes on character line (WL)
Word line voltages impose on the grid selection line voltage in grid selection line (SG), impose on the line voltage of erasing on line of erasing (EL),
The bitline voltage on bit line (BL) is imposed on, the source line voltage on source electrode line (SL) is imposed on, imposes on the P wells of the wellblocks P (PW)
Area's voltage, and the channel voltage of the first N-type MOS transistor 510 that is lifted in third time point t3 and the 4th time point t4.
As shown in figure 5, in period from the second time point t2 to third time point t3, channel voltage is raised to the 6th voltage V6.From third
In the period of time point t3 to the 4th time point t4, control line voltage is for first voltage V1, and it is electric for second that grid, which select line voltage,
Press V2, line voltage of erasing is for tertiary voltage V3, and bitline voltage is for the 4th voltage V4, and channel voltage is for the 5th voltage
V5.During forbidding write operation, the magnitude relationship of first voltage V1 to the 6th voltage V6 be can be V1 >=V3>V5>V4≥V2>
V6.During write operation the magnitude relationship of first voltage V1 to the 6th voltage V6 be can be V1 >=V3 >=V2>V4=V5=V6
≥0V.For example, as shown in figure 4, during forbidding write operation, control line voltage can be between 5 volts to 20 volts
Between range, word line voltages can between 5 volts of 0 volt of range, grid select line voltage can between 1 volt 5
Between the range of volt, line voltage of erasing can be between 5 volts to 20 volts of range, and bitline voltage can be between 1 volt
To between 5 volts of ranges, source line voltage can be between 0 volt to 5 volts of range, and P trap zone voltages can be 0 volt
It is special.
Above-mentioned nonvolatile storage location 40 can be completely compatible with general complementary oxo half processing procedure, and only needs opposite
Good write-in and speed of erasing, durability and data keeping quality can be realized in small assembly layout area, and is stored without degenerating
The cycle-index of device.
Please refer to Fig. 6 and Fig. 7.Fig. 6 is the schematic diagram of the nonvolatile storage location 90 of another embodiment of the present invention, and
Fig. 7 is the line map of Fig. 6 nonvolatile storage locations 90.Nonvolatile storage location 90 includes Floating gate 900, character
Line (WL) 971, grid selection line (SG) 972, control line (CL), source electrode line (SL), bit line (BL) and line of erasing (EL), and can
Make it when neighbor memory cell is written using grid selection line (SG) 972, the function of write-in is forbidden in enhancing.With p-type (first
Electric conductivity) for substrate, also that is, nonvolatile storage location 90 is that (third with the second electric conductivity is led in the wellblocks N 930
Electric region) composition, and the wellblocks N 930 are formed in P-type substrate.Nonvolatile storage location 90 is additionally comprised in
The first diffusion region 921 and the second diffusion region 922 formed in the first conductive region (P wellblock PW1) of one electric conductivity.Third is spread
Area 961, the 4th diffusion region 962, the 5th diffusion region 963 and the 6th diffusion region 964 can be conductive in second with the first electric conductivity
It is formed in region (P wellblock PW2).7th diffusion region 981 and the 8th diffusion region 982 can be conductive in the with the first electric conductivity the 4th
It is formed in region (P wellblock PW3).Second conductive region (P wellblock PW2) may be disposed at the first conductive region (P wellblock PW1) and
Between four conductive regions (P wellblock PW3).Floating gate (FG) 900 includes first grid portion 901 and second grid portion 902.First
Gate portion 901 is to be formed between the first diffusion region 921 and the second diffusion region 922, and second grid portion 902 is in the 4th diffusion
It is formed, and is extended between the 7th diffusion region 981 and the 8th diffusion region 982 between area 962 and the 5th diffusion region 963.The first grid
Pole portion 901 and second grid portion 902 are to be made of the polysilicon of same layer, and can be connected with each other.The face in first grid portion 901
Product is big compared with the area in second grid portion 902.Character line (WL) 971 can between third diffusion region 961 and the 4th diffusion region 962 shape
At, and grid selection line (SG) 972 is formed between the 5th diffusion region 963 and the 6th diffusion region 964.First diffusion region 921
And second diffusion region 922 have the second electric conductivity.Third diffusion region 961, the 4th diffusion region 962, the 5th diffusion region 963 and the 6th
Diffusion region 964 also all has the second electric conductivity.7th diffusion region 981 and the 8th diffusion region 982 also all have the second electric conductivity.It is non-
Volatile storage unit 90 can be manufactured using the complementary oxo half processing procedure of single level polysilicon.In addition, in the another of the present invention
In one embodiment, the first electric conductivity is for N-type, and the second electric conductivity is then p-type.
Please refer to Fig. 6 and Fig. 7.Coupling assembly 1000 can be the gold that is made of first grid portion 901 and control line (CL)
Half capacitance of oxygen or metal-oxide half field effect transistor.It second grid portion 902 can be common with the 4th diffusion region 962 and the 5th diffusion region 963
Form the first Floating gate transistor 1010 (N-type MOS transistor), and with the 7th diffusion region 981 and the 8th diffusion region 982
Collectively constitute the second Floating gate transistor 1020 (N-type MOS transistor).Character line (WL) 971 can be with third diffusion region
961 and the 4th diffusion region 962 collectively constitute first choice transistor 1030 (N-type MOS transistor).Grid selection line (SG)
972 can collectively constitute 1040 (N-type gold oxygen semi-crystal of the second selection transistor with the 5th diffusion region 963 and the 6th diffusion region 964
Pipe).Source electrode line (SL) can be electrically connected with third diffusion region 961, and third diffusion region 961 can be first choice transistor 1030
Source electrode.Bit line BL can be electrically connected with the 6th diffusion region 964, and the 6th diffusion region 964 can be the second selection transistor 1040
Drain.Line (EL) of erasing can be electrically connected with the 7th diffusion region 981 of the second Floating gate transistor 1020 and the 8th diffusion region 982
It connects.It 4th diffusion region 962 can be simultaneously as the source electrode of the first Floating gate transistor 1010 and first choice transistor 1030
Drain.It 5th diffusion region 963 can be simultaneously as the drain of the first Floating gate transistor 1010 and the second selection transistor 1040
Source electrode.In another embodiment of the present invention, the second Floating gate transistor 1020 can be made of half capacitance of golden oxygen.
Fig. 8 illustrate in one embodiment of the invention Fig. 6 and Fig. 7 nonvolatile storage locations 90 in be written, erase, read,
Forbid voltage arrangement when write operation.When write operation, in applying between 5 volts to 20 volts of model on control line (CL)
Control line voltage between enclosing, in applying on the first conductive region (P wellblock PW1), the first well identical with control line voltage is electric
Pressure, source electrode line (SL), bit line (BL) and the second conductive region (P wellblock PW2) can be ground connection.Character line (WL) voltage can be between
Range between 0 volt to 5 volts.In erase line of the application between 5 volts to 20 volts of range on line of erasing (EL)
Voltage, in applying the 4th well voltage identical with line voltage of erasing on the 4th conductive region (P wellblock PW3), in grid selection line
(SG) grid applied between 1 volt to 5 volts selects line voltage.In addition, in the wellblocks N 930 (third conductive region)
Apply the third well voltage between 5 volts to 20 volts of range.In the case where the voltage of above-mentioned write operation arranges, control line
Voltage can via coupling assembly 1000 and according to the area ratio of coupling assembly 1000 and the first Floating gate transistor 1010 come
It is coupled with 900 phase of Floating gate.For example, if control line voltage is 10 volts and coupling assembly 1000 and Floating gate are brilliant
The area ratio of body pipe 1010 is 9:1, then the current potential of Floating gate 900 is 9 volts (9/10ths of 10 volts).In write-in
When operation, the first Floating gate transistor 1010 will produce electronics tunneling injection, and thus electronics can be via the first suspension joint
Gridistor 1010 injects Floating gate 900.
When erasing operation, in word line voltages of the application between 0 volt to 5 volts on character line (WL), and control
Line (CL), the first conductive region (P wellblock PW1), source electrode line (SL), bit line (BL) and the second conductive region (P wellblock PW2) processed
It is for ground connection.Line voltage is selected in the grid applied in grid selection line (SG) between 0 volt to 5 volts.In line of erasing
(EL) apply line voltage of erasing between 5 volts to 20 volts on, and in the 4th conductive region (P wellblock PW3) apply with
The 4th equal well voltage of line voltage of erasing.In addition, applying between 5 volts to 20 volts in the wellblocks N 930 (third conductive region)
Between third well voltage to avoid generate the first conductive region (P wellblock PW1), the second conductive region (P wellblock PW2) and the 4th
Forward bias voltage drop of the conductive region (P wellblock PW3) between the wellblocks N 930.When erasing operation, led in line of erasing (EL) and the 4th
Apply the voltage of erasing between 5 volts to 20 volts on electric region (P wellblock PW3), at this time the second Floating gate transistor
1020 will produce the tunneling injection of electronics.Thus, which the electronics being stored on Floating gate 900 can be worn from Floating gate 900
Tunnel projects.
When read operation, in applying the control line voltage between 0 volt to 5 volts on control line (CL), in word
The word line voltages applied on line (WL) between 1 volt to 5 volts are accorded with, in application in grid selection line (SG) between 1 volt
Spy selects line voltage to the grid between 5 volts, in applying the bit line between 1 volt to 5 volts on bit line (BL)
Voltage.In addition, applying the first well voltage identical with control line voltage in the first conductive region (P wellblock PW1).Source electrode line (SL)
And second conductive region (P wellblock PW2) can be ground connection.In application erasing between 0 volt to 5 volts on line of erasing (EL)
Line voltage, wherein the 4th well voltage for being applied to the 4th conductive region (P wellblock PW3) is identical as line voltage of erasing.In addition, in N
Wellblock 930 (third conductive region) applies the third well voltage between 0 volt to 5 volts to avoid the first conduction region is generated
Domain (P wellblock PW1), the second conductive region (P wellblock PW2) and the 4th conductive region (P wellblock PW3) are suitable between the wellblocks N 930
To bias.Through the capacitive coupling with coupling assembly 1000, part, such as 9/10ths, line voltage is controlled, will couple to floating
Connect grid 900.If non-volatility memorizer 90 has been erased, the current potential of Floating gate 900 can be enough that the first suspension joint grid are connected
Gated transistors 1010.Since bitline voltage is applied on bit line (BL) and source electrode line (SL) and the second conductive region (wellblocks P
PW2) it is all ground connection, the first Floating gate transistor 1010 can be flowed through by reading electric current.It is detected larger reading electricity at this time
Stream is represented by high potential logic state.If non-volatility memorizer 90 has been written into, then by the electricity of injection Floating gate 900
Son, which can be enough that line voltage (VCL) will be controlled, is coupled to the partial offset of Floating gate 900, or at least reduces in large quantities, such one
Come, the first Floating gate transistor 1010 can maintain cut-off state, or only conduction ratio has been smeared in non-volatility memorizer 90
Except when may detect that read the much smaller electric current of electric current.And it is detected smaller reading electric current at this time and is represented by low electricity
Position logic state.It is above-mentioned larger reading current judgement is high potential logic state and to be low by smaller reading current judgement
Current potential logic state be only one embodiment of the invention and not limiting the present invention.In other embodiment, larger reading
Obtaining current also can be mapped to low potential logic state, and smaller reading electric current then can be mapped to high logic level.
Referring to FIG. 9, Fig. 9 is the oscillogram for forbidding write operation of Fig. 6 and Fig. 7 nonvolatile storage locations 90.Fig. 9
Mode chart illustrate during forbidding write operation, impose on the control line voltage of control line (CL), impose on character line (WL)
Word line voltages, impose in grid selection line (SG) grid selection line voltage, impose on line of erasing (EL) erase line electricity
Pressure, imposes on the bitline voltage on bit line (BL), imposes on the source line voltage on source electrode line (SL), impose on the second conductive region
The second well voltage of (P wellblock PW2) imposes on the third well voltage of the wellblocks N 930, and from third time point t3 to the 4th time point t4
Period in be lifted the first Floating gate transistor 1010 channel voltage.Wherein impose on the first conductive region (P wellblock PW1)
The first well voltage it is equal with control line voltage, and impose on the 4th well voltage of the 4th conductive region (P wellblock PW3) and erase line
Voltage is equal.As shown in figure 9, in period from the second time point t2 to third time point t3, channel voltage has been lifted to the 6th voltage
V6.In from third time point t3 to the period of the 4th time point t4, control line voltage is for first voltage V1, and grid selection line voltage is
For second voltage V2, line voltage of erasing be for tertiary voltage V3, bitline voltage be for the 4th voltage V4, and channel voltage be for
5th voltage V5.During forbidding write operation, the magnitude relationship of first voltage V1 to the 6th voltage V6 be can be V1 >=V3>V5
>V4≥V2>V6.During write operation, the magnitude relationship of first voltage V1 to the 6th voltage V6 be can be V1 >=V3 >=V2>V4
=V5=V6 >=0V.For example, as shown in figure 8, during forbidding write operation, control line voltage can be between 5 volts extremely
Between 20 volts of range, word line voltages can be between 0 volt to 5 volts of range, and grid selects line voltage can be between 1
Volt is between 5 volts of range, and line voltage of erasing can be between 5 volts to 20 volts of range, and bitline voltage can be situated between
Between 1 volt to 5 volts of range, source line voltage can be between 0 volt to 5 volts of range, and the 4th well voltage can
Between 5 volts to 20 volts of range, and the second well voltage for imposing on the second conductive region (P wellblock PW2) can be 0 volt
It is special.
Referring to FIG. 6, although nonvolatile storage location 90 can be applicable in embedded system, because second leads
Electric region (P wellblock PW2) is disposed between the first conductive region (P wellblock PW1) and the 4th conductive region (P wellblock PW3), because
This nonvolatile storage location 90 also needs more chip area to reach set process design specification.
Please refer to Fig.1 0 and Figure 11.Figure 10 is the signal of the nonvolatile storage location 110 of another embodiment of the present invention
Figure, and the line map that Figure 11 is Figure 10 nonvolatile storage locations 110.The nonvolatile storage location 110 of Figure 10 includes
Floating gate (FG) 1100, character line (WL) 1171, grid selection line (SG) 1172, control line (CL), source electrode line (SL), bit
Line (BL) and line of erasing (EL), and through grid selection line (SG) 1172 so that it can increase when neighbor memory cell is written
The strong function of forbidding write-in.By taking p-type (the first electric conductivity) substrate 120 as an example, also that is, nonvolatile storage location 110 is in N
Composition in type deep well area 1130 (the 4th conductive region with the second electric conductivity), and N-type deep-well area 1130 is in P-type substrate
Composition in 120.Nonvolatile storage location 110 can be additionally comprised in the first conductive region (wellblocks P with the first electric conductivity
PW1 the first diffusion region 1121 and the second diffusion region 1122 formed on).Third diffusion region 1161, the 4th diffusion region the 1162, the 5th
Diffusion region 1163 and the 6th diffusion region 1164 can be formed on the second conductive region (P wellblock PW2) with the first electric conductivity.The
Seven diffusion regions 1181 and the 8th diffusion region 1182 can be formed on the third conductive region (N wellblock NW) with the second electric conductivity.
Third conductive region (N wellblock NW) is centered around the first conductive region (P wellblock PW1) and the second conductive region (P wellblock PW2) week
It encloses.Floating gate (FG) 1100 may include first grid portion 1101 and second grid portion 1102.First grid portion 1101 is in
It is formed between one diffusion region 1121 and the second diffusion region 1122, and second grid portion 1102 is in the 4th diffusion region 1162 and the 5th
It spreads and is formed between 1163rd area, and also between the 7th diffusion region 1181 and the 8th diffusion region 1182.First grid portion 1101
It is made of, and can be connected with each other the polysilicon of same layer with second grid portion 1102.The area in first grid portion 1101 compared with
The area in second grid portion 1102 is big.Character line (WL) 1171 and grid selection line (SG) 1172 can by with Floating gate (FG)
The polysilicon of 1100 same layers forms.Character line (WL) 1171 can between third diffusion region 1161 and the 4th diffusion region 1162 shape
At, and grid selection line (SG) 1172 can be formed between the 5th diffusion region 1163 and the 6th diffusion region 1164.First diffusion region
1121 and second diffusion region 1122 have the second electric conductivity.Third diffusion region 1161, the 4th diffusion region 1162, the 5th diffusion region
1163 and the 6th diffusion region 1164 also have the second electric conductivity.And the 7th diffusion region 1181 and the 8th diffusion region 1182 have first
Electric conductivity.Nonvolatile storage location 110 can be manufactured using the complementary oxo half processing procedure of single level polysilicon.And first leads
Can be electrically p-type, the second electric conductivity can be N-type.
Please refer to Fig.1 0 and Figure 11.Coupling assembly 1200 can be made of first grid portion 1101 and control line (CL)
Half capacitance of golden oxygen or metal-oxide half field effect transistor.It second grid portion 1102 can be with the 4th diffusion region 1162 and the 5th diffusion region 1163
The first Floating gate transistor 1210 (N-type MOS transistor) is collectively constituted, and can be expanded with the 7th diffusion region 1181 and the 8th
It dissipates area 1182 and collectively constitutes the second Floating gate transistor 1220 (p-type MOS transistor), and the second Floating gate transistor
1220 can be golden half capacitance of oxygen or metal-oxide half field effect transistor.In addition, as shown in figure 11, character line (WL) 1171 can expand with third
It dissipates 1161 and the 4th diffusion region 1162 of area and collectively constitutes first choice transistor 1230 (N-type MOS transistor).Grid selects
Line (SG) 1172 can collectively constitute the second selection transistor (N-type gold oxygen half with the 5th diffusion region 1163 and the 6th diffusion region 1164
Transistor) 1240.And the first Floating gate transistor 1210 is between first choice transistor 1230 and the second selection transistor
Between 1240.Source electrode line (SL) can be electrically connected with third diffusion region 1161, and third diffusion region 1161 can be used as first choice crystalline substance
The source electrode of body pipe 1230.Bit line (BL) can be electrically connected with the 6th diffusion region 1164, and the 6th diffusion region 1164 can be the second choosing
Select the drain of transistor 1240.Erasing line (EL) can be with the 7th diffusion region 1181 and the 8th of the second Floating gate transistor 1220
There is electrical connection in diffusion region 1182.4th diffusion region 1162 can simultaneously as the first Floating gate transistor 1210 source electrode and first
The drain of selection transistor 1230.It 5th diffusion region 1163 can be simultaneously as the drain of the first Floating gate transistor 1210 and
The source electrode of two selection transistors 1240.In another embodiment of the present invention, 1220 device of the second Floating gate transistor can be by
Half capacitance of golden oxygen is formed.
2A-12D is please referred to Fig.1, Figure 12 A-12D are Figure 10 nonvolatile storage locations 110 respectively along straight line A-A ', B-
B ', C-C ' and the sectional view of D-D ' cuttings.As shown in fig. s 12a through 12d, third conductive region (N wellblock NW) is around the first conduction region
Domain (P wellblock PW1) and the second conductive region (P wellblock PW2), and the first conductive region (P wellblock PW1), the second conductive region (P
Wellblock PW2) and third conductive region (N wellblock NW) be all to be formed in the 4th conductive region 1130.And the first conductive region (P
Wellblock PW1), the second conductive region (P wellblock PW2) and third conductive region (N wellblock NW) be well construction, and the 4th conductive region
1130 are constructed for deep-well.In addition, shallow channel isolation layer STI shown in Figure 12 A-12D is for shallow trench isolation (shallow
trench isolation)。
The write-in of Figure 13 definition graphs 10 and Figure 11 nonvolatile storage locations 110 erases, reads, forbidding write operation
When voltage arrangement.When write operation, apply the control line electricity between 5 volts to 20 volts of range in control line (CL)
Pressure applies the first well voltage identical with control line voltage, source electrode line (SL), bit line in the first conductive region (P wellblock PW1)
(BL) and the second conductive region (PW2) can be ground connection.Word line voltages can be between the range between 0 volt to 5 volts.In erasing
Line (EL) applies the line voltage of erasing between 5 volts to 20 volts of range, applies and smears in third conductive region (NW)
Except the identical third well voltage of line voltage, apply the grid selection line between 1 volt to 5 volts in grid selection line (SG)
Voltage.In addition, apply the 4th well voltage between 5 volts to 20 volts in N-type deep-well area 1130 (the 4th conductive region), with
It avoids generating the first conductive region (P wellblock PW1), the second conductive region (P wellblock PW2) or third conductive region and N-type deep-well
Forward bias voltage drop between area 1130.Under the arrangement of above-mentioned write-in voltage, control line voltage can be via coupling assembly 1200 and root
It is coupled with 1100 phase of Floating gate according to coupling assembly 1200 and the area ratio of the first Floating gate transistor 1210.Citing comes
It says, if control line voltage is 10 volts and the area ratio of coupling assembly 1200 and the first Floating gate transistor 1210 is 9:
1, then the current potential of Floating gate 1100 is 9 volts (9/10ths of 10 volts).When write operation, the first Floating gate is brilliant
Body pipe 1210 will produce electronics tunneling injection, and thus electronics can inject suspension joint via the first Floating gate transistor 1210
Grid 1100.
When erasing operation, in word line voltages of the application between 0 volt to 5 volts on character line (WL).Control
Line, the first conductive region (P wellblock PW1), source electrode line (SL), bit line (BL) and the second conductive region (P wellblock PW2) are to connect
Ground.Line voltage is selected in the grid applied in grid selection line (SG) between 0 volt to 5 volts.In on line of erasing (EL)
Apply the line voltage of erasing between 5 volts to 20 volts, and applies and line electricity of erasing in third conductive region (N wellblock NW)
Press equal third well voltage.In addition, in N-type deep-well area 1130 (the 4th conductive region) apply between 5 volts to 20 volts it
Between the 4th well voltage to avoid generate the first conductive region (P wellblock PW1), the second conductive region (P wellblock PW2) or third are led
Forward bias voltage drop between electric region and N-type deep-well area 1130.When erasing operation, when in line of erasing (EL) and third conductive region
On (N wellblock NW) apply erase voltage when, the tunneling injection of electronics can occur for the second Floating gate transistor 1220.Thus,
The electronics being stored on Floating gate 1100 can be projected from Floating gate 1100.
When read operation, in applying the control line voltage between 0 volt to 5 volts on control line (CL), in word
The word line voltages applied on line (WL) between 1 volt to 5 volts are accorded with, in application in grid selection line (SG) between 1 volt
Spy selects line voltage to the grid between 5 volts, in applying the bit line between 1 volt to 5 volts on bit line (BL)
Voltage, and apply the first well voltage identical with control line voltage in the first conductive region (P wellblock PW1).Source electrode line (SL) and
Second conductive region (P wellblock PW2) can be ground connection.In erase line of the application between 0 volt to 5 volts on line of erasing (EL)
Voltage, wherein the third well voltage for being applied to third conductive region (N wellblock NW) is identical as line voltage of erasing.In addition, in N-type depth
It is conductive to avoid generating first that wellblock 1130 (the 4th conductive region) applies the 4th well voltage between 0 volt to 5 volts
Between region (P wellblock PW1), the second conductive region (P wellblock PW2) or third conductive region and N-type deep-well area 1130 forward
Bias.Through the capacitive coupling with coupling assembly 1200, the control line voltage of part, such as 9/10ths control line voltage,
It will couple to Floating gate 1100.If non-volatility memorizer 110 has been erased, the current potential of Floating gate 1100 can be enough to lead
Logical first Floating gate transistor 1210.Since bitline voltage is applied on bit line (BL) and source electrode line (SL) and second is led
Electric region (P wellblock PW2) is all ground connection, and the first Floating gate transistor 1210 can be flowed through by reading electric current.The reading being detected
Obtaining current is represented by high potential logic state.If non-volatility memorizer 110 has been written into, then by injection Floating gate
1100 electronics can be enough that the partial offset that line voltage is coupled to Floating gate 1100 will be controlled, or at least reduce in large quantities, such as
This one, the first Floating gate transistor 1210 can maintain cut-off state, or can only conduction ratio in non-volatility memorizer 110
What be may detect that when being erased reads the much smaller electric current of electric current.And being detected smaller reading electric current at this time can indicate
For low potential logic state.It is above-mentioned to be high potential logic state by larger reading current judgement and by smaller reading current judgement be
Low potential logic state be only one embodiment of the invention and not limiting the present invention.It is larger in other embodiment
It reads electric current and also can be mapped to low potential logic state, and smaller reading electric current then can be mapped to high logic level.
Please refer to Fig.1 the waveform for forbidding write operation that 4, Figure 14 is Figure 10 and Figure 11 nonvolatile storage locations 110
Figure.The mode chart of Figure 14 illustrates during forbidding write operation, imposes on the control line voltage of control line (CL), imposes on character line
(WL) word line voltages on impose on the grid selection line voltage in grid selection line (SG), impose on smearing on line of erasing (EL)
Except line voltage, the bitline voltage on bit line (BL) is imposed on, imposes on the source line voltage on source electrode line (SL), second is imposed on and leads
Second well voltage of electric region (P wellblock PW2), imposes on the 4th well voltage in N-type deep-well area 1130, and third time point t3 extremely
The channel voltage for the first Floating gate transistor 1210 being lifted in 4th time point t4.Wherein impose on the first conductive region (wellblocks P
PW1 the first well voltage) is equal with control line voltage, and imposes on the third well voltage of third conductive region (N wellblock NW) and smear
Except line voltage is equal.As shown in figure 14, out of from the second time point t2 to third time point t3, channel voltage is raised to the 6th voltage V6.
Out of from third time point t3 to the 4th time point t4, control line voltage is for first voltage V1, and it is electric for second that grid, which select line voltage,
Press V2, line voltage of erasing is for tertiary voltage V3, and bitline voltage is for the 4th voltage V4, and channel voltage is for the 5th voltage
V5.During forbidding write operation, the magnitude relationship of first voltage V1 to the 6th voltage V6 be can be V1 >=V3>V5>V4≥V2>
V6.During write operation the magnitude relationship of first voltage V1 to the 6th voltage V6 be can be V1 >=V3 >=V2>V4=V5=V6
≥0V.For example, as shown in figure 14, during forbidding write operation, control line voltage can be between 5 volts to 20 volts
Between range, word line voltages can be between 5 volts of 0 volt of range, and grid selects line voltage can be between 1 volt to 5
Between the range of volt, line voltage of erasing can be between 5 volts to 20 volts of range, and bitline voltage can be between 1 volt
To between 5 volts of ranges, source line voltage can be between 0 volt to 5 volts of range, and the second well voltage can be 0 volt,
And the 4th well voltage can be between 5 volts to 20 volts of range.In addition, as shown in Figure 14 figures, third conductive region is imposed on
Leading the first well voltage (P wellblock PW1) for imposing on the first conductive region of the liter edge of the third well voltage of (N wellblock NW), and impose on
The drop edge of the third well voltage of third conductive region (N wellblock NW) falls behind the first well for imposing on the first conductive region (P wellblock PW1)
Voltage, therefore can avoid the first conductive region (P wellblock PW1) and the second conductive region (P wellblock PW2) and third conductive region (N
Wellblock NW) between forward bias voltage drop.
In conclusion the nonvolatile storage location of aforementioned present invention can be completely simultaneous with general complementary oxo half processing procedure
Hold, and only needs relatively small assembly layout area that good write-in and speed of erasing, durability and data guarantor can be realized
Sustainability, and without the cycle-index of degeneration memory.
The foregoing is only a preferred embodiment of the present invention, is not intended to restrict the invention, for the skill of this field
For art personnel, the invention may be variously modified and varied.All within the spirits and principles of the present invention, any made by repair
Change, equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of nonvolatile storage location, which is characterized in that include：
Coupling assembly is formed on the first conductive region；
First choice transistor is concatenated with the first Floating gate transistor and the second selection transistor, and wherein the first choice is brilliant
Body pipe, the first Floating gate transistor and second selection transistor are formed on the second conductive region；
Second Floating gate transistor, is formed on third conductive region, wherein first conductive region, second conductive region
And the third conductive region is formed in the 4th conductive region, and the grid of the first Floating gate transistor, this is second floating
The electrode of the grid and the coupling assembly that connect gridistor is the Floating gate formed by single-polysilicon；
Control line is electrically connected to the coupling assembly；
Character line is electrically connected to the grid of the first choice transistor；
Grid selection line is electrically connected to the grid of second selection transistor；
It erases line, is electrically connected to diffusion region and the third conductive region of the second Floating gate transistor；
Bit line is electrically connected to the drain of second selection transistor；And
Source electrode line is electrically connected to the source electrode of the first choice transistor；
Wherein first conductive region, second conductive region and the third conductive region are well, and the 4th conductive region is
Deep-well；
Wherein the third conductive region is around first conductive region and second conductive region；And
Wherein impose on leading the first well electricity for imposing on first conductive region of liter edge of the third well voltage of the third conductive region
Pressure, and the drop edge for imposing on the third well voltage of the third conductive region falls behind first well electricity for imposing on first conductive region
Pressure.
2. nonvolatile storage location as described in claim 1, which is characterized in that first conductive region and this second lead
Electric region is to belong to first electrically, and the third conductive region and the 4th conductive region are to belong to second electrically.
3. nonvolatile storage location as described in claim 1, which is characterized in that the Floating gate includes：
First grid portion, to form the electrode of the coupling assembly；And
Second grid portion, to form the grid of the first Floating gate transistor and being somebody's turn to do for the second Floating gate transistor
Grid；
The wherein area in the first grid portion is big compared with the area in the second grid portion.
4. nonvolatile storage location as described in claim 1, which is characterized in that the coupling assembly is metal-oxide-semiconductor's electricity
Perhaps metal-oxide half field effect transistor.
5. nonvolatile storage location as described in claim 1, which is characterized in that the second Floating gate transistor is gold
Oxygen half field effect transistor or metal-oxide-semiconductor's capacitance.
6. nonvolatile storage location as described in claim 1, which is characterized in that the first Floating gate transistor is to set
Between the first choice transistor and second selection transistor.
7. nonvolatile storage location as described in claim 1, which is characterized in that under read mode, control is applied
In the control line voltage of the control line, control imposes on the word line voltages of the character line, and control imposes on the grid of the grid selection line
Pole selects line voltage, control to impose on the line voltage of erasing of the line of erasing, and control imposes on the bitline voltage of the bit line, and control is applied
In the source line voltage of the source electrode line, control imposes on the first well voltage of first conductive region, and control imposes on this and second leads
The second well voltage in electric region, control impose on the third well voltage of the third conductive region, and control imposes on the 4th conduction
The 4th well voltage in region, with sensing flow through the first choice transistor concatenated mutually, the first Floating gate transistor and
The electric current of second selection transistor, wherein imposing on the first well voltage of first conductive region and imposing on being somebody's turn to do for the control line
Control line voltage is equal and imposes on the third well voltage of the third conductive region and imposes on the line voltage of erasing of the line of erasing
It is equal.
8. nonvolatile storage location as described in claim 1, which is characterized in that under write operation mode, control is applied
In the control line voltage of the control line, control imposes on the word line voltages of the character line, and control imposes on the grid of the grid selection line
Pole selects line voltage, control to impose on the line voltage of erasing of the line of erasing, and control imposes on the bitline voltage of the bit line, and control is applied
In the source line voltage of the source electrode line, control imposes on the first well voltage of first conductive region, and control imposes on this and second leads
The second well voltage in electric region, control impose on the third well voltage of the third conductive region, and control imposes on the 4th conduction
The 4th well voltage in region is to induce electronics tunneling injection in the first Floating gate transistor, wherein imposing on first conduction region
The first well voltage and this in domain impose on the control line voltage of the control line it is equal and impose on the third conductive region this
Three well voltages are equal with the line voltage of erasing of the line of erasing is imposed on.
9. nonvolatile storage location as described in claim 1, which is characterized in that in the case where forbidding write operation mode, control
System imposes on the control line voltage of the control line, and control imposes on the word line voltages of the character line, and control imposes on the grid selection line
Grid select line voltage, control to impose on the line voltage of erasing of the line of erasing, control imposes on the bitline voltage of the bit line, control
System imposes on the source line voltage of the source electrode line, and control imposes on the first well voltage of first conductive region, control impose on this
Second well voltage of two conductive regions, control impose on the third well voltage of the third conductive region, and control imposes on the 4th
4th well voltage of conductive region ends the first choice transistor and second selection transistor to force, wherein impose on this
The first well voltage of one conductive region is equal with the control line voltage of the control line is imposed on and imposes on the third conductive region
The third well voltage it is equal with the line voltage of erasing of the line of erasing is imposed on.
10. nonvolatile storage location as described in claim 1, which is characterized in that under operation mode of erasing, control is applied
In the control line voltage of the control line, control imposes on the word line voltages of the character line, and control imposes on the grid of the grid selection line
Pole selects line voltage, control to impose on the line voltage of erasing of the line of erasing, and control imposes on the bitline voltage of the bit line, and control is applied
In the source line voltage of the source electrode line, control imposes on the first well voltage of first conductive region, and control imposes on this and second leads
The second well voltage in electric region, control impose on the third well voltage of the third conductive region, and control imposes on the 4th conduction
The 4th well voltage in region is to induce the tunneling injection of electronics in the second Floating gate transistor, wherein imposing on the third conduction region
The third well voltage in domain is equal with the line voltage of erasing of the line of erasing is imposed on.
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| TWI632558B (en) * | 2017-05-01 | 2018-08-11 | 卡比科技有限公司 | Non-volatile memory device and operation method of the same |
| US11063772B2 (en) * | 2017-11-24 | 2021-07-13 | Ememory Technology Inc. | Multi-cell per bit nonvolatile memory unit |
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| US7391647B2 (en) * | 2006-04-11 | 2008-06-24 | Mosys, Inc. | Non-volatile memory in CMOS logic process and method of operation thereof |
| CN103094285A (en) * | 2011-11-07 | 2013-05-08 | 力旺电子股份有限公司 | Non-volatile memory unit |
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| US7391647B2 (en) * | 2006-04-11 | 2008-06-24 | Mosys, Inc. | Non-volatile memory in CMOS logic process and method of operation thereof |
| CN103094285A (en) * | 2011-11-07 | 2013-05-08 | 力旺电子股份有限公司 | Non-volatile memory unit |
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