TWI442552B - Differential nonvolatile memory unit and its operation method - Google Patents

Description

Differential non-volatile memory unit and method of operating same

The present invention relates to a non-volatile memory unit, and more particularly to a differential non-volatile memory unit and method of operation thereof.

At present, the demand for non-volatile memory has increased dramatically with the growth of portable electronic products. The conventional floating gate non-volatile memory cell structure is formed by using a poly-Silicon gate of a gold-oxygen half-field transistor and coating it in an oxide layer (for example, SiO ₂ ), which is called floating. Gate. The charge is stored in the floating gate and is isolated by the oxide layer to achieve the effect of charge storage. The operation principle of the floating gate non-volatile memory unit is mainly to use the carrier to inject into the floating gate through the oxide layer, thereby causing the shift of the threshold voltage (V _TH ) of the transistor, so that 0 can be defined. And 1 logical state.

Since traditional non-volatile memory cells are mostly designed and manufactured in a non-standard CMOS process technology, additional masking and processing steps are required to increase the cost of memory fabrication. In the development of integrated circuit system chips, the need to integrate memory cells and systems on the same chip is sometimes required, and the development of non-volatile memory cells in embedded CMOS processes has gradually become an important market application. The evolution of the new process has continued to reduce the thickness of the oxide layer, which also causes the carriers generally stored in the floating gate to be easily lost. Therefore, it has been developed that the differential non-volatile memory can be written multiple times, and the differential type is developed. The advantage is that slight leakage can be tolerated and it is easy to discriminate small current differences.

Referring to Figure 1, in the literature "Yi-Hung Tsai, Hsiao-Lan Yang, Wun-Jie Lin, Chrong Jung Lin, and Ya-Chin King, "A New Differential Logic-Compatible Multiple-Time Programmable Memory Cell," Japanese Journal of In Applied Physics 49 (2010) 04DD13, a conventional multi-write differential type non-volatile memory unit is disclosed, comprising: a first transistor 11, a second transistor 12, and a third The crystal 13 has a first voltage coupling member 14 and a second voltage coupling member 15.

The first transistor 11, the second transistor 12 and the third transistor 13 are fabricated on a P-type doping well 10 (as shown by PW in FIG. 1), the first voltage coupling 14 and the second Voltage couplings 15 are fabricated on N-type wells 140 and 150, respectively (as indicated by NW in Figure 1). The first transistor 11, the second transistor 12 and the third transistor 13 are NMOS transistors, and the first voltage coupling 14 and the second voltage coupling 15 are a MOS structure.

The first transistor 11 includes a gate 111 for storing electric charge, a first end 112 and a second end 113. The second transistor 12 includes a gate 121 for storing electric charge, a first end 122, and a second end 123. The third transistor 13 includes a gate 131, a first end 132 coupled to the second end 113 of the first transistor 11 and the second end 123 of the second transistor 12, and a second end 133.

The first voltage coupling member 14 includes a gate 141 coupled to the gate 111 of the first transistor 11, and a first end 142 and a second end 143 short-circuited to each other when a high voltage is applied. The charge in the gate 141 can be removed through the oxide layer under the gate 141. The second voltage coupling member 15 includes a gate 151 coupled to the gate 121 of the second transistor 12, and a gate 510 coupled to the first end 142 of the first voltage coupling member 14 The first end 152 and the second end 153 can remove the charge in the gate 151 through the oxide layer under the gate 151 when a high voltage is applied.

The writing operation is to apply a plurality of voltages to the memory unit, and inject a charge into the gate 111 or 121 through a channel hot electron (CHE), thereby causing a threshold voltage of the first transistor 11 and the second transistor 12. The difference in value. The reading operation is to apply a plurality of voltages to the memory unit, and the first transistor 11, the second transistor 12, and the third transistor 13 are turned on. At this time, the sensing amplifier (not shown) is used to simultaneously read the first A channel current value of a transistor 11 and a second transistor 12 produces a logic state output. The erase operation applies a plurality of voltages to the memory cell through the Fowler-Nordheim tunneling to eliminate the charge of the gate 111 or 121. The detailed operating voltage data is shown in Table 1 below:

It can be seen from Table 1 that when the memory cell is erased, the boosting is required to be as high as 9.5 V with respect to the second end 133 of the third transistor 13 (for example, the first end of the first voltage coupling 14) 142) When writing, it is also necessary to boost 7V (for example, the first end 112 of the first transistor 11), so there is a disadvantage that the operating voltage difference is large.

Accordingly, it is an object of the present invention to provide a differential non-volatile memory cell that can reduce the operating voltage difference and a method of operating the same.

Therefore, the differential non-volatile memory unit of the present invention comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor.

The first transistor includes a gate for storing a charge, a first end, and a second end. The second transistor includes a gate for storing charge, a first end, and a second end coupled to the second end of the first transistor. The third transistor includes a gate, a first end coupled to the second end of the first transistor, and a second end for controlling the channel of the first transistor and the second transistor Current.

The fourth transistor includes a gate coupled to the gate of the first transistor, and a first end and a second end shorted to each other for coupling a voltage on the first end thereof to the first The gate of the transistor. The fifth transistor includes a gate coupled to the gate of the second transistor, and a first end and a second end that are shorted to each other and coupled to the first end of the fourth transistor. To couple the voltage on its first terminal to the gate of the second transistor.

The first transistor, the second transistor and the third transistor are fabricated on an N-type doping well, and the fourth transistor and the fifth transistor are fabricated on other N-type doping wells. The transistors are P-type transistors.

The method for operating a differential non-volatile memory cell of the present invention is applicable to the differential non-volatile memory cell described above, and comprises the following steps:

Erasing logic 0: applying a plurality of voltages to a first end of the first transistor of the memory cell, a gate and a second end of the third transistor, a first end of the fourth transistor, and Forming the N-type doping well of the first transistor, the voltage is sufficient to cause a breakdown effect of the first transistor to generate a hot carrier, and causing a gate of the first transistor to be injected into a portion of the hot carrier And eliminate the charge.

Erasing logic 1 step: applying a plurality of voltages to a first end of the second transistor of the memory cell, a gate and a second end of the third transistor, a first end of the fourth transistor, and Forming the N-type doping well of the first transistor, the voltage is sufficient to cause a breakdown effect of the second transistor to generate a hot carrier, and causing a gate of the second transistor to be injected into a portion of the hot carrier And eliminate the charge.

The effect of the invention is that the differential non-volatile memory unit can be effectively erased by the structural change and the bumping effect, and can be effectively reduced relative to the second end of the third transistor during operation. Boost and buck.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments.

Referring to FIG. 2 and FIG. 3, a preferred embodiment of the differential non-volatile memory cell of the present invention comprises a first transistor 21, a second transistor 22, a third transistor 23, and a fourth transistor. 24 and a fifth transistor 25. 2 is a top view of the preferred embodiment, and FIG. 3 is a circuit diagram of the preferred embodiment.

The first transistor 21, the second transistor 22 and the third transistor 23 are formed on a main doping well 20, and the fourth transistor 24 and the fifth transistor 25 are respectively fabricated in two Sub-doped wells 240, 250. In the preferred embodiment, the doping wells 20, 240, and 250 are all N-type (as shown by NW in FIG. 2), and the transistors 21-25 are PMOS transistors.

The first transistor 21 includes a gate 211 for storing electric charge, a first end 212 and a second end 213. The second transistor 22 includes a gate 221 for storing electric charge, a first end 222, and a second end 223. The third transistor 23 is configured to control channel currents of the first transistor 21 and the second transistor 22, and includes a gate 231, a second end 213 of the first transistor 21, and the second The second end 223 of the transistor 22 is coupled to the first end 232 and to the second end 233.

The fourth transistor 24 includes a gate 241 coupled to the gate 211 of the first transistor 21, and a first end 242 and a second end 243 short-circuited to each other for coupling the first end 242 thereof. The upper voltage is applied to the gate 211 of the first transistor 21. The fifth transistor 25 includes a gate 251 coupled to the gate 221 of the second transistor 22, and a first end 252 that is shorted to each other and coupled to the first end 242 of the fourth transistor 24. And a second terminal 253 for coupling the voltage on the first terminal 252 to the gate 221 of the second transistor 22.

The voltage coupling ratio (Coupling Ratio) of the fourth transistor 24 coupled to the first transistor 21 is determined by the area ratio of the gate 241 and the gate 211. The voltage coupling ratio can be expressed as:

Voltage coupling ratio =

Wherein, A represents the area of the gate 241 of the fourth transistor 24, and B represents the area of the gate 211 of the first transistor 21. When A>B, the charge is easily in and out of the gate 211; when A<B, the charge is easily in and out of the gate 241. The prior art (Fig. 1) adopts the architecture of A<B, and in the preferred embodiment, in order to increase the voltage coupling ratio, the charge is easily entered and exited by the gate 211, and the gate 241 of the fourth transistor 24 has a larger area. The gate 211 of the first transistor 21 has an area, and similarly, the gate 251 of the fifth transistor 25 has an area larger than the gate 221 of the second transistor 22. In the preferred embodiment, since A>B, a thermal carrier can be generated by the bumping effect for erasing to avoid applying a high voltage to the first terminal 242 of the fourth transistor 24.

Referring to Table 2, a preferred embodiment of the method of operating a differential non-volatile memory cell of the present invention is applicable to the differential non-volatile memory cell described above, and includes the steps of: writing logic 0, writing Logic 1, read data, erase logic 0, and erase logic 1.

3 and 4, FIG. 4 is a cross-sectional view taken along line II' of FIG. 2. The step of writing logic 0 includes: applying 3V to the main doping well 20; applying 0V to the gate 231 of the third transistor 23, applying 3V to the second end 233 of the third transistor 23, and making the third electric The crystal 23 is turned on; applying -3V to the first end 212 of the first transistor 21, applying 0V to the first end 242 of the fourth transistor 24, and the voltage of the first transistor 21 by the fourth transistor 24. The coupling effect causes the first transistor 21 to be turned on; at this time, the first end 222 of the second transistor 22 floats to make the second transistor 22 non-conductive. The holes in the channels of the transistors 21, 23 will move from the second end 233 of the transistor 23 to the first end 212 of the first transistor 21 (as shown in the direction A of Figure 4, the solid circles represent electrons, hollow circles Representing the hole), the hole is accelerated in the vicinity of the junction of the first end 212 of the first transistor 21 by the acceleration of the transverse electric field in the channel to generate electrons and holes, and the electrons and holes are accelerated by the electric field. The impact free generates new electrons and holes, and a cumulative collapse occurs in the vicinity of the junction of the first end 212 of the first transistor 21. The electrons and holes are accelerated by the electric field to obtain a sufficiently high energy to become a hot carrier. After the thermal cavity has a high enough energy to overcome the potential energy barrier between Si-SiO ₂ after the collision process, the vertical electric field between the gate 211 of the first transistor 21 and the channel will have an opportunity to be injected into the first The gate 211 of a transistor 21 is charged. Most of the holes in the channel flow into the first end 212 of the first transistor 21, and most of the electrons generated by the impact free are received by the electric field between the first end 212 of the first transistor 21 and the main doping well 20. The effect flows through the main doping well 20 to form a substrate current.

The step of writing logic 1 includes: applying 3V to the main doping well 20; applying 0V to the gate 231 of the third transistor 23, applying 3V to the second end 233 of the third transistor 23, and making the third electric The crystal 23 is turned on; applying -3V to the first end 222 of the second transistor 22, applying 0V to the first end 242 of the fourth transistor 24, and the voltage of the second transistor 22 by the fifth transistor 25. The coupling effect causes the second transistor 22 to be turned on; at this time, the first end 212 of the first transistor 21 is floated to make the first transistor 21 non-conductive. As described above, the first end 222 of the second transistor 22 undergoes a cumulative collapse to generate a hot carrier, and the gate 221 of the second transistor 22 is injected into a portion of the thermoelectric hole to carry a charge.

Based on the differential type structure design, when one of the first transistor and the second transistor of the memory cell is written, the threshold voltage values of the first transistor 21 and the second transistor 22 are different. If a thermoelectric hole is injected into the gate 211 of the first transistor 21, the threshold voltage of the first transistor 21 is increased, so that the first transistor 21 has a lower channel current than the second transistor 22, and vice versa. Also. In this embodiment, the logic 0 of the memory cell is defined as the channel current of the second transistor 22 is greater than the channel current of the first transistor 21; the logic 1 is defined as the channel current of the first transistor 21 is greater than the second transistor. 22 channel current.

Referring to FIG. 3, the step of reading data includes: applying 3V to the main doping well 20; applying 1.8V to the gate 231 of the third transistor 23, applying 3V to the second end 233 of the third transistor 23, Turning the third transistor on; and applying 2V to the first end 212 of the first transistor 21 and the first end 222 of the second transistor 22, applying 1V (read mode 1) or 1.5V (reading Mode 2) To the first end 242 of the fourth transistor 24, at least one of the first transistor 21 and the second transistor 22 generates a channel current (I1 and I2 in the figure). At this time, a channel current of the first transistor 21 and the second transistor 22 is received by a sense amplifier 3 and compared, and a logic state output is generated.

Referring to Figures 3 and 5, Figure 5 is a cross-sectional view taken along line I-I' of Figure 2 . The erase logic 0 step includes: applying 3V to the main doping well 20; applying 0V to the gate 231 of the third transistor 23, applying 3V to the second end 233 of the third transistor 23, causing the third The crystal 23 is turned on; -3V is applied to the first end 212 of the first transistor 21, 6V is applied to the first end 242 of the fourth transistor 24, and the voltage of the first transistor 21 is applied by the fourth transistor 24. The coupling effect causes the first transistor 21 to be non-conducting; the first end 222 of the second transistor 22 floats to make the second transistor 22 non-conductive. At this time, the first transistor 21 generates a large amount of leakage current, and flows to the first end 212 of the first transistor 21 via the main doping well 20, and is accelerated by the high electric field near the junction of the first end 212 of the first transistor 21. In the vicinity of the junction of the first end 212 of the first transistor 21, an impact is generated to generate electrons and holes (as shown by the direction B in Fig. 5). The electrons generated by the impact are accelerated by a high electric field near the junction of the first end 212 to obtain a sufficiently high energy to become hot electrons. In other words, the first transistor 21 has a breakdown effect to generate a hot carrier. After the collision of the hot electrons, if there is still enough energy to overcome the potential energy barrier between the Si-SiO2, the influence of the vertical electric field between the gate 211 of the first transistor 21 and the channel will have an opportunity to be injected into the first The gate 211 of the transistor 21 is removed to eliminate the charge. Obviously, the injection of hot electrons into the gate 211 of the first transistor 21 lowers the threshold voltage value of the first transistor 21, so that the channel current increases, thus causing more hot electrons to be injected into the first transistor 21. In the gate 211, the channel current is gradually increased. This process will eventually lead to the burning of the memory cells, so that the third transistor 23 is connected in series with the first transistor 21 in order to limit the magnitude of the channel current of the first transistor 21, and to avoid the occurrence of component burnout.

The erase logic 1 step includes: applying -3V to the main doping well 20; applying 0V to the gate 231 of the third transistor 23, applying 3V to the second end 233 of the third transistor 23, making the third The transistor 23 is turned on; -3V is applied to the first end 222 of the second transistor 22, 6V is applied to the first end 242 of the fourth transistor 24, and the second transistor 22 is applied to the second transistor 22 The voltage coupling effect causes the second transistor 22 to be non-conducting; the first end 212 of the first transistor 21 is floated to make the first transistor 21 non-conductive. As described above, the second transistor 22 is subjected to a breakdown effect to generate a hot carrier, and the gate 221 of the second transistor 22 is injected with a portion of the hot electrons to eliminate the charge.

When the above embodiment is designed with a 3.3V Normal PMOS transistor in a standard 0.18μm CMOS process technology, the memory cell is measured in the first read mode 1 when the memory cell is initially not written. The channel currents of the transistor 21 and the second transistor 22 are approximately 8.81 μA and 7.86 μA, respectively. When the mode 2 is read, the channel currents of the first transistor 21 and the second transistor 22 are measured to be about 2.31 μA and 2.03 μA, respectively.

After the logic 0 is written, when the read mode 1 is operated, the channel currents of the first transistor 21 and the second transistor 22 are measured to be about 2.59 μA and 8.97 μA, respectively. When the mode 2 is read, the channel currents of the first transistor 21 and the second transistor 22 are measured to be about 0.22 μA and 2.15 μA, respectively.

After the logic 0 is erased, when the read mode 1 is operated, the channel currents of the first transistor 21 and the second transistor 22 are measured to be about 9.53 μA and 7.59 μA, respectively, and when the read mode 2 is operated, the amount is The channel currents of the first transistor 21 and the second transistor 22 were measured to be about 2.47 μA and 1.97 μA, respectively.

After the logic 1 is written, when the read mode 1 is operated, the channel currents of the first transistor 21 and the second transistor 22 are measured to be about 10.7 μA and 1.97 μA, respectively. When the mode 2 is read, the channel currents of the first transistor 21 and the second transistor 22 are measured to be about 2.6 μA and 0.15 μA, respectively.

After the logic 1 is erased, when the read mode 1 is operated, the channel currents of the first transistor 21 and the second transistor 22 are measured to be approximately 8.94 μA and 8.24 μA, respectively, and when the read mode 2 is operated, the amount is The channel currents of the first transistor 21 and the second transistor 22 were measured to be about 2.34 μA and 2.26 μA, respectively.

In summary, the above embodiment performs the erasing operation by means of a structural change and a hot carrier injection by the bumping effect, relative to the 3V of the second end 233 of the third transistor 23, In addition to the operation, it is required to boost 3V (for example, 6V of the first end 242 of the fourth transistor 24) and a step-down of 6V (for example, -3V of the first end 212 of the first transistor 21), which is lower than the prior art In addition to the operation, it is required to boost 9.5V (for example, the first end 142 of the fourth transistor 14 is opposite to the second end 133 of the third transistor 13), and the voltage is boosted to 9.5V in the design complexity of the external circuit. The design is more complicated. In addition, the above embodiment performs the write operation by means of a structural change and a hot carrier injection by the cumulative collapse, and the write operation is required with respect to the 3V of the second end 233 of the third transistor 23. The step-down of 6V (eg, -3V of the first terminal 212 of the first transistor 21) is also lower than the prior art required to boost 7V during the write operation (eg, the first end 112 of the first transistor 11 is relative to Similarly, since the second end 133) of the third transistor 13 is only required to be stepped down by 6 V, the external circuit is also easier to design than boosting to 7 V, and the object of the present invention can be achieved.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

20. . . Main doping well

twenty one. . . First transistor

211. . . Gate

212. . . First end

213. . . Second end

twenty two. . . Second transistor

221. . . Gate

222. . . First end

223. . . Second end

twenty three. . . Third transistor

231. . . Gate

232. . . First end

233. . . Second end

twenty four. . . Fourth transistor

240. . . Secondary doping well

241. . . Gate

242. . . First end

243. . . Second end

25. . . Fifth transistor

250. . . Secondary doping well

251. . . Gate

252. . . First end

253. . . Second end

3. . . Sense amplifier

Figure 1 is a top view showing the structure of a conventional differential non-volatile memory unit;

Figure 2 is a top plan view showing the structure of a preferred embodiment of the differential non-volatile memory cell of the present invention;

Figure 3 is a circuit diagram of the preferred embodiment;

Figure 4 is a cross-sectional view taken along line I-I' of Figure 2, illustrating the principle of the write operation of the preferred embodiment of the method of operating a differential non-volatile memory cell of the present invention;

Figure 5 is a cross-sectional view taken along line I-I' of Figure 2 illustrating the principle of the erasing operation of the preferred embodiment.

20. . . Main doping well

twenty one. . . First transistor

211. . . Gate

212. . . First end

213. . . Second end

twenty two. . . Second transistor

221. . . Gate

222. . . First end

223. . . Second end

twenty three. . . Third transistor

231. . . Gate

232. . . First end

233. . . Second end

twenty four. . . Fourth transistor

240. . . Secondary doping well

241. . . Gate

242. . . First end

243. . . Second end

25. . . Fifth transistor

250. . . Secondary doping well

251. . . Gate

252. . . First end

253. . . Second end

Claims (9)

A differential non-volatile memory unit includes: a first transistor, including a gate for storing charge, a first end and a second end; and a second transistor, including a device for storing a gate of the charge, a first end, and a second end coupled to the second end of the first transistor; a third transistor comprising a gate, a second portion of the first transistor a first end coupled to the end, and a second end for controlling channel currents of the first transistor and the second transistor; a fourth transistor comprising a gate coupled to the first transistor a gate connected, and a first end and a second end shorted to each other for coupling a voltage on the first end to the gate of the first transistor; and a fifth transistor, including a a gate coupled to the gate of the second transistor, and a first end and a second end shorted to each other and coupled to the first end of the fourth transistor for coupling the voltage on the first end thereof a gate to the second transistor; wherein the first transistor, the second transistor, and the third transistor are fabricated in an N-type doping well The fourth transistor and the fifth transistor are fabricated on other N-type doping wells, and the transistors are P-type transistors. The memory unit of claim 1, wherein a gate area of the fourth transistor is greater than a gate area of the first transistor, and a gate area of the fifth transistor is greater than the second The gate area of the crystal. A method of operating a differential non-volatile memory cell, the memory cell comprising a first transistor, a second transistor, and a third transistor fabricated on an N-doped well, and fabricated in other a fourth transistor and a fifth transistor on the N-type doping well, the first transistor includes a gate for storing electric charge, a first end and a second end, and the second transistor includes a second transistor a gate for storing a charge, a first end, and a second end coupled to the second end of the first transistor, the third transistor including a gate, a first transistor a first end coupled to the second end, and a second end for controlling channel currents of the first transistor and the second transistor, the fourth transistor including a gate of the first transistor a coupled gate, and a first end and a second end shorted to each other for coupling a voltage on the first end thereof to a gate of the first transistor, the fifth transistor including a first a gate coupled to the gate of the second transistor, and a first short circuit coupled to the first end of the fourth transistor And a second end for coupling a voltage on the first end thereof to a gate of the second transistor, the transistor being a P-type transistor, the method comprising the steps of: erasing logic 0: applying a plurality of voltages respectively reaching a first end of the first transistor of the memory unit, a gate and a second end of the third transistor, a first end of the fourth transistor, and the first transistor is fabricated The N-type doping well, the voltage is sufficient for the first transistor to have a breakdown effect to generate a hot carrier, and the gate of the first transistor is injected with a portion of the hot carrier to eliminate the charge; and erasing Logic 1 step: applying a plurality of voltages to the first end of the second transistor of the memory unit, the gate and the second end of the third transistor, the first end of the fourth transistor, and The N-type doping well of the first transistor, the voltage is sufficient to cause a breakdown effect of the second transistor to generate a hot carrier, and the gate of the second transistor is injected into a portion of the hot carrier to eliminate Charge. The method of claim 3, wherein in the step of erasing logic 0, the applied voltage is to turn on the third transistor to limit the current flowing through the third transistor, and The fourth transistor is coupled to a voltage at its first end such that the first transistor is non-conducting. The method of claim 3, wherein in the erasing logic 1 step, the applied voltage is to turn on the third transistor to limit the current flowing through the third transistor, and The fifth transistor is coupled to the voltage at its first terminal such that the second transistor is non-conducting. According to the method of claim 3, the method further includes the step of: writing a logic 0: applying a plurality of voltages to the first end of the first transistor of the memory unit, the third transistor a gate and a second end, a first end of the fourth transistor, and the N-type doping well formed with the first transistor, the voltages being sufficient to cause a cumulative collapse of the first end of the first transistor Generating a hot carrier, and causing a gate of the first transistor to be injected with a portion of the hot carrier to carry a charge; and writing a logic 1 step: applying a plurality of voltages to the second transistor of the memory cell a first end, a gate and a second end of the third transistor, a first end of the fourth transistor, and the N-type doping well formed with the first transistor, the voltages being sufficient for the second The first end of the transistor undergoes a cumulative collapse to generate a hot carrier, and the gate of the second transistor is injected with a portion of the hot carrier to carry a charge. The method of claim 6, wherein in the writing logic 0 step, the applied voltage is to turn on the third transistor, and the fourth transistor is coupled to the first end thereof. The voltage causes the first transistor to conduct. The method of claim 6, wherein in the writing logic 1 step, the applied voltage is to turn on the third transistor, and the fifth transistor is coupled to the first end thereof The voltage causes the second transistor to conduct. According to the method of claim 3, the method further includes the step of: reading a data: applying a plurality of voltages to the first end of the first transistor of the memory unit, and the second transistor An end, a gate and a second end of the third transistor, a first end of the fourth transistor, and the N-type doping well on which the first transistor is formed, the voltages being sufficient to make the first At least one of the crystal and the second transistor and the third transistor generate a channel current.