CN105259676B - A kind of array substrate, the production method of display panel and array substrate - Google Patents
A kind of array substrate, the production method of display panel and array substrate Download PDFInfo
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- CN105259676B CN105259676B CN201510796890.6A CN201510796890A CN105259676B CN 105259676 B CN105259676 B CN 105259676B CN 201510796890 A CN201510796890 A CN 201510796890A CN 105259676 B CN105259676 B CN 105259676B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/0128—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on electro-mechanical, magneto-mechanical, elasto-optic effects
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/3433—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using light modulating elements actuated by an electric field and being other than liquid crystal devices and electrochromic devices
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- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Optics & Photonics (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses the production methods of a kind of array substrate, display panel and array substrate.The array substrate, including：Multiple pixel units；Each pixel unit both sides are respectively arranged with the first data line and the second data line；Each pixel unit includes first film transistor, the second thin film transistor (TFT), transparent reference layer and the nontransparent deformation layer to insulate above the transparent reference layer and with the transparent reference layer；Wherein, the output end of the first film transistor is electrically connected with the transparent reference layer, and input terminal is electrically connected with corresponding first data line, and control terminal is electrically connected with corresponding scan line；The output end of second thin film transistor (TFT) is electrically connected with the nontransparent deformation layer, and input terminal is electrically connected with corresponding second data line, and control terminal is electrically connected with the corresponding scan line.The display panel structure made using array substrate of the present invention is simple, and production cost is low.
Description
Technical field
The present embodiments relate to a kind of display technology field more particularly to array substrate, display panel and array bases
The production method of plate.
Background technology
Information can be intuitively presented to people by display device due to having so that the transmission of interpersonal information with
More convenient advantage is exchanged, is widely used in the Working Life of people.
With the continuous development of display technology, display device experienced display picture from black and white to color so far from being born,
From obscuring to clear, from bulky thick and heavy to frivolous development course, the performance of display device is also promoted constantly.But work as
Various display devices of modern mainstream, such as LCD (Liquid Crystal Display) liquid crystal display etc. or generally existing
Complicated, the problems such as manufacture craft is cumbersome and of high cost,
Invention content
The present invention provides a kind of array substrate, the production method of display panel and array substrate, to solve the prior art
The problem that middle display device structure is complicated, preparation process is cumbersome and of high cost.
In a first aspect, an embodiment of the present invention provides a kind of array substrates, including：
Multiple pixel units；
Each pixel unit both sides are respectively arranged with the first data line and the second data line；
Each pixel unit includes first film transistor, the second thin film transistor (TFT), transparent reference layer and is located at
The nontransparent deformation layer to insulate above the transparent reference layer and with the transparent reference layer；
Wherein, the output end of the first film transistor is electrically connected with the transparent reference layer, input terminal with it is corresponding
The first data line electrical connection, control terminal are electrically connected with corresponding scan line；The output end of second thin film transistor (TFT) with
The nontransparent deformation layer electrical connection, input terminal and the corresponding second data line electrical connection, control terminal with it is corresponding described
Scan line is electrically connected；According to the voltage difference of itself and the transparent reference layer elastic deformation occurs for the nontransparent deformation layer, to change
Become area coverage of the nontransparent deformation layer to the transparent reference layer.
Second aspect, the embodiment of the present invention additionally provide a kind of display panel, including：
Color membrane substrates and any array substrate of first aspect, the array substrate are opposite with the color membrane substrates
Setting.
The third aspect, the embodiment of the present invention additionally provide a kind of production method of array substrate, including：
Form the first film transistor of each pixel unit, the second thin film transistor (TFT), Yi Jiwei in multiple pixel units
The first data line and the second data line in each pixel unit both sides；
Transparent reference layer is sequentially formed in each pixel unit and above the transparent reference layer and with it is described
The nontransparent deformation layer of transparent reference layer insulation；
Wherein, the output end of the first film transistor is electrically connected with the transparent reference layer, input terminal with it is corresponding
The first data line electrical connection, control terminal are electrically connected with corresponding scan line；The output end of second thin film transistor (TFT) with
The nontransparent deformation layer electrical connection, input terminal and the corresponding second data line electrical connection, control terminal with it is corresponding described
Scan line is electrically connected；According to the voltage difference of itself and the transparent reference layer elastic deformation occurs for the nontransparent deformation layer, to change
Become area coverage of the nontransparent deformation layer to the transparent reference layer.
The present invention is led to by the way that nontransparent deformation layer and transparent reference layer are arranged in each pixel unit of array substrate
Cross the electricity of nontransparent deformation layer and transparent reference layer described in the first data line, the second data line and scan line co- controlling
Pressure, occurs different degrees of deformation to control the deformation layer, achievees the purpose that control array substrate light emission rate with this, in this way
Without liquid crystal material can to realizing the control that show of image, compared with the existing technology in display device for it is simple in structure,
Production technology is not only simplified, production cost is also reduced.
Description of the drawings
Fig. 1 is a kind of overlooking structure diagram of array substrate provided in an embodiment of the present invention；
Fig. 2 is the cross-sectional view in the directions A1-A2 provided in an embodiment of the present invention along Fig. 1；
Fig. 3 is the cross-sectional view in the directions B1-B2 provided in an embodiment of the present invention along Fig. 1；
Fig. 4 is the overlooking structure diagram of another array substrate provided in an embodiment of the present invention；
Fig. 5 is the cross-sectional view in the directions D1-D2 provided in an embodiment of the present invention along Fig. 4；
Fig. 6 is the cross-sectional view in the directions E1-E2 provided in an embodiment of the present invention along Fig. 4；
Fig. 7 is the structural schematic diagram of another array substrate provided in an embodiment of the present invention；
Fig. 8 is the overlooking structure diagram of another array substrate provided in an embodiment of the present invention；
Fig. 9 is the principle schematic of array substrate shown in Fig. 8；
Figure 10 is the overlooking structure diagram of another array substrate provided in an embodiment of the present invention；
Figure 11 is a kind of structural schematic diagram of display panel provided in an embodiment of the present invention；
Figure 12 is the flow diagram of the production method of array substrate provided in an embodiment of the present invention.
Specific implementation mode
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limitation of the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
Fig. 1 is a kind of overlooking structure diagram of array substrate provided in an embodiment of the present invention, and Fig. 2 is the embodiment of the present invention
The cross-sectional view in the directions A1-A2 along Fig. 1 provided, Fig. 3 are the side B1-B2 provided in an embodiment of the present invention along Fig. 1
To cross-sectional view.As shown in Figure 1-Figure 3, array substrate provided in an embodiment of the present invention includes mainly with lower structure：
Multiple pixel units (not marked in figure), the first data line 130, the second data line 140 and scan line 150.
Wherein, each pixel unit includes：First film transistor 110, the second thin film transistor (TFT) 120, transparent ginseng
The nontransparent deformation layer examined layer 161 and insulated above the transparent reference layer 161 and with the transparent reference layer 161
162；First data line, 130 and second data line 140 is arranged in the both sides of each pixel unit, can be specifically
Each pixel unit is correspondingly arranged first data line 130 and second data line 140 respectively.
Wherein, the output end 111 of first film transistor 110 is electrically connected with transparent reference layer 161, input terminal 112 with it is right
The first data line 130 electrical connection answered, control terminal 113 are electrically connected with corresponding scan line 150；The output of second thin film transistor (TFT)
End 121 is electrically connected with nontransparent deformation layer 162, and input terminal 122 is electrically connected with corresponding second data line 140, control terminal 123 and
Corresponding scan line 150 is electrically connected；According to the voltage difference of itself and transparent reference layer 161 elastic shape occurs for nontransparent deformation layer 162
Become, to change the area coverage of nontransparent 162 pairs of transparent reference layer 161 of deformation layer.As shown in Figure 1, two neighboring pixel unit
Between interval one first data line 130 and one second data line 140, each pixel unit is respectively by the first data line of its both sides
130 and second data line 140 control.
The operation principle of array substrate provided in this embodiment is as follows：
Referring to Fig. 1, scan line 150 is the control terminal 113 and the second film crystal of often capable first film transistor 110
The control terminal 123 of pipe 120 provides scanning signal, and the first film transistor 110 of the row and the second thin film transistor (TFT) 120 is made to beat
It opens.First data line 130 is to the input terminal 112 of first film transistor 110, and the second data line 140 is to the second thin film transistor (TFT)
120 input terminal 122 provides data-signal；Due to the output end 111 and transparent reference layer of the first film transistor 110
161 electrical connections, the output end 121 of the second thin film transistor (TFT) 120 are electrically connected with nontransparent deformation layer 162, so passing through the first number
The data-signal inputted according to line 130 and the second data line 140 controls the transparent reference layer 161 and the nontransparent deformation layer
Voltage difference between 162；Pass through the polarity and voltage of the voltage of the voltage and transparent reference layer 161 of nontransparent deformation layer 162
Whether the size of value controls nontransparent 162 deformation of deformation layer and the degree of deformation.Specifically, for example when the first data line 130
When identical with the data-signal polarity of the second data line 140 input, the transparent reference layer 161 and the nontransparent deformation layer
162 polarity is identical, the elastic deformation (as shown in dotted line in Fig. 2 or Fig. 3) that nontransparent deformation layer 162 is flipped up, light
Line can pass through.The data-signal inputted by the first data line 130 and the second data line 140 controls nontransparent deformation layer 162
Voltage and transparent reference layer 161 between voltage difference, control nontransparent deformation layer 162 and be flipped up degree, to control
The percent of pass of light.It is described transparent when the data-signal polarity that the first data line 130 and the second data line 140 input is opposite
The polarity of reference layer 161 and the nontransparent deformation layer 162 is completely covered on the contrary, nontransparent deformation layer 162 does not deform upon
Surface of insulating layer, light cannot pass through, and therefore, array substrate provided in an embodiment of the present invention can realize the tune to light penetration
Section.
The embodiment of the present invention in each pixel unit of array substrate by being arranged nontransparent deformation layer 162 and transparent
Reference layer 161 passes through the first data line 130, the second data line 140 and the nontransparent deformation layer of 150 co- controlling of scan line 162
And the voltage of transparent reference layer 161, control nontransparent deformation layer 162 and the voltage difference between the two of transparent reference layer 161 with
And the respective polarity of voltage of the two, and then the deformation degree of nontransparent deformation layer 162 can be controlled, 162 pairs of nontransparent deformation layer
The area coverage of transparent reference layer 161 changes with deformation degree, and the transmitance of light is controlled with this, realizes different gray scales
Image shows, compared with the existing technology in display device structure it is simple, not only simplify production technology, also reduce and be produced into
This.
Preferably, the array substrate provided referring to Fig. 2, above-described embodiment, in first film transistor 110, the second film
It is additionally provided with absolutely between film layer and the transparent reference layer 161 where transistor 120 and the first data line and the second data line
Edge layer 170；The output end 111 of first film transistor is electrically connected by insulating layer via 171 with transparent reference layer 161, and second
The output end 121 of thin film transistor (TFT) is electrically connected by insulating layer via 171 with nontransparent deformation layer 162.
Further, it is preferred that the insulating layer 170 is set as planarization layer 170, the output end of first film transistor
111 are electrically connected by planarization layer via 171 with transparent reference layer 161, and the output end 121 of the second thin film transistor (TFT) is by flat
Change layer via 171 to be electrically connected with nontransparent deformation layer 162.Flatness layer 170 can make transparent reference layer 161 be in flat and put down
On face, to which the relative distance size between transparent reference layer 161 and nontransparent deformation layer 162 is distributed more in the horizontal direction
It is even, on the flatness layer transparent reference layer 161 and on transparent reference layer 161 and with transparent reference layer 161 it is exhausted
Voltage's distribiuting between the nontransparent deformation layer 162 of edge is more uniform, can more effectively control nontransparent deformation layer 162 and carry out
Deformation.
Fig. 4 is the overlooking structure diagram of another array substrate provided in an embodiment of the present invention, and Fig. 5 is that the present invention is implemented
The cross-sectional view in the directions D1-D2 along Fig. 4 that example provides, Fig. 6 are the E1-E2 provided in an embodiment of the present invention along Fig. 4
The cross-sectional view in direction.It should be noted that for convenience of description, it is same as the previously described embodiments in following embodiment
Structure still continues to use identical reference numeral.Referring to Fig. 4, Fig. 5 and Fig. 6, the array substrate includes：Multiple pixel units,
Each pixel unit includes first film transistor 110, the second thin film transistor (TFT) 120, transparent reference layer 161 and is located at
The nontransparent deformation layer 162 transparent reference layer 161 top and insulated with the transparent reference layer 161；It is separately positioned on every
The first data line 130 and the second data line 140 of a pixel unit both sides.Wherein, the output end of first film transistor 110
111 are electrically connected with transparent reference layer 161, and input terminal 112 is electrically connected with corresponding first data line 130, control terminal 113 with it is corresponding
Scan line 150 be electrically connected；The output end 121 of second thin film transistor (TFT) 120 is electrically connected with nontransparent deformation layer 162, input terminal
122 are electrically connected with corresponding second data line 140, and control terminal 123 is electrically connected with corresponding scan line 150.
Unlike the embodiments above, Fig. 4, Fig. 5 and array substrate shown in fig. 6 further include：
Protective layer 180, the protective layer 180 cover the subregion of the nontransparent deformation layer 162, and being used for will be described non-
Transparent deformation layer 162 is fixed in the array substrate.So that the nontransparent deformation layer 162 is connect more with the array substrate
Add firm, nontransparent deformation layer 162 is prevented to be detached from from the array substrate.Optionally, the protective layer 180 can also be by
The nontransparent deformation layer 162 is same as at 121 electrical connection of output end of second thin film transistor (TFT) 120 to be covered, this
The benefit of sample setting is that nontransparent deformation layer 162 can be made when deforming upon, and still is able to ensure the nontransparent deformation layer
162 and second the output end 121 of thin film transistor (TFT) effectively realize electrical connection.Optionally, protective layer 180 can be that viscosity is high
Nonmetallic materials can also be the metal material, such as copper, aluminium etc. of conduction.
Optionally, referring to Fig. 7, when the protective layer 180 is metal material, the nontransparent deformation layer 162 can be
It is electrically connected with the realization of the output end 121 of second thin film transistor (TFT) 120 by the protective layer 180.
Fig. 8 is the overlooking structure diagram of another array substrate provided in an embodiment of the present invention, and Fig. 9 is battle array shown in Fig. 8
The principle schematic of row substrate.Referring to Fig. 8 and Fig. 9, array substrate includes in above-described embodiment：Multiple pixel units, Mei Gesuo
Pixel unit is stated to include first film transistor 110, the second thin film transistor (TFT) 120, transparent reference layer 161 and be located at described transparent
The nontransparent deformation layer 162 reference layer 161 top and insulated with the transparent reference layer 161；It is separately positioned on each pixel list
The first data line 130 and the second data line 140 of first both sides；And scan line 150.
Unlike the embodiments above, Fig. 8 and array substrate shown in Fig. 9 can also include：
A plurality of reference potential line 190 can be the transparent reference layer 161 and the nontransparent deformation layer 162 with it is described
Reference potential line 190 insulate and part is overlapping.Transparent reference layer 161 and nontransparent deformation layer 162 respectively with reference potential line 190
Form capacitance C1 and C2, the voltage on voltage and nontransparent deformation layer 162 to maintain transparent reference layer 161, to above-mentioned
Voltage Z can be continuously maintained next update picture.
Figure 10 is the overlooking structure diagram of another array substrate provided in an embodiment of the present invention, as shown in Figure 10, institute
Stating array substrate includes：Multiple pixel units, each pixel unit include first film transistor 110, the second film crystalline substance
Body pipe 120, transparent reference layer 161 and above the transparent reference layer 161 and with the transparent reference layer 161 insulation
Nontransparent deformation layer 162；It is separately positioned on the first data line 130 and the second data line 140 of each pixel unit both sides；Scanning
Line 150；Cover the protective layer 180 of nontransparent 162 subregion of deformation layer；And reference potential line 190.
Unlike the embodiments above, the transparent reference layer 161 and the protective layer 180 are respectively with described with reference to electricity
Bit line 190 insulate and part is overlapping, and protective layer 180 is electrically connected with nontransparent deformation layer 162.Array provided in an embodiment of the present invention
The operation principle of substrate is same as above, when array substrate is in running order, transparent reference layer 161 and reference potential line 190
Capacitance is formed, to maintain the voltage of transparent reference layer 161；Nontransparent deformation layer 162 passes through protective layer 180 and reference potential line
190 form capacitance, to maintain the voltage on nontransparent deformation layer 162, in transparent reference layer 161 and nontransparent deformation layer
Voltage difference is formed between 162.
It should be noted that above-mentioned first film transistor 110 and the second thin film transistor (TFT) 120 can be a-Si non-crystalline silicons
Structure, low-temperature polysilicon silicon structure or oxide-semiconductor structure.
Further, on the basis of the above embodiments, it is preferred that reference potential line 190 is with scan line 150 in same system
Make in technique, be made of same material, the benefit designed in this way is in the production process of array substrate, it is possible to reduce technique walks
Suddenly, it is only necessary to which same step can realize the making of reference potential line 190 and scan line 150, reduce production cost.
Figure 11 is a kind of structural schematic diagram of display panel provided in an embodiment of the present invention.As shown in figure 11, the present invention is real
A kind of display panel of example offer is provided, including：
Any array substrate 12 in color membrane substrates 11 and above-described embodiment, array substrate 12 are opposite with color membrane substrates 11
Setting.
Further, display panel further includes：
Support member 13, support member 13 is between array substrate and color membrane substrates 11, when nontransparent deformation layer 162 is sent out
When raw largest deformation, the thickness of support member 13 is more than deformation layer peak and 12 neighbour's color membrane substrates of array substrate, 11 side
Distance.The shape of support member 13 can be cylindrical structure or cube structure or sphere structure or vertebral body structure or terrace with edge
Structure is not specifically limited herein.
It should be noted that display panel provided in an embodiment of the present invention can also be including other for supporting display surface
The device of plate normal work, display panel provided in an embodiment of the present invention are therefore same as a result of above-mentioned array substrate 12
Advantageous effect with above-mentioned array substrate 12.
Preferably, display panel in above-described embodiment further includes：
It is set to the antistatic transparency conducting layer (not shown) that color membrane substrates 11 deviate from 12 side of array substrate, is used for
Prevent electrostatic.Antistatic transparency conducting layer can be ITO (Indium Tin Oxide, tin indium oxide) layer.
Figure 12 is the flow diagram of the production method of array substrate provided in an embodiment of the present invention.As shown in figure 12, originally
The production method for the array substrate that embodiment provides, mainly includes the following steps that：
S11：Formed the first film transistor of each pixel unit in multiple pixel units, the second thin film transistor (TFT), with
And the first data line and the second data line positioned at each pixel unit both sides.
S12：Transparent reference layer is sequentially formed in each pixel unit and above the transparent reference layer and with
The nontransparent deformation layer of the transparent reference layer insulation.
Wherein, the output end of the first film transistor is electrically connected with the transparent reference layer, input terminal with it is corresponding
The first data line electrical connection, control terminal are electrically connected with corresponding scan line；The output end of second thin film transistor (TFT) with
The nontransparent deformation layer electrical connection, input terminal and the corresponding second data line electrical connection, control terminal with it is corresponding described
Scan line is electrically connected；According to the voltage difference of itself and the transparent reference layer elastic deformation occurs for the nontransparent deformation layer, to change
Become area coverage of the nontransparent deformation layer to the transparent reference layer.
Optionally, the first film transistor of each pixel unit, the second film crystal in forming multiple pixel units
Pipe and after the first data line and the second data line of each pixel unit both sides, in each pixel unit successively
The nontransparent deformation layer for forming transparent reference layer and insulating above the transparent reference layer and with the transparent reference layer
Before, can also include：
Where the first film transistor, second thin film transistor (TFT) and the first data line and the second data line
Insulating layer is formed above film layer, and is formed insulating layer via and exposed the output end of the first film transistor and described second thin
The output end of film transistor；The output end of the first film transistor is electrically connected by insulating layer via and the transparent reference layer
It connects, the output end of second thin film transistor (TFT) is electrically connected by insulating layer via with the nontransparent deformation layer.
Preferably, in above-described embodiment, in forming multiple pixel units the first film transistor of each pixel unit,
Second thin film transistor (TFT) and after the first data line and the second data line of each pixel unit both sides, in each picture
Transparent reference layer is sequentially formed in plain unit and is insulated above the transparent reference layer and with the transparent reference layer
Before nontransparent deformation layer, can also include：
Where the first film transistor, second thin film transistor (TFT) and the first data line and the second data line
Planarization layer is formed above film layer, and forms the output end and described that planarization layer via exposes the first film transistor
The output end of two thin film transistor (TFT)s；The output end of the first film transistor passes through planarization layer via and the transparent reference
Layer electrical connection, the output end of second thin film transistor (TFT) are electrically connected by planarization layer via with the nontransparent deformation layer.
Optionally, in above-described embodiment, after forming the nontransparent deformation layer, can also include：
Protective layer is formed, the protective layer covers the subregion of the nontransparent deformation layer, and being used for will be described nontransparent
Deformation layer is fixed in the array substrate.
Optionally, in above-described embodiment, can also include：
It forms a plurality of reference potential line, the transparent reference layer and the nontransparent deformation layer and the reference potential line is exhausted
Edge and part is overlapping or the transparent reference layer and insulate with the protective layer and the reference potential line and part is overlapping.
Optionally, the reference potential line can be formed simultaneously with scan line, and the benefit designed in this way is can to reduce processing step,
Improve production efficiency.
Note that above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that
The present invention is not limited to specific embodiments described here, can carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out to the present invention by above example
It is described in further detail, but the present invention is not limited only to above example, without departing from the inventive concept, also
May include other more equivalent embodiments, and the scope of the present invention is determined by scope of the appended claims.
Claims (11)
1. a kind of array substrate, which is characterized in that including：
Multiple pixel units；
Each pixel unit both sides are respectively arranged with the first data line and the second data line；
Each pixel unit includes first film transistor, the second thin film transistor (TFT), transparent reference layer and is located at described
The nontransparent deformation layer to insulate above transparent reference layer and with the transparent reference layer；
Wherein, the output end of the first film transistor is electrically connected with the transparent reference layer, input terminal with it is corresponding described
First data line is electrically connected, and control terminal is electrically connected with corresponding scan line；The output end of second thin film transistor (TFT) with it is described
Nontransparent deformation layer electrical connection, input terminal are electrically connected with corresponding second data line, control terminal and the corresponding scanning
Line is electrically connected；According to the voltage difference of itself and the transparent reference layer elastic deformation occurs for the nontransparent deformation layer, to change
State area coverage of the nontransparent deformation layer to the transparent reference layer；
The array substrate further includes：
A plurality of reference potential line, the transparent reference layer and the nontransparent deformation layer insulate with the reference potential line and part
It is overlapping；Or protective layer and a plurality of reference potential line, the protective layer covers the subregion of the nontransparent deformation layer, described
Bright reference layer and the protective layer insulate with the reference potential line and part is overlapping.
2. array substrate according to claim 1, which is characterized in that in the first film transistor, described second thin
Where film transistor and the first data line and the second data line insulating layer is additionally provided between film layer and the transparent reference layer；
The output end of the first film transistor is electrically connected by insulating layer via with the transparent reference layer, and second film is brilliant
The output end of body pipe is electrically connected by insulating layer via with the nontransparent deformation layer.
3. array substrate according to claim 1, which is characterized in that in the first film transistor, described second thin
Where film transistor and the first data line and the second data line planarization is additionally provided between film layer and the transparent reference layer
Layer；The output end of the first film transistor is electrically connected by planarization layer via with the transparent reference layer, and described second
The output end of thin film transistor (TFT) is electrically connected by planarization layer via with the nontransparent deformation layer.
4. array substrate according to claim 1, which is characterized in that the reference potential line is with the scan line same
In manufacture craft, it is made of same material.
5. array substrate according to claim 1, which is characterized in that the protective layer is metal material.
6. a kind of display panel, which is characterized in that including：
Any array substrate, the array substrate and the color membrane substrates phase in color membrane substrates and claim 1-5
To setting.
7. display panel according to claim 6, which is characterized in that further include：
Support member, the support member is between the array substrate and the color membrane substrates, when the nontransparent deformation
When largest deformation occurs for layer, the thickness of the support member is more than the deformation layer peak and the array substrate neighbour coloured silk film
The distance of substrate side.
8. display panel according to claim 7, which is characterized in that further include：
It is set to the antistatic transparency conducting layer that the color membrane substrates deviate from the array substrate side.
9. a kind of production method of array substrate, which is characterized in that including：
Form the first film transistor of each pixel unit in multiple pixel units, the second thin film transistor (TFT) and positioned at every
The first data line and the second data line of a pixel unit both sides；
Transparent reference layer is sequentially formed in each pixel unit and above the transparent reference layer and with it is described transparent
The nontransparent deformation layer of reference layer insulation；
Wherein, the output end of the first film transistor is electrically connected with the transparent reference layer, input terminal with it is corresponding described
First data line is electrically connected, and control terminal is electrically connected with corresponding scan line；The output end of second thin film transistor (TFT) with it is described
Nontransparent deformation layer electrical connection, input terminal are electrically connected with corresponding second data line, control terminal and the corresponding scanning
Line is electrically connected；According to the voltage difference of itself and the transparent reference layer elastic deformation occurs for the nontransparent deformation layer, to change
State area coverage of the nontransparent deformation layer to the transparent reference layer；
The production method of the array substrate further includes：
Form a plurality of reference potential line, the transparent reference layer and the nontransparent deformation layer insulate with the reference potential line and
Part is overlapping；Or
Protective layer and a plurality of reference potential line are formed, the protective layer covers the subregion of the nontransparent deformation layer, described
Transparent reference layer and the protective layer insulate with the reference potential line and part is overlapping.
10. according to the method described in claim 9, it is characterized in that, in forming multiple pixel units each pixel unit
First film transistor, the second thin film transistor (TFT) and the first data line and the second data positioned at each pixel unit both sides
After line, transparent reference layer is sequentially formed in each pixel unit and above the transparent reference layer and with it is described
Before the nontransparent deformation layer of bright reference layer insulation, further include：
In film layer where the first film transistor, second thin film transistor (TFT) and the first data line and the second data line
Top forms insulating layer, and forms output end and second film crystalline substance that insulating layer via exposes the first film transistor
The output end of body pipe；The output end of the first film transistor is electrically connected by insulating layer via with the transparent reference layer,
The output end of second thin film transistor (TFT) is electrically connected by insulating layer via with the nontransparent deformation layer.
11. according to the method described in claim 9, it is characterized in that, in forming multiple pixel units each pixel unit
First film transistor, the second thin film transistor (TFT) and the first data line and the second data positioned at each pixel unit both sides
After line, transparent reference layer is sequentially formed in each pixel unit and above the transparent reference layer and with it is described
Before the nontransparent deformation layer of bright reference layer insulation, further include：
In film layer where the first film transistor, second thin film transistor (TFT) and the first data line and the second data line
Top forms planarization layer, and forms planarization layer via and expose the output end of the first film transistor and described second thin
The output end of film transistor；The output end of the first film transistor passes through planarization layer via and transparent reference layer electricity
Connection, the output end of second thin film transistor (TFT) are electrically connected by planarization layer via with the nontransparent deformation layer.
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| CN101726893A (en) * | 2008-10-28 | 2010-06-09 | 乐金显示有限公司 | Horizontal electric field liquid crystal display |
| WO2012165745A1 (en) * | 2011-06-01 | 2012-12-06 | 한국과학기술원 | Display device |
| CN103926755A (en) * | 2013-12-30 | 2014-07-16 | 厦门天马微电子有限公司 | Display and manufacturing method thereof |
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| US5781331A (en) * | 1997-01-24 | 1998-07-14 | Roxburgh Ltd. | Optical microshutter array |
| CN101726893A (en) * | 2008-10-28 | 2010-06-09 | 乐金显示有限公司 | Horizontal electric field liquid crystal display |
| WO2012165745A1 (en) * | 2011-06-01 | 2012-12-06 | 한국과학기술원 | Display device |
| CN103926755A (en) * | 2013-12-30 | 2014-07-16 | 厦门天马微电子有限公司 | Display and manufacturing method thereof |
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