CN105227296B - A kind of manufacturing method and device of the 3D crypto chip of error resilience mistake injection attacks - Google Patents
A kind of manufacturing method and device of the 3D crypto chip of error resilience mistake injection attacks Download PDFInfo
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Abstract
The present invention provides manufacturing methods and device that a kind of error resilience misses the 3D crypto chip of injection attacks, are related to the security technology area of 3D crypto chip.This method comprises: error injection attack method corresponding to the cryptographic algorithm according to used by cryptochannel determines the sensitive and logical unit in cryptochannel；Cryptochannel is subjected to 3D distinguishing hierarchy, the 3D cryptochannel by sensitive and logical dividing elements to the middle layer in 3D level, after generating 3D distinguishing hierarchy；The easy overturning area type in region locating for sensitive and logical unit in 3D cryptochannel is determined according to the load particle mobility in 3D cryptochannel under the influence of by TSV and STI；It is inserted into corresponding sensor respectively at the sensitive and logical cell position in the easy Flip Zone PMOS, the easy Flip Zone NMOS or random Flip Zone, completes the safety manufacture of 3D crypto chip.It is weaker that the present invention solves the problems, such as that current 3D crypto chip resists the ability that error injection is attacked.
Description
Technical field
The present invention relates to the 3D passwords that the security technology area of 3D crypto chip more particularly to a kind of error resilience miss injection attacks
The manufacturing method and device of chip.
Background technique
Currently, TSV technology just will collection with the development of through silicon via technology (Through Silicon Vias, abbreviation TSV)
3 D stereo (3D) trend is gone to by plane trend at the interconnection line of circuit, forms three-dimensional interconnection architecture.Three-dimensional interconnection structure pair
The utilization rate in space shortens interconnection delay and power consumption to reduce interconnection length in itself better than planar structure,
To reduce the delay and power consumption of entire circuit.Crypto chip belongs to a very important branch in IC industry,
It is widely used in the occasion to sensitive information need for confidentiality, such as PC, network router, bank card, E-Passport etc..
However, one side is close since distribution of the sensing unit in 3D chip on 3D chip will affect error injection attack
The success or not (sensing unit for being distributed in middle layer is comparatively safe) of code chip, another aspect TSV and shallow trench isolation
(Shallow Trench Isolation, abbreviation STI) also results in error injection attack method to particle mobility influence is carried
With the difference of safety reinforcement means.Obviously, this will bring huge challenge to the manufacture of the 3D crypto chip based on TSV.
The existing invention of industry at present is all only interconnected to TSV in 3D integrated circuit and the optimization of layout, not by security consideration
Into the manufacture of 3D crypto chip, the ability for causing current 3D crypto chip to resist error injection attack is weaker.
Summary of the invention
The embodiment of the present invention provides the manufacturing method and device of a kind of 3D crypto chip of error resilience mistake injection attacks, with solution
Certainly current 3D crypto chip is made without the safety for considering that it resists error injection attack, causes current 3D code core
The weaker problem of the ability of piece resistance error injection attack.
In order to achieve the above objectives, the present invention adopts the following technical scheme:
A kind of manufacturing method of the 3D crypto chip of error resilience mistake injection attacks characterized by comprising
Error injection attack method corresponding to the cryptographic algorithm according to used by cryptochannel determines in cryptochannel
Sensitive and logical unit；
The cryptochannel is subjected to 3D distinguishing hierarchy, by the sensitive and logical dividing elements to the centre in 3D level
Layer, the 3D cryptochannel after generating 3D distinguishing hierarchy；
Determine that sensitivity is patrolled in 3D cryptochannel according to the load particle mobility in 3D cryptochannel under the influence of by TSV and STI
Collect the easy overturning area type in region locating for unit；The easy overturning region include: the easy Flip Zone PMOS, the easy Flip Zone NMOS and
Random Flip Zone；
It is inserted at the sensitive and logical cell position in the easy Flip Zone the PMOS, the easy Flip Zone NMOS and random Flip Zone
Corresponding sensor completes the safety manufacture of 3D crypto chip.
Specifically, error injection attack method corresponding to the cryptographic algorithm according to used by cryptochannel determine it is close
Sensitive and logical unit in code circuit, comprising:
If the cryptographic algorithm is RSA Algorithm, determine that the private key register circuit in cryptochannel is sensitive and logical unit；
If the cryptographic algorithm is CRT-RSA algorithm, the Sp operation participated in RSA cryptographic algorithms in cryptochannel is determined
All logic units be sensitive and logical unit.
Specifically, the cryptochannel is carried out 3D distinguishing hierarchy, by the sensitive and logical dividing elements into 3D level
Middle layer, generate 3D distinguishing hierarchy after 3D cryptochannel, comprising:
Obtain the area and through silicon via of the area under the 2D chip mode of the cryptochannel, the through silicon via in cryptochannel
Number and the cryptochannel 3D chip number of plies to be divided；
According to the area under the 2D chip mode of the cryptochannel, the area and through silicon via of the through silicon via in cryptochannel
Number and the cryptochannel 3D chip number of plies to be divided determine 3D chip estimate minimum area:
Wherein, A3DMinimum area is estimated for the 3D chip；A2DFor the face under the 2D chip mode of the cryptochannel
Product；Nsub-layerFor the cryptochannel 3D chip number of plies to be divided；ATSVFor the area of through silicon via；NTSVFor the number of through silicon via.
Further, the cryptochannel is subjected to 3D distinguishing hierarchy, by the sensitive and logical dividing elements to 3D level
In middle layer, generate 3D distinguishing hierarchy after 3D cryptochannel, further includes:
Obtain the area A of all sensitive and logical unitsmodule；
Judge the area A of all sensitive and logical unitsmoduleWhether A is less than or equal to3D×(Nsub-layer-2)；
If Amodule≤A3D×(Nsub-layer- 2) the 3D chip, is estimated into minimum area A3DIt is determined as the 3D core
The practical minimum area of piece；
If Amodule>A3D×(Nsub-layer- 2), willIt is determined as the practical minimum area of the 3D chip.
Further, the cryptochannel is subjected to 3D distinguishing hierarchy, by the sensitive and logical dividing elements to 3D level
In middle layer, generate 3D distinguishing hierarchy after 3D cryptochannel, further includes:
Other circuits in the cryptochannel in addition to the sensitive and logical unit are divided according to TSV number optimisation strategy
It is fitted in each layer of 3D distinguishing hierarchy, wherein the area equation of each layer.
Specifically, the load particle mobility according in 3D cryptochannel under the influence of by TSV and STI determines 3D password electricity
The easy overturning area type in region locating for sensitive and logical unit in road, comprising:
According to the doping concentration of the NMOS tube in the region in 3D cryptochannel, the electricity determined under no stress influence is calculated
Transport factor μn(ND)；
Wherein, NDFor the doping concentration of the NMOS tube in the region in the 3D cryptochannel.
Further, the load particle mobility according in 3D cryptochannel under the influence of by TSV and STI determines 3D password
The easy overturning area type in region locating for sensitive and logical unit in circuit, further includes:
According to the doping concentration of the PMOS tube in the region in 3D cryptochannel, the sky determined under no stress influence is calculated
Cave mobility [mu]p(NA)；
Wherein, NAFor the doping concentration of the PMOS tube in the region in the 3D cryptochannel.
Further, the load particle mobility according in 3D cryptochannel under the influence of by TSV and STI determines 3D password
The easy overturning area type in region locating for sensitive and logical unit in circuit, further includes:
According to formula:
Determine the change rate of the electron mobility under stress influenceWherein, Δ μnFor affected by force
Under electron mobility variable quantity；For the electron mobility influenced by through silicon via change rate each
The sum in direction；For the change rate sum in all directions of the electron mobility influenced by shallow trench isolation；
According to formula:
Determine the change rate of the hole mobility under stress influenceWherein, Δ μpFor affected by force
Under hole mobility variable quantity；For the hole mobility influenced by through silicon via change rate each
The sum in direction；For the change rate sum in all directions of the hole mobility influenced by shallow trench isolation；
According to formula:
Determine the maximum charge for causing PMOS tube to overturn in 3D cryptochannel；Wherein, Qsig.PMOSCause PMOS tube to be described
The maximum charge of overturning；I'onIt is 3D cryptochannel under error injection, and has the leakage current under stress influence；IonFor 3D password
Circuit is under error injection, and without the leakage current under stress influence；kpFor constant；
According to formula:
Determine the maximum charge for causing NMOS tube to overturn in 3D cryptochannel；Wherein, Qsig.NMOSCause PMOS tube to be described
The maximum charge of overturning；I'onIt is 3D cryptochannel under error injection, and has the leakage current under stress influence；IonFor 3D password
Circuit is under error injection, and without the leakage current under stress influence；knFor constant；
CompareWithSize；
IfThen the region is the easy Flip Zone NMOS；
IfThen the region is the easy Flip Zone PMOS；
IfThen the region is random Flip Zone.
A kind of manufacturing device of the 3D crypto chip of error resilience mistake injection attacks, comprising:
Sensitive and logical unit determination unit, for error injection corresponding to the cryptographic algorithm according to used by cryptochannel
Attack method determines the sensitive and logical unit in cryptochannel；
3D distinguishing hierarchy unit draws the sensitive and logical unit for the cryptochannel to be carried out 3D distinguishing hierarchy
The middle layer in 3D level is assigned to, the 3D cryptochannel after generating 3D distinguishing hierarchy；
Easily overturning area determination unit, for according to the load particle mobility in 3D cryptochannel under the influence of by TSV and STI
Determine the easy overturning area type in region locating for sensitive and logical unit in 3D cryptochannel；The easy overturning region includes: PMOS
Easy Flip Zone, the easy Flip Zone NMOS and random Flip Zone；
3D crypto chip generation unit, in the easy Flip Zone the PMOS, the easy Flip Zone NMOS and random Flip Zone
Sensitive and logical cell position at be inserted into corresponding sensor respectively, complete the safety manufacture of 3D crypto chip.
Wherein, the sensitive and logical unit determination unit, is specifically used for:
When the cryptographic algorithm is RSA Algorithm, determine that the private key register circuit in cryptochannel is sensitive and logical list
Member；
When the cryptographic algorithm is CRT-RSA algorithm, the Sp fortune participated in RSA cryptographic algorithms in cryptochannel is determined
All logic units calculated are sensitive and logical unit.
Specifically, the 3D distinguishing hierarchy unit, comprising:
Data acquisition module, the area under 2D chip mode, the silicon in cryptochannel for obtaining the cryptochannel
The area of through-hole and the number of through silicon via and the cryptochannel 3D chip number of plies to be divided；
Minimum area computing module, under the 2D chip mode according to the cryptochannel area, in cryptochannel
The area of through silicon via and the number of through silicon via and the cryptochannel 3D chip number of plies to be divided determine estimating most for 3D chip
Small area:
Wherein, A3DMinimum area is estimated for the 3D chip；A2DFor the face under the 2D chip mode of the cryptochannel
Product；Nsub-layerFor the cryptochannel 3D chip number of plies to be divided；ATSVFor the area of through silicon via；NTSVFor the number of through silicon via.
Further, the 3D distinguishing hierarchy unit, further includes:
Sensitive and logical cellar area obtains module, for obtaining the area A of all sensitive and logical unitsmodule；
Judgment module, for judging the area A of all sensitive and logical unitsmoduleWhether A is less than or equal to3D×
(Nsub-layer-2)；
First division module, in Amodule≤A3D×(Nsub-layer- 2) when, the 3D chip is estimated into minimal face
Product A3DIt is determined as the practical minimum area of the 3D chip；
Second division module, in Amodule>A3D×(Nsub-layerIt -2), will whenIt is determined as the 3D core
The practical minimum area of piece.
In addition, the 3D distinguishing hierarchy unit, is specifically used for:
Other circuits in the cryptochannel in addition to the sensitive and logical unit are divided according to TSV number optimisation strategy
It is fitted in each layer of 3D distinguishing hierarchy, wherein the area equation of each layer.
In addition, the easy overturning area determination unit, is specifically used for:
According to the doping concentration of the NMOS tube in the region in 3D cryptochannel, the electricity determined under no stress influence is calculated
Transport factor μn(ND)；
Wherein, NDFor the doping concentration of the NMOS tube in the region in the 3D cryptochannel.
Further, the easy overturning area determination unit, is also used to:
According to the doping concentration of the PMOS tube in the region in 3D cryptochannel, the sky determined under no stress influence is calculated
Cave mobility [mu]p(NA)；
Wherein, NAFor the doping concentration of the PMOS tube in the region in the 3D cryptochannel.
Further, the easy overturning area determination unit, is also used to:
According to formula:
Determine the change rate of the electron mobility under stress influenceWherein, Δ μnFor affected by force
Under electron mobility variable quantity；For the electron mobility influenced by through silicon via change rate each
The sum in direction；For the change rate sum in all directions of the electron mobility influenced by shallow trench isolation；
According to formula:
Determine the change rate of the hole mobility under stress influenceWherein, Δ μpFor affected by force
Under hole mobility variable quantity；For the hole mobility influenced by through silicon via change rate each
The sum in direction；For the change rate sum in all directions of the hole mobility influenced by shallow trench isolation；
According to formula:
Determine the maximum charge for causing PMOS tube to overturn in 3D cryptochannel；Wherein, Qsig.PMOSCause PMOS tube to be described
The maximum charge of overturning；I'onIt is 3D cryptochannel under error injection, and has the leakage current under stress influence；IonFor 3D password
Circuit is under error injection, and without the leakage current under stress influence；kpFor constant；
According to formula:
Determine the maximum charge for causing NMOS tube to overturn in 3D cryptochannel；Wherein, Qsig.NMOSCause PMOS tube to be described
The maximum charge of overturning；I'onIt is 3D cryptochannel under error injection, and has the leakage current under stress influence；IonFor 3D password
Circuit is under error injection, and without the leakage current under stress influence；knFor constant；
CompareWithSize；
IfThen the region is the easy Flip Zone NMOS；
IfThen the region is the easy Flip Zone PMOS；
IfThen the region is random Flip Zone.
A kind of error resilience provided in an embodiment of the present invention misses the manufacturing method and device of the 3D crypto chip of injection attacks, first
Determine the sensitive and logical unit in cryptochannel；Later, the cryptochannel is subjected to 3D distinguishing hierarchy, by the sensitive and logical
3D cryptochannel of the dividing elements to the middle layer in 3D level, after generating 3D distinguishing hierarchy；According in 3D cryptochannel by TSV
The easy overturning region class in region locating for sensitive and logical unit in 3D cryptochannel is determined with the load particle mobility under the influence of STI
Type；It is inserted into respectively at the sensitive and logical cell position in the easy Flip Zone the PMOS, the easy Flip Zone NMOS and random Flip Zone
Corresponding sensor completes the safety manufacture of 3D crypto chip.In this way, the 3D crypto chip that the present invention is formed will infuse mistake
Enter the middle layer that the more sensitive sensitive and logical unit of attack is placed in 3D level, avoids it from directly being attacked by error injection, improve
The safety of 3D crypto chip；Meanwhile using quick in the easy Flip Zone PMOS, the easy Flip Zone NMOS or random Flip Zone
Sense is inserted into the mode of corresponding sensor at logic unit position respectively, avoids that energy is larger or longer wavelengths of laser is made
3D crypto chip is attacked for error injection attack source.The present invention improves the safety for resisting error injection attack of 3D crypto chip
Property, avoid the weaker problem of the ability of current 3D crypto chip resistance error injection attack.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention without any creative labor, may be used also for those of ordinary skill in the art
To obtain other drawings based on these drawings.
Fig. 1 provides a kind of flow chart of the manufacturing method of the 3D crypto chip of error resilience mistake injection attacks for the embodiment of the present invention
One；
Fig. 2 provides a kind of flow chart of the manufacturing method of the 3D crypto chip of error resilience mistake injection attacks for the embodiment of the present invention
Two；
Fig. 3 is formed by for the manufacturing method that the embodiment of the present invention provides a kind of 3D crypto chip that error resilience misses injection attacks
The structural schematic diagram of 3D crypto chip；
The structure that Fig. 4 provides a kind of manufacturing device of the 3D crypto chip of error resilience mistake injection attacks for the embodiment of the present invention is shown
It is intended to one；
The structure that Fig. 5 provides a kind of manufacturing device of the 3D crypto chip of error resilience mistake injection attacks for the embodiment of the present invention is shown
It is intended to two.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As shown in Figure 1, the embodiment of the present invention provides a kind of manufacturing method of the 3D crypto chip of error resilience mistake injection attacks, packet
It includes:
Error injection attack method corresponding to step 101, the cryptographic algorithm according to used by cryptochannel determines password
Sensitive and logical unit in circuit.
Cryptochannel is carried out 3D distinguishing hierarchy by step 102, by sensitive and logical dividing elements to the centre in 3D level
Layer, the 3D cryptochannel after generating 3D distinguishing hierarchy.
Step 103 determines 3D cryptochannel according to the load particle mobility in 3D cryptochannel under the influence of by TSV and STI
The easy overturning area type in region locating for middle sensitive and logical unit.
The easy overturning region includes: the easy Flip Zone PMOS, the easy Flip Zone NMOS and random Flip Zone.
Step 104, the sensitive and logical cell position in the easy Flip Zone PMOS, the easy Flip Zone NMOS or random Flip Zone
Place is inserted into corresponding sensor respectively, completes the safety manufacture of 3D crypto chip.
This is in the punishment of the sensitive and logical cell position in the easy Flip Zone PMOS, the easy Flip Zone NMOS or random Flip Zone
It is not inserted into corresponding sensor, may is that
In the easy Flip Zone insertion band pull-up resistor of PMOS, and driving force ratio forms the drive of the PMOS tube of sensitive and logical unit
The small PMOS tube of power, monitoring signals are drawn from source level；
In the easy Flip Zone insertion band pull-up resistor of NMOS, and driving force ratio forms the drive of the NMOS tube of sensitive and logical unit
The small NMOS tube of power, monitoring signals are drawn from drain；
In CMOS (complementary metal oxide semiconductor, the Complementary of random Flip Zone insertion driving force very little
Metal Oxide Semiconductor) it manages, monitoring signals are drawn from drain.
Wherein, NMOS tube is NMOS transistor (N-Metal-Oxide-Semiconductor, abbreviation NMOS), PMOS tube
For PMOS transistor (P-Metal-Oxide-Semiconductor, abbreviation PMOS).
A kind of error resilience provided in an embodiment of the present invention misses the manufacturing method of the 3D crypto chip of injection attacks, it is first determined close
Sensitive and logical unit in code circuit；Later, cryptochannel is subjected to 3D distinguishing hierarchy, by sensitive and logical dividing elements to 3D layers
Middle layer in secondary, the 3D cryptochannel after generating 3D distinguishing hierarchy；It is determined according to the load particle mobility in 3D cryptochannel
Easy overturning region in 3D cryptochannel；Sensitivity in the easy Flip Zone PMOS, the easy Flip Zone NMOS or random Flip Zone is patrolled
It collects and is inserted into corresponding sensor at cell position respectively, complete the safety manufacture of 3D crypto chip.In this way, what the present invention was formed
The sensitive and logical unit more sensitive to error injection attack is placed in the middle layer of 3D level by 3D crypto chip, avoids it directly
It is attacked by error injection, improves the safety of 3D crypto chip；Meanwhile using the sensitive and logical unit position in easily overturning region
The mode that place is inserted into corresponding sensor is set, avoids that energy is larger or longer wavelengths of laser is as error injection attack source
Attack 3D crypto chip.The present invention improves the safety for resisting error injection attack of 3D crypto chip, avoids current
The weaker problem of the ability of 3D crypto chip resistance error injection attack.
In order to make those skilled in the art be better understood by the present invention, a more specifically embodiment is set forth below,
As shown in Fig. 2, the embodiment of the present invention provides a kind of manufacturing method of the 3D crypto chip of error resilience mistake injection attacks, comprising:
Error injection attack method corresponding to step 201, the cryptographic algorithm according to used by cryptochannel determines password
Sensitive and logical unit in circuit.
Specifically, determining that the private key in cryptochannel is posted if cryptographic algorithm is RSA Algorithm (abbreviation RSA algorithm)
Latch circuit is sensitive and logical unit.And if cryptographic algorithm is CRT-RSA algorithm (Chinese remainder theorem-RSA, abbreviation CRT-
RSA), determine that all logic units for participating in the Sp operation in RSA cryptographic algorithms in cryptochannel are sensitive and logical unit.
Step 202, the area and silicon for obtaining the area under the 2D chip mode of cryptochannel, through silicon via in cryptochannel
The number and cryptochannel 3D chip of the through-hole number of plies to be divided.
3D crypto chip can be divided into multiple sub- chips of area equation, and the number of plies of the sub- chip is cryptochannel herein
The 3D chip number of plies to be divided.
Step 203, according to the area under the 2D chip mode of cryptochannel, the area and silicon of the through silicon via in cryptochannel
The number and cryptochannel 3D chip of the through-hole number of plies to be divided determine the minimum area of 3D chip.
Specifically, can pass through
It is calculated.Wherein, A3DMinimum area is estimated for 3D chip；A2DFor under the 2D chip mode of cryptochannel
Area；Nsub-layerFor the cryptochannel 3D chip number of plies to be divided；ATSVFor the area of through silicon via；NTSVFor the number of through silicon via.
Herein, due in the case where 3D distinguishing hierarchy, the area A of TSVTSV×NTSVRelative to the minimum area very little of 3D chip, because
This can be ignored, then has
Step 204, the area A for obtaining all sensitive and logical unitsmodule。
Step 205, the area A for judging all sensitive and logical unitsmoduleWhether A is less than or equal to3D×(Nsub-layer-2)。
If Amodule≤A3D×(Nsub-layer- 2) it, executes step 206: the 3D chip is estimated into minimum area A3DReally
It is set to the practical minimum area of the 3D chip.
If Amodule>A3D×(Nsub-layer- 2) step 207, is executed: willIt is determined as the reality of the 3D chip
Border minimum area.
Since the sensitive and logical unit for being present in middle layer is safer, it is placed on middle layer.The middle layer
Be in addition in 3D level top and the bottom other than, be hidden in intermediate sub- chip layer.
After step 206 and step 207, step 208 is continued to execute.
Step 208 divides other circuits in cryptochannel in addition to sensitive and logical unit according to TSV number optimisation strategy
It is fitted in each layer of 3D distinguishing hierarchy.
Wherein, the area equation of each layer.There are many TSV number optimisation strategies herein, generally optimizes mould by establishing TSV
Type searches out the optimal solution of TSV number.
Step 209, the doping concentration according to the NMOS tube in the region in 3D cryptochannel, calculating determination does not have stress shadow
Electron mobility μ under ringingn(ND)。
Wherein,
Wherein, NDFor the doping concentration of the NMOS tube in the region in 3D cryptochannel.
Step 210, the doping concentration according to the PMOS tube in the region in 3D cryptochannel, calculating determination does not have stress shadow
Hole mobility μ under ringingp(NA)。
Wherein,
Wherein, NAFor the doping concentration of the PMOS tube in the region in 3D cryptochannel.
Step 211, according to formula:
Determine the change rate of the electron mobility under stress influenceWherein, Δ μnFor affected by force
Under electron mobility variable quantity；For the electron mobility influenced by through silicon via change rate each
The sum in direction；For the change rate sum in all directions of the electron mobility influenced by shallow trench isolation；
And according to formula:
Determine the change rate of the hole mobility under stress influenceWherein, Δ μpFor affected by force
Under hole mobility variable quantity；For the hole mobility influenced by through silicon via change rate each
The sum in direction；For the change rate sum in all directions of the hole mobility influenced by shallow trench isolation.
Step 212, according to formula:
Determine the maximum charge for causing PMOS tube to overturn in 3D cryptochannel；Wherein, Qsig.PMOSCause PMOS tube to be described
The maximum charge of overturning；I'onIt is 3D cryptochannel under error injection, and has the leakage current under stress influence；IonFor 3D password
Circuit is under error injection, and without the leakage current under stress influence；kpFor constant.
And according to formula:
Determine the maximum charge for causing NMOS tube to overturn in 3D cryptochannel；Wherein, Qsig.NMOSCause PMOS tube to be described
The maximum charge of overturning；I'onIt is 3D cryptochannel under error injection, and has the leakage current under stress influence；IonFor 3D password
Circuit is under error injection, and without the leakage current under stress influence；knFor constant
Step 213 comparesWithSize.
IfThening follow the steps 214, determining the region is the easy Flip Zone NMOS.
IfThening follow the steps 215, determining the region is the easy Flip Zone PMOS.
IfThening follow the steps 216, determining the region is random Flip Zone.
It, can be in the easy Flip Zone PMOS, the easy Flip Zone NMOS or random Flip Zone after having determined easy overturning region
In sensitive and logical cell position at be inserted into corresponding sensor respectively, specifically can be such as:
In the easy Flip Zone insertion band pull-up resistor of PMOS, and driving force ratio forms the drive of the PMOS tube of sensitive and logical unit
The small PMOS tube of power, monitoring signals are drawn from source level.
In the easy Flip Zone insertion band pull-up resistor of NMOS, and driving force ratio forms the drive of the NMOS tube of sensitive and logical unit
The small NMOS tube of power, monitoring signals are drawn from drain.
In CMOS (complementary metal oxide semiconductor, the Complementary of random Flip Zone insertion driving force very little
Metal Oxide Semiconductor) it manages, monitoring signals are drawn from drain.
It is worth noting that the stress as caused by TSV and STI will lead to the variation for carrying particle mobility.And carry particle
Mobility relative size will affect the case where sensitivity register bit flipping under error injection, have direct influence to safety.TSV
Lateral stress have the effect of enhancing to the mobility of electrons and holes, it is but more than electronics to the enhancing in hole, and TSV
Longitudinal compressive stress enhance the mobility of electronics, reduce the mobility in hole.Shallow trench isolation (STI) will also cause phase
When big thermal and mechanical stress.The compression stress in the horizontal direction of STI will affect mobility, be that the master of enhancing hole mobility answers
Power, but electron mobility can be reduced.Carry particle specific size and it is actual doping and it is related with the relative position of TSV.Not
In the case where considering stress, the mobility for carrying particle is related with the concentration of doping.
Herein, the present invention is by taking a circuit scale is 700,000 cryptochannels as an example, to illustrate the feasibility of circuit.It should
It include RSA encryption/decryption module, the key parameter of RSA such as table 1 in cryptochannel.
Table 1:
Since the RSA is 1024, and public key e very little, by lowThe private key of position can recover completely
Private key herein can be by password electricity so need private key position at least more than 768 (3/4ths of i.e. 1024) to be protected
Road is divided into 3 sub- chips, and 1024 private key registers are totally placed in the chip of middle layer, use top-level metallic as TSV
Interconnection.Then layout design, the size of three chips are carried out to three sub- chips respectively with Cadence Encounter software
All be 4mm × 4mm, there is the interconnection line of 208 TSV between top layer chip and middle layer chip, middle layer and bottom chip it
Between have 2298 TSV interconnection lines.It, can be easily in corresponding position finally according to the relative position of TSV and sensitivity register
It is inserted into sensor and carries out security hardening design.
The manufacturing method that the error resilience provided through the embodiment of the present invention misses the 3D crypto chip of injection attacks is formed by 3D
Crypto chip can be as shown in Figure 3, wherein the 3D crypto chip is divided into 3 layers, respectively top layer, middle layer and bottom.
A kind of error resilience provided in an embodiment of the present invention misses the manufacturing method of the 3D crypto chip of injection attacks, it is first determined close
Sensitive and logical unit in code circuit；Later, the cryptochannel is subjected to 3D distinguishing hierarchy, the sensitive and logical unit is drawn
The middle layer in 3D level is assigned to, the 3D cryptochannel after generating 3D distinguishing hierarchy；According in 3D cryptochannel by TSV and STI
Under the influence of load particle mobility determine the easy overturning area type in region locating for sensitive and logical unit in 3D cryptochannel；Institute
It states and is inserted into corresponding biography respectively at the sensitive and logical cell position in the easy Flip Zone PMOS, the easy Flip Zone NMOS and random Flip Zone
Sensor completes the safety manufacture of 3D crypto chip.In this way, the 3D crypto chip that is formed of the present invention error injection will be attacked compared with
It is placed in the middle layer of 3D level for sensitive sensitive and logical unit, avoids it from directly being attacked by error injection, improves 3D password
The safety of chip；Meanwhile the sensitive and logical unit position in the easy Flip Zone PMOS, the easy Flip Zone NMOS or random Flip Zone
The place of setting is inserted into the mode of corresponding sensor respectively, avoids that energy is larger or longer wavelengths of laser is attacked as error injection
Hit source attack 3D crypto chip.The present invention improves the safety for resisting error injection attack of 3D crypto chip, avoids and works as
The weaker problem of the ability of preceding 3D crypto chip resistance error injection attack.
Corresponding to above-mentioned Fig. 1 and embodiment of the method shown in Fig. 2, as shown in figure 4, the embodiment of the present invention provides a kind of error resilience
The accidentally manufacturing device of the 3D crypto chip of injection attacks, comprising:
Sensitive and logical unit determination unit 31, can the note of mistake corresponding to the cryptographic algorithm according to used by cryptochannel
Enter attack method and determines sensitive and logical unit in cryptochannel.
Cryptochannel can be carried out 3D distinguishing hierarchy, by sensitive and logical dividing elements to 3D by 3D distinguishing hierarchy unit 32
Middle layer in level, the 3D cryptochannel after generating 3D distinguishing hierarchy.
Easily overturning area determination unit 33, can be according to the load particle migration in 3D cryptochannel under the influence of by TSV and STI
Rate determines the easy overturning area type in region locating for sensitive and logical unit in 3D cryptochannel.
The easy overturning region includes: the easy Flip Zone PMOS, the easy Flip Zone NMOS and random Flip Zone.
3D crypto chip generation unit 34, can be in the easy Flip Zone PMOS, the easy Flip Zone NMOS or random Flip Zone
Sensitive and logical cell position at be inserted into corresponding sensor respectively, complete the safety manufacture of 3D crypto chip.
Wherein, sensitive and logical unit determination unit 31, specifically can be with:
When cryptographic algorithm is RSA Algorithm, determine that the private key register circuit in cryptochannel is sensitive and logical unit；
When cryptographic algorithm is CRT-RSA algorithm, the Sp operation participated in RSA cryptographic algorithms in cryptochannel is determined
All logic units are sensitive and logical unit.
Specifically, as shown in figure 5,3D distinguishing hierarchy unit 32, may include:
Data acquisition module 321, the area under the 2D chip mode of available cryptochannel, the silicon in cryptochannel are logical
The area in hole and the number of through silicon via and the cryptochannel 3D chip number of plies to be divided.
Minimum area computing module 322, can according under the 2D chip mode of cryptochannel area, in cryptochannel
What the area of through silicon via and the number of through silicon via and the cryptochannel 3D chip number of plies to be divided determined 3D chip estimates minimum
Area:
Wherein, A3DMinimum area is estimated for 3D chip；A2DFor the area under the 2D chip mode of cryptochannel；
Nsub-layerFor the cryptochannel 3D chip number of plies to be divided；ATSVFor the area of through silicon via；NTSVFor the number of through silicon via.
Further, the 3D distinguishing hierarchy unit 32 can also include:
Sensitive and logical cellar area obtains module 323, the area A of available all sensitive and logical unitsmodule。
Judgment module 324, it can be determined that the area A of all sensitive and logical unitsmoduleWhether 3D chip is less than or equal to most
Small area A3D。
First division module 325, can be in Amodule≤A3D×(Nsub-layer- 2) when, the 3D chip is estimated into minimum
Area A3DIt is determined as the practical minimum area of the 3D chip.
Second division module 326, can be in Amodule>A3D×(Nsub-layerIt -2), will whenIt is determined as described
The practical minimum area of 3D chip.
It, specifically can be in addition, 3D distinguishing hierarchy unit 32:
Other circuits in cryptochannel in addition to sensitive and logical unit are assigned to 3D layers according to TSV number optimisation strategy
In each layer of secondary division, wherein the area equation of each layer.
In addition, as shown in figure 5, easy overturning area determination unit 33, it specifically can be with:
According to the doping concentration of the NMOS tube in the region in 3D cryptochannel, the electricity determined under no stress influence is calculated
Transport factor μn(ND)；
Wherein, NDFor the doping concentration of the NMOS tube in the region in 3D cryptochannel.
Further, easy overturning area determination unit 33, can be with:
According to the doping concentration of the PMOS tube in the region in 3D cryptochannel, the sky determined under no stress influence is calculated
Cave mobility [mu]p(NA)；
Wherein, NAFor the doping concentration of the PMOS tube in the region in 3D cryptochannel.
Further, easy overturning area determination unit 33, can be with:
According to formula:
Determine the change rate of the electron mobility under stress influenceWherein, Δ μnFor affected by force
Under electron mobility variable quantity；For the electron mobility influenced by through silicon via change rate each
The sum in direction；For the change rate sum in all directions of the electron mobility influenced by shallow trench isolation.
According to formula:
Determine the change rate of the hole mobility under stress influenceWherein, Δ μpFor affected by force
Under hole mobility variable quantity；For the hole mobility influenced by through silicon via change rate each
The sum in direction；For the change rate sum in all directions of the hole mobility influenced by shallow trench isolation.
According to formula:
Determine the maximum charge for causing PMOS tube to overturn in 3D cryptochannel；Wherein, Qsig.PMOSCause PMOS tube to be described
The maximum charge of overturning；I'onIt is 3D cryptochannel under error injection, and has the leakage current under stress influence；IonFor 3D password
Circuit is under error injection, and without the leakage current under stress influence；kpFor constant；
According to formula:
Determine the maximum charge for causing NMOS tube to overturn in 3D cryptochannel；Wherein, Qsig.NMOSCause PMOS tube to be described
The maximum charge of overturning；I'onIt is 3D cryptochannel under error injection, and has the leakage current under stress influence；IonFor 3D password
Circuit is under error injection, and without the leakage current under stress influence；knFor constant；
CompareWithSize；
IfThen the region is the easy Flip Zone NMOS；
IfThen the region is the easy Flip Zone PMOS；
IfThen the region is random Flip Zone.
It is worth noting that error resilience provided in an embodiment of the present invention misses the manufacturing device of the 3D crypto chip of injection attacks
Specific implementation may refer to above-mentioned Fig. 1,2 corresponding embodiments of the method, and details are not described herein again.
A kind of error resilience provided in an embodiment of the present invention misses the manufacturing device of the 3D crypto chip of injection attacks, it is first determined close
Sensitive and logical unit in code circuit；Later, the cryptochannel is subjected to 3D distinguishing hierarchy, the sensitive and logical unit is drawn
The middle layer in 3D level is assigned to, the 3D cryptochannel after generating 3D distinguishing hierarchy；According in 3D cryptochannel by TSV and STI
Under the influence of load particle mobility determine the easy overturning area type in region locating for sensitive and logical unit in 3D cryptochannel；Institute
It states and is inserted into corresponding biography respectively at the sensitive and logical cell position in the easy Flip Zone PMOS, the easy Flip Zone NMOS and random Flip Zone
Sensor completes the safety manufacture of 3D crypto chip.In this way, the 3D crypto chip that is formed of the present invention error injection will be attacked compared with
It is placed in the middle layer of 3D level for sensitive sensitive and logical unit, avoids it from directly being attacked by error injection, improves 3D password
The safety of chip；Meanwhile using the sensitive and logical list in the easy Flip Zone PMOS, the easy Flip Zone NMOS or random Flip Zone
The mode of corresponding sensor is inserted at first position respectively, avoids that energy is larger or longer wavelengths of laser is as mistake note
Enter attack source attack 3D crypto chip.The present invention improves the safety for resisting error injection attack of 3D crypto chip, avoids
Current 3D crypto chip resists the weaker problem of ability of error injection attack.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the present invention
Apply the form of example.Moreover, it wherein includes the computer of computer usable program code that the present invention, which can be used in one or more,
The computer program implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) produces
The form of product.
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that the instruction generation executed by computer or the processor of other programmable data processing devices can be real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction offer executed on other programmable devices may be implemented in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Specific embodiment is applied in the present invention, and principle and implementation of the present invention are described, above embodiments
Explanation be merely used to help understand method and its core concept of the invention；At the same time, for those skilled in the art,
According to the thought of the present invention, there will be changes in the specific implementation manner and application range, in conclusion in this specification
Appearance should not be construed as limiting the invention.
Claims (16)
1. the manufacturing method that a kind of error resilience misses the 3D crypto chip of injection attacks characterized by comprising
Error injection attack method corresponding to the cryptographic algorithm according to used by cryptochannel determines the sensitivity in cryptochannel
Logic unit；
The cryptochannel is subjected to 3D distinguishing hierarchy, it is raw by the sensitive and logical dividing elements to the middle layer in 3D level
At the 3D cryptochannel after 3D distinguishing hierarchy；
It is determined in 3D cryptochannel according to the load particle mobility in 3D cryptochannel under the influence of by through silicon via and shallow trench isolation
The easy overturning area type in region locating for sensitive and logical unit；The easy overturning region includes: that the easy Flip Zone PMOS, NMOS are easily turned over
Turn area and random Flip Zone；
It is inserted into respectively at the sensitive and logical cell position in the easy Flip Zone the PMOS, the easy Flip Zone NMOS and random Flip Zone
Corresponding sensor completes the safety manufacture of 3D crypto chip.
2. the manufacturing method that error resilience according to claim 1 misses the 3D crypto chip of injection attacks, which is characterized in that described
Error injection attack method corresponding to the cryptographic algorithm according to used by cryptochannel determines the sensitive and logical in cryptochannel
Unit, comprising:
If the cryptographic algorithm is RSA Algorithm, determine that the private key register circuit in cryptochannel is sensitive and logical unit；
If the cryptographic algorithm is CRT-RSA algorithm, the institute for participating in the Sp operation in RSA cryptographic algorithms in cryptochannel is determined
Having logic unit is sensitive and logical unit.
3. the manufacturing method that error resilience according to claim 2 misses the 3D crypto chip of injection attacks, which is characterized in that described
The cryptochannel is subjected to 3D distinguishing hierarchy, by the sensitive and logical dividing elements to the middle layer in 3D level, generates 3D
3D cryptochannel after distinguishing hierarchy, comprising:
Obtain the number of the area under the 2D chip mode of the cryptochannel, the area of the through silicon via in cryptochannel and through silicon via
Mesh and the cryptochannel 3D chip number of plies to be divided；
According to the area under the 2D chip mode of the cryptochannel, the number of the area of the through silicon via in cryptochannel and through silicon via
What mesh and the cryptochannel 3D chip number of plies to be divided determined 3D chip estimates minimum area:
Wherein, A3DMinimum area is estimated for the 3D chip；A2DFor the area under the 2D chip mode of the cryptochannel；
Nsub-layerFor the cryptochannel 3D chip number of plies to be divided；ATSVFor the area of through silicon via；NTSVFor the number of through silicon via.
4. the manufacturing method that error resilience according to claim 3 misses the 3D crypto chip of injection attacks, which is characterized in that described
The cryptochannel is subjected to 3D distinguishing hierarchy, by the sensitive and logical dividing elements to the middle layer in 3D level, generates 3D
3D cryptochannel after distinguishing hierarchy, further includes:
Obtain the area A of all sensitive and logical unitsmodule；
Judge the area A of all sensitive and logical unitsmoduleWhether A is less than or equal to3D×(Nsub-layer-2)；
If Amodule≤A3D×(Nsub-layer- 2) the 3D chip, is estimated into minimum area A3DIt is determined as the reality of the 3D chip
Border minimum area；
If Amodule>A3D×(Nsub-layer- 2), willIt is determined as the practical minimum area of the 3D chip.
5. the manufacturing method that error resilience according to claim 4 misses the 3D crypto chip of injection attacks, which is characterized in that described
The cryptochannel is subjected to 3D distinguishing hierarchy, by the sensitive and logical dividing elements to the middle layer in 3D level, generates 3D
3D cryptochannel after distinguishing hierarchy, further includes:
Other circuits in the cryptochannel in addition to the sensitive and logical unit are divided according to through silicon via number optimisation strategy
It is fitted in each layer of 3D distinguishing hierarchy, wherein the area equation of each layer.
6. the manufacturing method that error resilience according to claim 5 misses the 3D crypto chip of injection attacks, which is characterized in that described
It is determined according to the load particle mobility in 3D cryptochannel under the influence of by through silicon via and shallow trench isolation sensitive in 3D cryptochannel
The easy overturning area type in region locating for logic unit, comprising:
According to the doping concentration of the NMOS tube in the region in 3D cryptochannel, calculates and determine that the electronics under no stress influence moves
Shifting rate μn(ND)；
Wherein, NDFor the doping concentration of the NMOS tube in the region in the 3D cryptochannel.
7. the manufacturing method that error resilience according to claim 6 misses the 3D crypto chip of injection attacks, which is characterized in that described
It is determined according to the load particle mobility in 3D cryptochannel under the influence of by through silicon via and shallow trench isolation sensitive in 3D cryptochannel
The easy overturning area type in region locating for logic unit, further includes:
According to the doping concentration of the PMOS tube in the region in 3D cryptochannel, calculates and determine that the hole under no stress influence is moved
Shifting rate μp(NA)；
Wherein, NAFor the doping concentration of the PMOS tube in the region in the 3D cryptochannel.
8. the manufacturing method that error resilience according to claim 7 misses the 3D crypto chip of injection attacks, which is characterized in that described
According to sensitive and logical in the load particle mobility 3D cryptochannel in 3D cryptochannel under the influence of by through silicon via and shallow trench isolation
The easy overturning area type in region locating for unit, further includes:
According to formula:
Determine the change rate of the electron mobility under stress influenceWherein, Δ μnFor under affected by force
The variable quantity of electron mobility；For the electron mobility influenced by through silicon via change rate in all directions
Sum；For the change rate sum in all directions of the electron mobility influenced by shallow trench isolation；
According to formula:
Determine the change rate of the hole mobility under stress influenceWherein, Δ μpFor under affected by force
The variable quantity of hole mobility；For the hole mobility influenced by through silicon via change rate in all directions
Sum；For the change rate sum in all directions of the hole mobility influenced by shallow trench isolation；
According to formula:
Determine the maximum charge for causing PMOS tube to overturn in 3D cryptochannel；Wherein, Qsig.PMOSPMOS tube is caused to overturn to be described
Maximum charge；I'onIt is 3D cryptochannel under error injection, and has the leakage current under stress influence；IonFor 3D cryptochannel
Under error injection, and without the leakage current under stress influence；kpFor constant；
According to formula:
Determine the maximum charge for causing NMOS tube to overturn in 3D cryptochannel；Wherein, Qsig.NMOSPMOS tube is caused to overturn to be described
Maximum charge；I'onIt is 3D cryptochannel under error injection, and has the leakage current under stress influence；IonFor 3D cryptochannel
Under error injection, and without the leakage current under stress influence；knFor constant；
CompareWithSize；
IfThen the region is the easy Flip Zone NMOS；
IfThen the region is the easy Flip Zone PMOS；
IfThen the region is random Flip Zone.
9. the manufacturing device that a kind of error resilience misses the 3D crypto chip of injection attacks characterized by comprising
Sensitive and logical unit determination unit is attacked for error injection corresponding to the cryptographic algorithm according to used by cryptochannel
Method determines the sensitive and logical unit in cryptochannel；
3D distinguishing hierarchy unit arrives the sensitive and logical dividing elements for the cryptochannel to be carried out 3D distinguishing hierarchy
Middle layer in 3D level, the 3D cryptochannel after generating 3D distinguishing hierarchy；
Easily overturning area determination unit, for according to the load particle in 3D cryptochannel under the influence of by through silicon via and shallow trench isolation
Mobility determines the easy overturning area type in region locating for sensitive and logical unit in 3D cryptochannel；The easy overturning region packet
It includes: the easy Flip Zone PMOS, the easy Flip Zone NMOS and random Flip Zone；
3D crypto chip generation unit, for quick in the easy Flip Zone the PMOS, the easy Flip Zone NMOS and random Flip Zone
Sense is inserted into corresponding sensor at logic unit position respectively, completes the safety manufacture of 3D crypto chip.
10. the manufacturing device that error resilience according to claim 9 misses the 3D crypto chip of injection attacks, which is characterized in that institute
Sensitive and logical unit determination unit is stated, is specifically used for:
When the cryptographic algorithm is RSA Algorithm, determine that the private key register in cryptochannel is sensitive and logical unit；
When the cryptographic algorithm is CRT-RSA algorithm, the institute that the Sp operation in RSA cryptographic algorithms is participated in cryptochannel is determined
Having logic unit is sensitive and logical unit.
11. the manufacturing device that error resilience according to claim 10 misses the 3D crypto chip of injection attacks, which is characterized in that institute
State 3D distinguishing hierarchy unit, comprising:
Data acquisition module, the area under 2D chip mode for obtaining the cryptochannel, the through silicon via in cryptochannel
Area and through silicon via number and cryptochannel 3D the chip number of plies to be divided；
Minimum area computing module, for the area under the 2D chip mode according to the cryptochannel, the silicon in cryptochannel
What the area of through-hole and the number of through silicon via and the cryptochannel 3D chip number of plies to be divided determined 3D chip estimates minimal face
Product:
Wherein, A3DMinimum area is estimated for the 3D chip；A2DFor the area under the 2D chip mode of the cryptochannel；
Nsub-layerFor the cryptochannel 3D chip number of plies to be divided；ATSVFor the area of through silicon via；NTSVFor the number of through silicon via.
12. the manufacturing device that error resilience according to claim 11 misses the 3D crypto chip of injection attacks, which is characterized in that institute
State 3D distinguishing hierarchy unit, further includes:
Sensitive and logical cellar area obtains module, for obtaining the area A of all sensitive and logical unitsmodule；
Judgment module, for judging the area A of all sensitive and logical unitsmoduleWhether A is less than or equal to3D×(Nsub-layer-
2)；
First division module, in Amodule≤A3D×(Nsub-layer- 2) when, the 3D chip is estimated into minimum area A3D
It is determined as the practical minimum area of the 3D chip；
Second division module, in Amodule>A3D×(Nsub-layerIt -2), will whenIt is determined as the 3D chip
Practical minimum area.
13. the manufacturing device that error resilience according to claim 12 misses the 3D crypto chip of injection attacks, which is characterized in that institute
3D distinguishing hierarchy unit is stated, is specifically used for:
Other circuits in the cryptochannel in addition to the sensitive and logical unit are divided according to through silicon via number optimisation strategy
It is fitted in each layer of 3D distinguishing hierarchy.
14. the manufacturing device that error resilience according to claim 13 misses the 3D crypto chip of injection attacks, which is characterized in that institute
Easily overturning area determination unit is stated, is specifically used for:
According to the doping concentration of the NMOS tube in the region in 3D cryptochannel, calculates and determine that the electronics under no stress influence moves
Shifting rate μn(ND)；
Wherein, NDFor the doping concentration of the NMOS tube in the region in the 3D cryptochannel.
15. the manufacturing device that error resilience according to claim 14 misses the 3D crypto chip of injection attacks, which is characterized in that institute
Easily overturning area determination unit is stated, is also used to:
According to the doping concentration of the PMOS tube in the region in 3D cryptochannel, calculates and determine that the hole under no stress influence is moved
Shifting rate μp(NA)；
Wherein, NAFor the doping concentration of the PMOS tube in the region in the 3D cryptochannel.
16. the manufacturing device that error resilience according to claim 15 misses the 3D crypto chip of injection attacks, which is characterized in that institute
Easily overturning area determination unit is stated, is also used to:
According to formula:
Determine the change rate of the electron mobility under stress influenceWherein, Δ μnFor under affected by force
The variable quantity of electron mobility；For the electron mobility influenced by through silicon via change rate in all directions
Sum；For the change rate sum in all directions of the electron mobility influenced by shallow trench isolation；
According to formula:
Determine the change rate of the hole mobility under stress influenceWherein, Δ μpFor under affected by force
The variable quantity of hole mobility；For the hole mobility influenced by through silicon via change rate in all directions
Sum；For the change rate sum in all directions of the hole mobility influenced by shallow trench isolation；
According to formula:
Determine the maximum charge for causing PMOS tube to overturn in 3D cryptochannel；Wherein, Qsig.PMOSPMOS tube is caused to overturn to be described
Maximum charge；I'onIt is 3D cryptochannel under error injection, and has the leakage current under stress influence；IonFor 3D cryptochannel
Under error injection, and without the leakage current under stress influence；kpFor constant；
According to formula:
Determine the maximum charge for causing NMOS tube to overturn in 3D cryptochannel；Wherein, Qsig.NMOSPMOS tube is caused to overturn to be described
Maximum charge；I'onIt is 3D cryptochannel under error injection, and has the leakage current under stress influence；IonFor 3D cryptochannel
Under error injection, and without the leakage current under stress influence；knFor constant；
CompareWithSize；
IfThen the region is the easy Flip Zone NMOS；
IfThen the region is the easy Flip Zone PMOS；
IfThen the region is random Flip Zone.
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| KR101066454B1 (en) * | 2010-12-15 | 2011-09-23 | 창신정보통신(주) | Side channel attack countermeasure device resistant to fault injection attack on the chip internal circuit and semiconductor chip including the same |
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