CN105226013B - Three-dimensional interconnection device of cellular insulating medium layer and preparation method thereof - Google Patents
Three-dimensional interconnection device of cellular insulating medium layer and preparation method thereof Download PDFInfo
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- CN105226013B CN105226013B CN201510617391.6A CN201510617391A CN105226013B CN 105226013 B CN105226013 B CN 105226013B CN 201510617391 A CN201510617391 A CN 201510617391A CN 105226013 B CN105226013 B CN 105226013B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
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Abstract
The invention discloses a kind of three-dimensional interconnection devices of cellular insulating medium layer, including：Chip, chip have annular deep hole；Electric conductor, electric conductor run through chip by annular deep hole；Cellular insulating medium layer, it is set in annular deep hole, and it is set between chip and electric conductor, wherein, cellular insulating medium layer be by can heat resolve the first high molecular material with can not heat resolve the porous structure that is generated by second high molecular material after making the decomposition of the first high molecular material by heating of the mixing high molecular material that is mixed to get according to preset ratio of the second high molecular material, to reduce the capacitance of three-dimensional interconnection, and alleviate the thermal stress generated by conductive thermal expansion.The three-dimensional interconnection device of the embodiment of the present invention can reduce the capacitance of three-dimensional interconnection, better ensure that the reliability of three-dimensional interconnection, simple and convenient.The invention also discloses a kind of preparation methods of the three-dimensional interconnection device of cellular insulating medium layer.
Description
Technical field
The present invention relates to 3-D technology field, more particularly to the three-dimensional interconnection device of a kind of cellular insulating medium layer and its
Preparation method.
Background technology
With the continuous reduction and the continuous increase of VLSI chip size of transistor feature size, mutually
Line delay has become the principal element for influencing circuit system delay.In addition, the power consumption of interconnection line is also more notable.
In the related technology, it is solved the above problems by three-dimensional integration technology, three-dimensionally integrated refers to by circuit function module point
Cloth is on different chips (can be the chip of different function, different process), three-dimensional stacked by bonding together to form by these chips
Structure, and using the three-dimensional interconnection (Through-Silicon-Via, TSV) for penetrating substrate realize different chip layers device it
Between be electrically connected, complete one or more functions jointly.It is three-dimensionally integrated that globally interconnected length can be greatly reduced, improve data
Transmission bandwidth reduces chip area, reduces power consumption, improve integrated level, realize heterogeneous integrated chip.
However, to realize three dimensional integrated circuits, it is necessary to realize and penetrate the three-dimensional interconnection of chip, this is three-dimensionally integrated core
Technology.The mainstream manufacturing technology of three-dimensional interconnection is realized based on blind hole at present, i.e., from chip front etching deep hole, then according to
Secondary deposition insulating medium layer, adhesion layer, diffusion impervious layer, copper seed layer recycle copper plating filling blind hole to realize conductor copper post,
It is thinned finally by back and realizes the three-dimensional interconnection for penetrating chip.Dielectric layer material used by three-dimensional interconnection is usually two
Silica.Its advantage is that manufacturing technology is ripe, thermodynamic property is stable, electrology characteristic research is abundant, but Jie of silica
Electric constant is larger, cause by three-dimensional interconnection conductor copper post, chip substrate and be clipped in that insulating medium layer between the two constitutes three
The capacitance for tieing up interconnection is larger, and the high frequency performance of three-dimensional interconnection can be influenced in frequency applications and generates larger power consumption.It is more important
, the coefficient of thermal expansion (0.5ppm) of silica and the coefficient of thermal expansion (2.5ppm) of silicon are much smaller than the coefficient of thermal expansion of copper
(18ppm), the serious deformation of thermal expansion generation of copper and stress, generate serious integrity problem when three-dimensional interconnection being caused to work
Even cause the fragmentation of silica dioxide medium layer and chip.
To solve the above-mentioned problems, the high molecular material substitution titanium dioxide that elasticity modulus is low, dielectric constant is small may be used
Insulating medium layer of the silicon as three-dimensional interconnection.The lower dielectric constant of high molecular material is conducive to reduce the capacitance of three-dimensional interconnection,
Its lower elasticity modulus makes it easier to deform simultaneously, alleviates copper post and thermally expands the thermal stress applied to substrate.However, macromolecule
The coefficient of thermal expansion higher (usual 50~100ppm) of material itself so that thermal stress issues not can be well solved.In recent years
There are the dielectric layer researched and proposed using the air gap as three-dimensional interconnection, the air gap that there is minimum dielectric constant and maximum journey
Degree allows the ability of copper post free wxpansion, can theoretically solve the problems, such as copper post thermal expansion and 3 D Interconnect Capacitance, but have
The conductor copper post of the three-dimensional interconnection of the air gap can only be supported by the planar dielectric layer of chip surface, bear vibration, impact
Ability is very low, seriously affects the reliability of three-dimensional interconnection.
Invention content
The present invention is directed to solve at least to a certain extent it is above-mentioned in the related technology the technical issues of one of.
For this purpose, an object of the present invention is to provide a kind of three-dimensional interconnection device of cellular insulating medium layer, the dress
The capacitance of three-dimensional interconnection can be reduced by setting, simple and convenient.
It is another object of the present invention to propose a kind of preparation side of the three-dimensional interconnection device of cellular insulating medium layer
Method.
In order to achieve the above objectives, one aspect of the present invention embodiment proposes a kind of three-dimensional interconnection of cellular insulating medium layer
Device, including：Chip, the chip have annular deep hole；Electric conductor, the electric conductor is by the annular deep hole through described
Chip；And cellular insulating medium layer, the cellular insulating medium layer is set in the annular deep hole, and is set to
Between the chip and the electric conductor, wherein the cellular insulating medium layer be by can heat resolve the first macromolecule
Material with can not the mixing high molecular material that is mixed to get according to preset ratio of the second high molecular material of heat resolve passing through
The porous structure that heating is generated after making first high molecular material decompose by the second high molecular material, to reduce three-dimensional interconnection
Capacitance, and alleviate the thermal stress generated by the conductive thermal expansion.
The three-dimensional interconnection device of the cellular insulating medium layer proposed according to embodiments of the present invention, can heat resolve by pair
The first high molecular material with can not the mixing high molecular material of the second high molecular material of heat resolve heated, make first
High molecular material decomposes, and cellular insulating medium layer is generated by the second high molecular material, to reduce the capacitance of three-dimensional interconnection, and
The thermal stress generated by conductive thermal expansion can be alleviated by cellular insulating medium layer, better ensure that three-dimensional interconnection can
It by property, and can ensure by electric conductor the intensity and reliability of three-dimensional interconnection structure, have more than entity high molecular material
The deformability of low dielectric constant and bigger, it is simple and convenient, it is easy to accomplish.
In addition, the three-dimensional interconnection device of cellular insulating medium layer according to the above embodiment of the present invention can also have such as
Under additional technical characteristic：
Preferably, in one embodiment of the invention, first high molecular material can be polynorbornene, poly- carbon
Acid esters and one kind in polypropylene carbonate.
Preferably, in one embodiment of the invention, second high molecular material can be polyimides, poly- methyl
One kind in methyl acrylate, benzocyclobutene and poly(p-phenylene terephthalamide).
Further, in one embodiment of the invention, the electric conductor can be cylindrical conducting body.
Further, in one embodiment of the invention, the cellular insulating medium layer is spongy macromolecule material
Material.
Further, in one embodiment of the invention, the cellular insulating medium layer is by heated under vacuum
The chip generates.
Another aspect of the present invention embodiment proposes a kind of preparation side of the three-dimensional interconnection device of cellular insulating medium layer
Method includes the following steps：According to preset ratio mixing can heat resolve the first high molecular material with can not heat resolve the
Two high molecular materials, to form mixing high molecular material；Annular deep hole is etched in chip front side, and in the annular deep hole
The mixing high molecular material is filled, and etches the silicon column that the removal annular deep hole surrounds and obtains to mix high molecular material
For the round deep hole of side wall；In the mixing high molecular material deposited on sidewalls diffusion barrier material and copper seed of round deep hole
Layer, and the round deep hole of electro-coppering filling manufactures plane to form electric conductor, and in chip surface in the round deep hole
Insulating medium layer and plane interconnection；It is bonded companion chip in the front of the chip by interim bonding method, from chip back
Thinned die manufactures planar insulative dielectric layer and plane interconnection, and go until exposing the electric conductor in the chip back
Except the companion chip；And the chip is heated under vacuum, it is high to decompose in the mixing high molecular material first
Molecular material realizes cellular insulating medium layer to generate the cellular insulating medium layer being made of the second high molecular material
Three-dimensional interconnection.
The preparation method of the three-dimensional interconnection device of the cellular insulating medium layer proposed according to embodiments of the present invention, by right
Can heat resolve the first high molecular material with can not heat resolve the second high molecular material mixing high molecular material carry out
Heating makes the first high molecular material decompose, and cellular insulating medium layer is generated by the second high molecular material, to reduce three-dimensional interconnection
Capacitance, and the thermal stress generated by conductive thermal expansion can be alleviated by cellular insulating medium layer, better ensured that
The reliability of three-dimensional interconnection, and can ensure by electric conductor the intensity and reliability of three-dimensional interconnection structure, have than entity
The deformability of high molecular material lower dielectric constant and bigger, it is simple and convenient, it is easy to accomplish.
In addition, the preparation method of the three-dimensional interconnection device of cellular insulating medium layer according to the above embodiment of the present invention is also
There can be following additional technical characteristic：
Preferably, in one embodiment of the invention, first high molecular material can be polynorbornene, poly- carbon
Acid esters and one kind in polypropylene carbonate.
Preferably, in one embodiment of the invention, second high molecular material can be polyimides, poly- methyl
One kind in methyl acrylate, benzocyclobutene and poly(p-phenylene terephthalamide).
The additional aspect of the present invention and advantage will be set forth in part in the description, and will partly become from the following description
Obviously, or practice through the invention is recognized.
Description of the drawings
The above-mentioned and/or additional aspect and advantage of the present invention will become in the description from combination following accompanying drawings to embodiment
Obviously and it is readily appreciated that, wherein：
Fig. 1 is the structural schematic diagram according to the three-dimensional interconnection device of the cellular insulating medium layer of the embodiment of the present invention；
Fig. 2 is the flow according to the preparation method of the three-dimensional interconnection device of the cellular insulating medium layer of the embodiment of the present invention
Figure；
Fig. 3 is the structural representation according to the three-dimensional interconnection device of the cellular insulating medium layer of one embodiment of the invention
Figure.
Fig. 4 is the chip structure schematic diagram for being had according to the manufacture of one embodiment of the invention annular deep hole；
Fig. 5 is according to filled high polymer mixture in the annular deep hole of one embodiment of the invention and to remove surface macromolecule
Chip structure schematic diagram after mixture redundancy；
Fig. 6 is that the chip structure after the silicon column surrounded according to the annular deep hole of etching removal of one embodiment of the invention is illustrated
Figure；
Fig. 7 is that the round deep hole of electro-coppering filling forms conductor copper post in round deep hole according to one embodiment of the invention
Chip structure schematic diagram afterwards；
Fig. 8 is the chip after chip surface manufactures insulating medium layer and plane interconnection according to one embodiment of the invention
Structural schematic diagram；
Fig. 9 is the interim bonding techniques of use according to one embodiment of the invention after chip front side is bonded companion chip
Chip structure schematic diagram；
Figure 10 is the slave chip back thinned die according to one embodiment of the invention, exposes the chip knot after conductor copper post
Structure schematic diagram；
Figure 11 is the core after chip back manufactures insulating medium layer and plane interconnection according to one embodiment of the invention
Chip architecture schematic diagram；
Figure 12 is the chip structure schematic diagram after the removal companion chip according to one embodiment of the invention；
Figure 13 is the heating chip under vacuum according to one embodiment of the invention, forms spongy cellular insulation
The three-dimensional interconnection structure schematic diagram of dielectric layer；
Figure 14 is the chip structure schematic diagram for being had according to the manufacture of one embodiment of the invention round deep hole；
Figure 15 is the core after round inner walls of deep holes coats Thin Polymer Mixture Films according to one embodiment of the invention
Chip architecture schematic diagram；
Figure 16 is that the round deep hole of electro-coppering filling forms conductive copper in round deep hole according to one embodiment of the invention
Chip structure schematic diagram after column；
Figure 17 is the core after chip surface manufactures insulating medium layer and plane interconnection according to one embodiment of the invention
Chip architecture schematic diagram；And
Figure 18 is the interim bonding techniques of use according to one embodiment of the invention after chip front side is bonded companion chip
Chip structure schematic diagram.
Specific implementation mode
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to for explaining the present invention, and is not considered as limiting the invention.
In addition, term " first ", " second " are used for description purposes only, it is not understood to indicate or imply relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more this feature.In the description of the present invention, the meaning of " plurality " is two or more,
Unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or be integrally connected；It can be machine
Tool connects, and can also be electrical connection；It can be directly connected, can also can be indirectly connected through an intermediary two members
Connection inside part.For the ordinary skill in the art, above-mentioned term can be understood in this hair as the case may be
Concrete meaning in bright.
In the present invention unless specifically defined or limited otherwise, fisrt feature the "upper" of second feature or "lower"
It may include that the first and second features are in direct contact, can also not be to be in direct contact but pass through it including the first and second features
Between other characterisation contact.Moreover, fisrt feature second feature " on ", " top " and " above " include first special
Sign is right over second feature and oblique upper, or is merely representative of fisrt feature level height and is higher than second feature.Fisrt feature exists
Second feature " under ", " lower section " and " following " include fisrt feature immediately below second feature and obliquely downward, or be merely representative of
Fisrt feature level height is less than second feature.
The three-dimensional interconnection device of cellular insulating medium layer proposed according to embodiments of the present invention is described with reference to the accompanying drawings
And preparation method thereof, the three-dimensional of the cellular insulating medium layer proposed according to embodiments of the present invention is described with reference to the accompanying drawings first mutually
Even device.Shown in referring to Fig.1, which includes：Chip 20, electric conductor 30 and cellular insulating medium layer 40.
Wherein, chip 20 has annular deep hole.Electric conductor 30 runs through chip 20 by annular deep hole.Cellular dielectric
Layer 40 is set in annular deep hole, and is set between chip 20 and electric conductor 30, wherein cellular insulating medium layer 40 is
By can heat resolve the first high molecular material with can not the second high molecular material of heat resolve mixed according to preset ratio
To mixing high molecular material generated by the second high molecular material after so that the first high molecular material is decomposed by heating it is porous
Structure to reduce the capacitance of three-dimensional interconnection, and is alleviated and thermally expands the thermal stress generated by electric conductor 30.The embodiment of the present invention
The capacitance of three-dimensional interconnection can be reduced, the deformability with more lower than entity high molecular material dielectric constant and bigger, more
Ensure the reliability of three-dimensional interconnection well.
It should be understood that preset ratio can be set by designer according to actual conditions.
Preferably, in one embodiment of the invention, the first high molecular material can be polynorbornene
(polynorbornene), makrolon (polycarbonate) and polypropylene carbonate (Poly propylene
Carbonate one kind in), the second high molecular material can be polyimides (Polyimide), polymethyl methacrylate
(Poly methylmethacrylate), benzocyclobutene (Benzocyclobutene) and poly(p-phenylene terephthalamide)
One kind in (poly p-phenylene terephthamide).
Further, in one embodiment of the invention, electric conductor 30 can be cylindrical conducting body, and cellular insulation is situated between
Matter layer 40 can be spongy high molecular material.
In addition, in one embodiment of the invention, heating chip 20 under vacuum, it is situated between with generating cellular insulation
Matter layer 40, in other words cellular insulating medium layer 40 generated by heated under vacuum chip 20, after heating, the first macromolecule
Material decomposes, and cellular insulating medium layer 40 is generated by the second high molecular material.
Specifically, the three-dimensional interconnection device 10 of the embodiment of the present invention can be by the post-like conductive through entire chip thickness
Body and the high-molecular porous shape insulating medium layer composition of annular sponge shape between chip and cylindrical conducting body.Spongy high score
Sub- cellular insulating medium layer using can heat resolve high molecular material and the mixing of heating nondecomposable high molecular material
Object manufacture around cylindrical conducting body annular dielectric layer, then to dielectric layer heating make can heat resolve high molecular material decompose,
It is formed and spongy high-molecular porous shape insulating medium layer is constituted by not heatable high molecular material.The embodiment of the present invention it is porous
Shape insulating medium layer can reduce the capacitance of three-dimensional interconnection, and alleviate cylindrical conductor thermal expansion stress pair three by porous medium layer
The influence of interlinking reliability is tieed up, while fixed and support drum electric conductor is to ensure the intensity and reliability of three-dimensional interconnection structure.
Wherein, in order to realize that the insulating medium layer between chip and cylindrical conducting body is spongy in a ring, in annular
In deep hole filling or the macromolecule mixture coated in round deep hole include can heat resolve high molecular material and heating
Nondecomposable high molecular material.Can heat resolve high molecular material can be polynorbornene, makrolon, poly- propylene carbonate
One kind in ester, and it can be polyimides, polymethyl methacrylate, benzocyclobutane to heat undecomposable high molecular material
One kind in alkene, poly(p-phenylene terephthalamide).In embodiments of the present invention can heat resolve high molecular material it is preferably poly-
Propene carbonate, it is preferably polyimides to heat undecomposable high molecular material.
The three-dimensional interconnection device of the cellular insulating medium layer proposed according to embodiments of the present invention, can heat resolve by pair
The first high molecular material with can not the mixing high molecular material of the second high molecular material of heat resolve heated so that
One high molecular material decomposes, and cellular insulating medium layer is generated by the second high molecular material, to reduce the capacitance of three-dimensional interconnection, and
And the thermal stress generated by conductive thermal expansion can be alleviated by cellular insulating medium layer, better ensure that three-dimensional interconnection
Reliability, and can ensure by electric conductor the intensity and reliability of three-dimensional interconnection structure, have than entity high molecular material
The deformability of lower dielectric constant and bigger, it is simple and convenient, it is easy to accomplish.
Secondly, the three-dimensional interconnection device of the cellular insulating medium layer proposed according to embodiments of the present invention is described with reference to the accompanying drawings
Preparation method.With reference to shown in Fig. 2, the preparation method of the embodiment of the present invention includes the following steps：
S201, according to preset ratio mixing can heat resolve the first high molecular material with can not heat resolve it is second high
Molecular material, to form mixing high molecular material.
In short, by can heat resolve high molecular material and the nondecomposable high molecular material of heating according to certain ratio
Example mixing forms two kinds into the macromolecule mixture being grouped as.
Preferably, in one embodiment of the invention, the first high molecular material can be polynorbornene, makrolon
With one kind in polypropylene carbonate, the second high molecular material can be polyimides, polymethyl methacrylate, benzocyclobutane
Alkene and one kind in poly(p-phenylene terephthalamide).
S202 etches annular deep hole in chip front side, and fills mixed sponge shape high molecular material in annular deep hole,
And it etches the silicon column that the annular deep hole of removal surrounds and obtains the round deep hole to mix high molecular material as side wall.
That is, etch annular deep hole in chip front side, in annular deep hole filling by can heat resolve macromolecule
The macromolecule mixture that material and the nondecomposable high molecular material of heating mix, the silicon that the annular deep hole of etching removal surrounds
Column is formed using macromolecule membrane as the round deep hole of side wall.
S203, in the mixing high molecular material deposited on sidewalls diffusion barrier material and copper seed layer of round deep hole, and
And the round deep hole of electro-coppering filling manufactures planar insulative dielectric layer to form electric conductor, and in chip surface in round deep hole
It is interconnected with plane.
S204 is bonded companion chip by interim bonding method in the front of chip, from chip back thinned die, until
Expose electric conductor, manufactures planar insulative dielectric layer and plane interconnection in chip back, and remove companion chip.
S205 heats chip under vacuum, and the first high molecular material in high molecular material is mixed to decompose, to generate
The cellular insulating medium layer being made of the second high molecular material realizes the three-dimensional interconnection of cellular insulating medium layer.
Specifically, heat chip under vacuum, make can heat resolve high molecular material decompose, it is remaining heating not
Decomposable high molecular material constitutes spongy cellular insulating medium layer, forms the three-dimensional of spongy cellular insulating medium layer
Interconnection.
In addition, in another embodiment of the present invention, the preparation method of the embodiment of the present invention can also be in chip surface
The round deep hole of etching.That is, the internal diameter of the annular deep hole of etching can be 0, i.e., round deep hole is etched in chip surface, and
The coating of round inner walls of deep holes by can heat resolve high molecular material and heat nondecomposable high molecular material and mix
Thin Polymer Mixture Films, it is similar with above-mentioned preparation method principle, in order to reduce redundancy, be not described in detail herein.
In an embodiment of the present invention, the insulating medium layer by using spongy high molecular material as three-dimensional interconnection,
Porosity characteristic makes the dielectric constant of high molecular material be less than entity high molecular material, can reduce the capacitance of three-dimensional interconnection；In addition,
Porous structure makes macromolecule medium layer be more easily deformed, and more free deformation space is provided for copper post thermal expansion, to reduce copper
Column thermally expands the stress generated to chip；Meanwhile copper post is fixed on the side wall of chip deep hole by insulating medium layer, is significantly carried
The mechanical strength and reliability of high three-dimensional interconnection structure.
To make those skilled in the art more fully understand the present invention, embodiment of the present invention is made into one below in conjunction with the accompanying drawings
Step ground detailed description.
Embodiment 1：
As shown in figure 3, the three-dimensional interconnection structure schematic diagram that present example provides.Including chip 200, cellular side wall is exhausted
Edge dielectric layer 201, cylindrical conducting body 202, integrated circuit transistor 203 that chip upper surface has been completed, metal interconnection 204,
Passivation layer 205, upper-surface interconnection line 101, surface insulation dielectric layer 100, chip back insulating medium layer 300, chip back is mutual
Line 301.
As shown in figure 4, carrying out photoetching using mask plate in 200 front of chip, the annular of three-dimensional interconnection structure is defined absolutely
Edge medium layer pattern, with reactive ion etching (RIE, Reactive Ion Etching) Etch Passivation 205, then using deep anti-
Ion etching (DIRE, Deep Reactive Ion Etch) technology is answered, the corresponding region etch of annular dielectric layer is gone out into depth
For 30~100 μm of annular deep hole 207.
As shown in figure 5, by can heat resolve high molecular material and the mixture that heats nondecomposable high molecular material
It is filled in annular deep hole 207, and is removed using chemically mechanical polishing (Chemical-Mechanical Polishing, CMP)
The surface redundancy of high molecular material forms macromolecule medium layer 206.
As shown in fig. 6, using the silicon column surrounded among DRIE etching macromolecule annulars dielectric layer 206, formed with high score
Sub- dielectric layer 206 is the round deep hole 208 of side wall, and etching depth is identical as annular deep hole, i.e., 30~100 μm.
As shown in fig. 7, sputter TiW and copper successively on the side wall of deep hole 208, as metal adhesion/diffusion impervious layer with
Copper seed layer.Using copper electroplating technology, electro-coppering filling deep hole, forms conductor copper post 202 in deep hole.Then, chemistry is utilized
The copper coating of mechanical polishing removal surface redundancy.
As shown in figure 8, in 200 front deposition silica dioxide medium layer 100 of chip, mask plate lithographic definition and three is reused
Tie up interconnection surface contact contact hole, be used in combination RIE etching silicon dioxides formed copper post contact hole, then using metal sputtering,
The aluminium plane interconnection 101 on 200 surface of photoetching and RIE etching manufacture chips.
As described in Figure 9, it is bonded glue 400 temporarily in chip front side spin coating using interim bonding techniques, it is interim using bonder
It is bonded companion chip 500.
As described in Figure 10, it is thinned from chip back using grinding and CMP technique, wafer thickness is thinned to 30~
100 μm, conductor copper post 202 is made to be exposed from chip back.
As shown in figure 11, in chip back deposition silica dioxide medium layer 300, photoetching and RIE etchings manufacture three are reused
The contact hole for tieing up interconnection, exposes the surface of conductor copper post.Then sputtering, photoetching and RIE etch metallic aluminium, form the flat of the back side
Face interconnection 301.
As shown in figure 12, the companion chip 500 being bonded temporarily is removed.
As shown in figure 13, chip is placed in vacuum chamber and is heated, while making polyimide curing, poly- propene carbonate heat
It decomposes.Poly- propene carbonate thermal decomposition product diffuses out dielectric layer by the silica dioxide medium layer of chip upper and lower surface, is formed
The polyimide media layer 201 of porous structure.
Embodiment 2：
As shown in figure 14, photoetching is carried out using mask plate in 200 front of chip, defines the circle three of three-dimensional interconnection structure
Interconnection structure figure is tieed up, with reactive ion etching (RIE, Reactive Ion Etching) Etch Passivation 205, then using deep
Reactive ion etching (DIRE, Deep Reactive Ion Etch) technology, goes out depth by the corresponding region etch of circular media layer
The annular deep hole 209 that degree is 30~100 μm.
As shown in figure 15, by can heat resolve high molecular material and the mixture that heats nondecomposable high molecular material
It is filled in annular deep hole 209, and is removed using chemically mechanical polishing (Chemical-Mechanical Polishing, CMP)
The surface redundancy of high molecular material forms macromolecule medium layer 210.
As shown in figure 16, TiW and copper are sputtered successively on the side wall of deep hole 209, as metal adhesion/diffusion impervious layer with
Copper seed layer.Using copper electroplating technology, electro-coppering filling deep hole, forms conductor copper post 202 in deep hole.Then, chemistry is utilized
The copper coating of mechanical polishing removal surface redundancy.
As shown in figure 17, in the front of chip 200 deposition silica dioxide medium layer 100, reuse mask plate lithographic definition with
The contact hole of three-dimensional interconnection surface contact, is used in combination RIE etching silicon dioxides to form the contact hole of copper post, is then splashed using metal
It penetrates, the aluminium plane interconnection 101 on 200 surface of photoetching and RIE etching manufacture chip
As described in Figure 18, it is bonded glue 400 temporarily in chip front side spin coating using interim bonding techniques, it is interim using bonder
It is bonded companion chip 500.
As shown in Figure 10~Figure 13, remaining step use with embodiment 1 just as technique, complete Figure 10 to Figure 13 work
Skill.
So far, the three of the cellular insulating medium layer of the embodiment of the present invention are realized respectively by embodiment 1 and embodiment 2
Tie up interconnection means.
The preparation method of the three-dimensional interconnection device of the cellular insulating medium layer proposed according to embodiments of the present invention, by right
Can heat resolve the first high molecular material with can not heat resolve the second high molecular material mixing high molecular material carry out
Heating generates cellular insulating medium layer so that the first high molecular material is decomposed by the second high molecular material, to reduce three-dimensional mutually
Capacitance even, and the thermal stress generated by conductive thermal expansion can be alleviated by cellular insulating medium layer, preferably protect
The reliability of three-dimensional interconnection is demonstrate,proved, and can ensure the intensity and reliability of three-dimensional interconnection structure by electric conductor, is had than reality
The deformability of body high molecular material lower dielectric constant and bigger, it is simple and convenient, it is easy to accomplish.
Any process described otherwise above or method description are construed as in flow chart or herein, and expression includes
It is one or more for realizing specific logical function or process the step of executable instruction code module, segment or portion
Point, and the range of the preferred embodiment of the present invention includes other realization, wherein can not press shown or discuss suitable
Sequence, include according to involved function by it is basic simultaneously in the way of or in the opposite order, to execute function, this should be of the invention
Embodiment person of ordinary skill in the field understood.
Expression or logic and/or step described otherwise above herein in flow charts, for example, being considered use
In the order list for the executable instruction for realizing logic function, may be embodied in any computer-readable medium, for
Instruction execution system, device or equipment (system of such as computer based system including processor or other can be held from instruction
The instruction fetch of row system, device or equipment and the system executed instruction) it uses, or combine these instruction execution systems, device or set
It is standby and use.For the purpose of this specification, " computer-readable medium " can any can be included, store, communicating, propagating or passing
Defeated program is for instruction execution system, device or equipment or the dress used in conjunction with these instruction execution systems, device or equipment
It sets.The more specific example (non-exhaustive list) of computer-readable medium includes following：Electricity with one or more wiring
Interconnecting piece (electronic device), portable computer diskette box (magnetic device), random access memory (RAM), read-only memory
(ROM), erasable edit read-only storage (EPROM or flash memory), fiber device and portable optic disk is read-only deposits
Reservoir (CDROM).In addition, computer-readable medium can even is that the paper that can print described program on it or other are suitable
Medium, because can be for example by carrying out optical scanner to paper or other media, then into edlin, interpretation or when necessary with it
His suitable method is handled electronically to obtain described program, is then stored in computer storage.
It should be appreciated that each section of the present invention can be realized with hardware, software, firmware or combination thereof.Above-mentioned
In embodiment, software that multiple steps or method can in memory and by suitable instruction execution system be executed with storage
Or firmware is realized.It, and in another embodiment, can be under well known in the art for example, if realized with hardware
Any one of row technology or their combination are realized：With the logic gates for realizing logic function to data-signal
Discrete logic, with suitable combinational logic gate circuit application-specific integrated circuit, programmable gate array (PGA), scene
Programmable gate array (FPGA) etc..
Those skilled in the art are appreciated that realize all or part of step that above-described embodiment method carries
Suddenly it is that relevant hardware can be instructed to complete by program, the program can be stored in a kind of computer-readable storage medium
In matter, which includes the steps that one or a combination set of embodiment of the method when being executed.
In addition, each functional unit in each embodiment of the present invention can be integrated in a processing module, it can also
That each unit physically exists alone, can also two or more units be integrated in a module.Above-mentioned integrated mould
The form that hardware had both may be used in block is realized, can also be realized in the form of software function module.The integrated module is such as
Fruit is realized in the form of software function module and when sold or used as an independent product, can also be stored in a computer
In read/write memory medium.
Storage medium mentioned above can be read-only memory, disk or CD etc..
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
Centainly refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any
One or more embodiments or example in can be combined in any suitable manner.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art are not departing from the principle of the present invention and objective
In the case of can make changes, modifications, alterations, and variations to the above described embodiments within the scope of the invention.
Claims (8)
1. a kind of three-dimensional interconnection device of cellular insulating medium layer, which is characterized in that including：
Chip, the chip have annular deep hole；
Electric conductor, the electric conductor run through the chip by the annular deep hole；And
Cellular insulating medium layer, the cellular insulating medium layer is set in the annular deep hole, and is set to described
Between chip and the electric conductor, wherein the cellular insulating medium layer be by can heat resolve the first high molecular material
With can not heat resolve the mixing high molecular material that is mixed to get according to preset ratio of the second high molecular material by heating
The porous structure generated by second high molecular material after making first high molecular material decompose, to reduce three-dimensional interconnection
Capacitance, and alleviate the thermal stress generated by the conductive thermal expansion, the cellular insulating medium layer is spongy high score
Sub- material.
2. the three-dimensional interconnection device of cellular insulating medium layer according to claim 1, which is characterized in that described first is high
Molecular material is one kind in polynorbornene, makrolon and polypropylene carbonate.
3. the three-dimensional interconnection device of cellular insulating medium layer according to claim 1, which is characterized in that described second is high
Molecular material is one kind in polyimides, polymethyl methacrylate, benzocyclobutene and poly(p-phenylene terephthalamide).
4. the three-dimensional interconnection device of cellular insulating medium layer according to claim 1, which is characterized in that the electric conductor
For cylindrical conducting body.
5. the three-dimensional interconnection device of cellular insulating medium layer according to claim 1, which is characterized in that the cellular
Insulating medium layer chip described in heated under vacuum generates.
6. a kind of preparation method of the three-dimensional interconnection device of cellular insulating medium layer, which is characterized in that include the following steps：
According to preset ratio mixing can heat resolve the first high molecular material with can not heat resolve the second high molecular material,
High molecular material is mixed to be formed；
Annular deep hole is etched in chip front side, and the mixing high molecular material is filled in the annular deep hole, and is carved
Etching off obtains the round deep hole to mix high molecular material as side wall except the silicon column that the annular deep hole surrounds；
In the mixing high molecular material deposited on sidewalls diffusion barrier material and copper seed layer of round deep hole, and in the circle
The round deep hole of electro-coppering filling manufactures planar insulative dielectric layer and plane to form electric conductor, and in chip surface in shape deep hole
Interconnection；
It is bonded companion chip in the front of the chip by interim bonding method, from chip back thinned die, until exposing
The electric conductor manufactures planar insulative dielectric layer and plane interconnection in the chip back, and removes the companion chip；With
And
The chip is heated under vacuum, to decompose the first high molecular material in the mixing high molecular material, to generate
The cellular insulating medium layer being made of the second high molecular material realizes the three-dimensional interconnection of cellular insulating medium layer.
7. the preparation method of the three-dimensional interconnection device of cellular insulating medium layer according to claim 6, which is characterized in that
First high molecular material is one kind in polynorbornene, makrolon and polypropylene carbonate.
8. the preparation method of the three-dimensional interconnection device of cellular insulating medium layer according to claim 7, which is characterized in that
Second high molecular material is polyimides, polymethyl methacrylate, benzocyclobutene and poly- paraphenylene terephthalamide to benzene two
One kind in amine.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006186003A (en) * | 2004-12-27 | 2006-07-13 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| CN101194356A (en) * | 2005-05-31 | 2008-06-04 | 先进微装置公司 | Technique for forming copper-containing lines embedded in low-k dielectric by providing a stiffening layer |
| CN101789417A (en) * | 2009-01-28 | 2010-07-28 | 台湾积体电路制造股份有限公司 | Through-silicon via sidewall isolation structure |
| CN103367280A (en) * | 2012-03-26 | 2013-10-23 | 南亚科技股份有限公司 | Through silicon via structure and manufacture method thereof |
| CN104576637A (en) * | 2013-10-17 | 2015-04-29 | 台湾积体电路制造股份有限公司 | 3D Integrated Circuit and Methods of Forming Same |
Family Cites Families (1)
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| JP2005142473A (en) * | 2003-11-10 | 2005-06-02 | Semiconductor Leading Edge Technologies Inc | Method of manufacturing semiconductor device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006186003A (en) * | 2004-12-27 | 2006-07-13 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| CN101194356A (en) * | 2005-05-31 | 2008-06-04 | 先进微装置公司 | Technique for forming copper-containing lines embedded in low-k dielectric by providing a stiffening layer |
| CN101789417A (en) * | 2009-01-28 | 2010-07-28 | 台湾积体电路制造股份有限公司 | Through-silicon via sidewall isolation structure |
| CN103367280A (en) * | 2012-03-26 | 2013-10-23 | 南亚科技股份有限公司 | Through silicon via structure and manufacture method thereof |
| CN104576637A (en) * | 2013-10-17 | 2015-04-29 | 台湾积体电路制造股份有限公司 | 3D Integrated Circuit and Methods of Forming Same |
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