CN105206529A - Fin-type field effect transistor and manufacturing method thereof - Google Patents
Fin-type field effect transistor and manufacturing method thereof Download PDFInfo
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- CN105206529A CN105206529A CN201410274226.0A CN201410274226A CN105206529A CN 105206529 A CN105206529 A CN 105206529A CN 201410274226 A CN201410274226 A CN 201410274226A CN 105206529 A CN105206529 A CN 105206529A
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Abstract
The present invention discloses a manufacturing method of a fin-type field effect transistor. The method comprises a step of forming a semiconductor substrate and forming fins, a gate dielectric layer, and a dummy gate on the substrate, a step of removing the dummy gate to form an opening, a step of filling the opening to form a metal gate stack, a step of removing the metal gate stack with a part of thickness on the fins in the opening to reform an opening, and a step of filling the above opening to form a top metal layer. According to the manufacturing method of the fin-type field effect transistor, the influence of metal gate stack hole filling is improved, at the same time, the resistance of a metal gate is reduced, and the performance of the device is improved.
Description
Technical field
The invention belongs to field of semiconductor manufacture, particularly relate to a kind of fin formula field effect transistor and manufacture method thereof.
Background technology
Along with the height of semiconductor device is integrated, MOSFET channel length constantly shortens, a series of in MOSFET long raceway groove model negligible effect become more remarkable, even become the leading factor affecting device performance, this phenomenon is referred to as short-channel effect.The electric property of short-channel effect meeting deterioration of device, as caused, threshold voltage of the grid declines, power consumption increases and degradation problem under signal to noise ratio.
In order to solve the problem of short-channel effect, propose the three-dimensional device architecture of fin formula field effect transistor (Fin-FET), Fin-FET is the transistor with fin channel structure, it utilizes several surfaces of thin fin as raceway groove, can operating current be increased, thus the short-channel effect in conventional transistor can be prevented.
Along with the continuous reduction of device size, the Fin-FET device of high-k/metal gate structure more and more becomes the emphasis in research.But when forming metal gate, because gate groove is very narrow, the filling of metal gate can be difficult to control, resistance can be very large, affects the performance of device.
Summary of the invention
The object of the invention is to overcome deficiency of the prior art, a kind of fin formula field effect transistor and manufacture method thereof are provided.
For achieving the above object, technical scheme of the present invention is:
A manufacture method for fin formula field effect transistor, comprising:
Semiconductor substrate is provided, described substrate is formed with fin and gate dielectric layer, dummy grid;
Remove dummy grid, to form opening;
Fill up opening stacking to form metal gate;
Remove on fin, open interior divides the metal gate of thickness stacking, again to form opening;
Again opening is filled up, to form metal layer at top.
Optionally, in the step removing dummy grid, remove the gate dielectric layer under dummy grid simultaneously, to form opening, and again form gate dielectric layer on opening inwall.
Optionally, the step forming metal gate stacking specifically comprises:
The inwall of opening forms the first metal layer, and described the first metal layer is work function regulating course;
Form diffusion impervious layer on the first metal layer;
Opening is filled up with the second metal level, stacking to form metal gate.
Optionally, described metal layer at top and the second metal level are same material.
Optionally, the metal gate heap superimposition divided in removal open interior is formed between metal layer at top, also comprises step:
The inwall of the opening again formed is formed the second diffusion impervious layer.
In addition, present invention also offers a kind of fin formula field effect transistor, comprise
Substrate, substrate is formed with fin;
The both sides of described fin are formed with opening;
At least in opening fin surface on the gate dielectric layer that formed;
The metal gate filling up lower opening portion formed in opening is stacking, and lower opening portion is higher than the height of fin;
Fill up the metal layer at top of upper opening portion.
Optionally, the inwall of opening is formed with gate dielectric layer.
Optionally, described metal gate is stacking comprises:
Be formed in the first metal layer on lower opening portion inwall;
Form the first diffusion impervious layer on the first metal layer;
Fill up the second metal level of lower opening portion.
Optionally, described metal layer at top and the second metal level are same material.
Optionally, described metal layer at top and the second metal level are same material.
Fin formula field effect transistor of the present invention and manufacture method thereof, formed in opening metal gate stacking after, further by stacking for the grid of upper opening portion removal, then carry out the filling of metal, thus improve the impact of the stacking pore filling of metal gate, meanwhile, reduce the resistance of metal gate, improve the performance of device.
Accompanying drawing explanation
In order to be illustrated more clearly in technical scheme of the invention process, be briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 shows the flow chart of the manufacture method of fin formula field effect transistor of the present invention;
Fig. 2-Figure 11 is the generalized section along fin direction grid in each manufacture process according to embodiment of the present invention manufacture fin formula field effect transistor.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
In order to understand the present invention better, the manufacture method below with reference to schematic diagram Fig. 2-11 pairs of embodiment of the present invention of flow chart Fig. 1 and the embodiment of the present invention is described in detail.All schematic cross-sections are all the schematic cross-sections along fin direction below.
First, substrate (scheming not shown) is provided.
In the present embodiment, described substrate is SOI substrate, and SOI substrate comprises at the bottom of backing, oxygen buried layer and top layer silicon.In other embodiments, described substrate can also be other substrat structures comprising semiconductor layer.
Then, in described substrate, form fin 100, shown in figure 2.
In the present embodiment, particularly, cap layers (scheming not shown) can be formed in top layer silicon, then graphical described cap layers, and be hard mask with cap layers, utilize lithographic technique, the such as method of RIE (reactive ion etching), etching top layer silicon, thus in top layer silicon, form fin 100, then, hard mask is removed further.
Then, described fin 100 forms gate dielectric layer 102 and dummy grid 104, as in Figure 2-4.
Particularly, form gate dielectric material, dummy grid material and hard mask material first respectively, as shown in Figure 3, gate dielectric layer can be thermal oxide layer or high K medium material etc., can be silicon dioxide in the present embodiment, can be formed by the method for thermal oxidation.Described dummy grid can be amorphous silicon, polysilicon etc., in the present embodiment, is amorphous silicon.Then, under the covering of hard mask, etching dummy grid material, forms the dummy grid 104 striding across fin.In the present embodiment, the silicon dioxide formed by thermal oxidation, as gate dielectric layer, is the stop-layer of follow-up formation side wall and dummy grid etching simultaneously.
Then, form side wall 106 at the sidewall of described dummy grid, and cover dummy grid both sides, to form interlayer dielectric layer 108, as shown in Figure 5.
Described side wall can have single or multiple lift structure, can by silicon nitride, silica, silicon oxynitride, carborundum, fluoride-doped silex glass, low k dielectric material and combination thereof, and/or other suitable materials are formed.In the present embodiment, side wall 106 is the silicon nitride spacer of individual layer.
Can by suitable deposition process deposit dielectric material, such as unadulterated silica (SiO
2), doping silica (as Pyrex, boron-phosphorosilicate glass etc.), silicon nitride (Si
3n
4) or other low k dielectric materials, then carry out planarization, such as CMP (chemico-mechanical polishing), until expose dummy grid, form described interlayer dielectric layer (ILD) 108, as shown in Figure 5.
Then, dummy grid 104 is removed, to form opening 110, as shown in Figure 6.
Dummy grid can use wet etching to remove, and in the present embodiment, removes amorphous silicon by Tetramethylammonium hydroxide (TMAH), thus, form opening 110 in the region of original dummy grid, as shown in Figure 6.
Then, in order to improve the quality of gate dielectric layer, further the gate dielectric layer under dummy grid can be removed, then, again new gate dielectric layer is formed, concrete, first can form boundary layer 112 in the opening, can be formed by the method for thermal oxidation, then, deposit layer of dielectric material 114, be such as high K medium material (such as, compare with silica, there is the material of high-k) or other suitable dielectric materials, high K medium material is hafnium base oxide such as, HFO2, HfSiO, HfSiON, HfTaO, HfTiO etc.
Then, in opening 110, metal gate is formed stacking, as shown in Figure 8.
Metal gate is stacked as the gate stack comprising metal level, can be such as Ti, TiAl
x, TiN, TaN
x, HfN, TiC
x, TaC
x, their combination such as polysilicon.
In the present embodiment, concrete, first, deposit the first metal layer 120, this first metal layer is work function regulating course, for NMOS, can select Al, TiAl, can select Ta, TaN for PMOS.Then, deposit diffusion impervious layer, to stop the diffusion of upper strata metal to the first metal layer and gate dielectric layer, the first diffusion impervious layer can be Ti layer 124, TiN layer 126, and then, carrying out the filling of the second metal level 128, such as, is W, as shown in Figure 7.Then, carry out planarization, such as, carry out cmp, until expose interlayer dielectric layer 108, thus, in opening 110, define metal gate stacking, as shown in Figure 8.
Then, remove on fin, open interior divides the metal gate of thickness stacking, again to form opening 130, as shown in Figure 9.
In the present embodiment, the metal gate of the segment thickness in the opening on the method for RIE (reactive ion etching) removal fin can be adopted stacking, the stacking removal of metal gate by upper opening portion, again forming section opening 130, in the present embodiment, remove gate dielectric layer 114, as shown in Figure 9 in etching simultaneously.
Then, again opening is filled up, to form metal layer at top 138, as shown in figure 11.
In the present embodiment, first, deposit second diffusion impervious layer, second diffusion impervious layer can be Ti layer 134, TiN layer 136, then, and deposit metal layer at top 138, this metal layer at top 138 adopts the material identical from the second metal level 128 or different materials, as W, as shown in Figure 10.Then, carry out planarization, such as, carry out cmp, until expose interlayer dielectric layer 108, thus again define metal layer at top 138 on the top of opening, as shown in figure 11.
So far, the fin formula field effect transistor that manufacturing method according to the invention is formed is defined.
In addition, present invention also offers the fin formula field effect transistor utilizing manufacture method of the present invention and embodiment to be formed.
With reference to shown in Figure 11, this fin formula field effect transistor comprises: substrate, substrate is formed with fin 100; The both sides of described fin are formed with opening 110; At least in opening fin surface on the gate dielectric layer 114 that formed; The metal gate filling up lower opening portion formed in opening is stacking, and lower opening portion is higher than the height of fin; Fill up the metal layer at top 138 of upper opening portion.
In the above-described embodiments, as shown in figure 11, the whole inwall of opening is formed with gate dielectric layer 114, this gate dielectric layer is high-k gate dielectric layer.
Described metal gate is stacking to be comprised: be formed in the first metal layer 120 on lower opening portion inwall; Form the first diffusion impervious layer 124,126 on the first metal layer; Fill up the second metal level 128 of lower opening portion.Described metal layer at top 138 is same material or different materials from the second metal level 128, such as, be W.
The second diffusion impervious layer 134,136 formed between the inwall and metal layer at top of upper opening portion.
The above is only preferred embodiment of the present invention, not does any pro forma restriction to the present invention.
Although the present invention discloses as above with preferred embodiment, but and be not used to limit the present invention.Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or be revised as the Equivalent embodiments of equivalent variations.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. a manufacture method for fin formula field effect transistor, is characterized in that, comprising:
Semiconductor substrate is provided, described substrate is formed with fin and gate dielectric layer, dummy grid;
Remove dummy grid, to form opening;
Fill up opening stacking to form metal gate;
Remove on fin, open interior divides the metal gate of thickness stacking, again to form opening;
Again opening is filled up, to form metal layer at top.
2. manufacture method according to claim 1, is characterized in that, in the step removing dummy grid, removes the gate dielectric layer under dummy grid simultaneously, to form opening, and again forms gate dielectric layer on opening inwall.
3. manufacture method according to claim 1, is characterized in that, the step forming metal gate stacking specifically comprises:
The inwall of opening forms the first metal layer, and described the first metal layer is work function regulating course;
Form diffusion impervious layer on the first metal layer;
Opening is filled up with the second metal level, stacking to form metal gate.
4. manufacture method according to claim 3, is characterized in that, described metal layer at top and the second metal level are same material.
5. manufacture method according to claim 1, is characterized in that, the metal gate heap superimposition divided in removal open interior is formed between metal layer at top, also comprises step:
The inwall of the opening again formed is formed the second diffusion impervious layer.
6. a fin formula field effect transistor, is characterized in that, comprising:
Substrate, substrate is formed with fin;
The both sides of described fin are formed with opening;
At least in opening fin surface on the gate dielectric layer that formed;
The metal gate filling up lower opening portion formed in opening is stacking, and lower opening portion is higher than the height of fin;
Fill up the metal layer at top of upper opening portion.
7. fin formula field effect transistor according to claim 6, is characterized in that, the inwall of opening is formed with gate dielectric layer.
8. fin formula field effect transistor according to claim 1, is characterized in that, described metal gate is stacking to be comprised:
Be formed in the first metal layer on lower opening portion inwall;
Form the first diffusion impervious layer on the first metal layer;
Fill up the second metal level of lower opening portion.
9. fin formula field effect transistor according to claim 8, is characterized in that, described metal layer at top and the second metal level are same material.
10. fin formula field effect transistor according to claim 1, is characterized in that, also comprises: the second diffusion impervious layer formed between the inwall and metal layer at top of upper opening portion.
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| CN201410274226.0A CN105206529A (en) | 2014-06-18 | 2014-06-18 | Fin-type field effect transistor and manufacturing method thereof |
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| US5783479A (en) * | 1997-06-23 | 1998-07-21 | National Science Council | Structure and method for manufacturing improved FETs having T-shaped gates |
| US5966597A (en) * | 1998-01-06 | 1999-10-12 | Altera Corporation | Method of forming low resistance gate electrodes |
| CN102214687A (en) * | 2010-04-07 | 2011-10-12 | 中国科学院微电子研究所 | Grid stack structure, semiconductor device and manufacturing methods of grid stack structure and semiconductor device |
| CN102810561A (en) * | 2011-06-02 | 2012-12-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN103325670A (en) * | 2012-03-20 | 2013-09-25 | 台湾积体电路制造股份有限公司 | Metal gate semiconductor device |
| CN103390638A (en) * | 2012-05-11 | 2013-11-13 | 三星电子株式会社 | Semiconductor device and fabricating method thereof |
| CN103426770A (en) * | 2012-05-18 | 2013-12-04 | 台湾积体电路制造股份有限公司 | Metal gate finFET device and method of fabricating same |
-
2014
- 2014-06-18 CN CN201410274226.0A patent/CN105206529A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5783479A (en) * | 1997-06-23 | 1998-07-21 | National Science Council | Structure and method for manufacturing improved FETs having T-shaped gates |
| US5966597A (en) * | 1998-01-06 | 1999-10-12 | Altera Corporation | Method of forming low resistance gate electrodes |
| CN102214687A (en) * | 2010-04-07 | 2011-10-12 | 中国科学院微电子研究所 | Grid stack structure, semiconductor device and manufacturing methods of grid stack structure and semiconductor device |
| CN102810561A (en) * | 2011-06-02 | 2012-12-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof |
| CN103325670A (en) * | 2012-03-20 | 2013-09-25 | 台湾积体电路制造股份有限公司 | Metal gate semiconductor device |
| CN103390638A (en) * | 2012-05-11 | 2013-11-13 | 三星电子株式会社 | Semiconductor device and fabricating method thereof |
| CN103426770A (en) * | 2012-05-18 | 2013-12-04 | 台湾积体电路制造股份有限公司 | Metal gate finFET device and method of fabricating same |
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Application publication date: 20151230 |