CN105187348B - Arbitrary velocity CPFSK signal timing synchronous method - Google Patents
Arbitrary velocity CPFSK signal timing synchronous method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
- H04L27/14—Demodulator circuits; Receiver circuits
- H04L27/144—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements
- H04L27/152—Demodulator circuits; Receiver circuits with demodulation using spectral properties of the received signal, e.g. by using frequency selective- or frequency sensitive elements using controlled oscillators, e.g. PLL arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
- H04L7/0276—Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0332—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with an integrator-detector
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Abstract
A kind of arbitrary velocity CPFSK signal timing synchronous method disclosed by the invention, is achieved by following technical proposals：MSD units are demodulated the baseband signal after resampling is handled, and feedback signal unit handles demodulation result, obtains feedback signal；Related operation unit carries out related operation to advanced, instant and hysteresis branch of the feedback signal respectively with CPFSK signals, and correlated results is sent into code ring discriminator after coherent integration, obtains phase demodulation information；Loop filter is filtered phase demodulation information, and filter result is sent into NCO；Resampling unit is adjusted integrating range under the control of NCO output enable signals, changes the phase of CPFSK signals, so as to achieve the purpose that Timing Synchronization.The present invention is obtained timing error by detecting likelihood function envelope, can be realized that accurate CPFSK signal timings are synchronous under low signal-to-noise ratio into line trace to code Doppler using delay lock ring structure using the advantage of MSD demodulation.
Description
Technical field
The present invention relates to a kind of Timing Synchronization technology of wireless communication field, more particularly to one kind to be based on multiple-symbol detection
(MSD) arbitrary velocity Continuous phase frequency shift keying (the Continuous Phrase Frequency Shift of decision-feedback
Key, CPFSK) modulated signal Timing Synchronization method.
Background technology
Continuous phase frequency shift keying (CPFSK) belongs to the special case of Continuous Phase Modulation (CPM).With traditional modulation not
Together, CPM modulated signals do not have SPA sudden phase anomalies at the time of symbol replaces, and can at utmost reduce spectrum width, meanwhile, CPM
Or constant enveloped modulation, it is insensitive to the nonlinear effect of power amplifier, it can significantly save transmission power.
The mode of traditional CPM signal generally use difference frequency discriminations is demodulated, although this mode is simple in structure, to because
Amplitude caused by multipath fading and the distortion in terms of phase have stronger antijamming capability, also easily by hardware realization.But should
Difference frequency discrimination method is since there are larger " threshold effect ", only after input signal-to-noise ratio reaches certain value, detector ability
Normal work.The Timing Synchronization of CPM signals is also a difficult point for realizing CPM system, since the phase that signal has in itself connects
The characteristics of continuous, do not have obvious amplitude transition, Timing Synchronization extraction relative difficulty between symbol and symbol.
Timing Synchronization is also bit synchronization, sign synchronization, is the element of communication system, i.e., produces one in receiving terminal
A clock signal identical with transmission bit or character rate, sentences for carrying out correctly sampling to the baseband signal after demodulation
Certainly, the influence of the factor such as noise and interference is eliminated.
The Performance Evaluating Indexes of Timing Synchronization mainly have：Static phase, shake, dislocation rate, settling time, the retention time,
Synchronous thresholding signal-to-noise ratio etc..Wherein static phase refers to inclined between the average phase of synchronizing signal and the phase of optimal sampling point
Difference, is mainly used for the synchronous precision of description；Shake refers to the synchronizing signal caused by the change of noise, and with the time to deviate its normal
The phenomenon of position, for describing synchronous stability；Dislocation rate refers to due to declining, disturbing or the reason such as send-receive clock error causes
Synchronizing pulse train deviate the frequency that original sequence phenomenon occurs, and a measurement index of stability；Settling time is
Since the reception signal containing bit synchronization information is into demodulator, synchronous extraction circuit exports normal bit synchronization signal in place
Untill needed for time, description synchronizing signal capture speed；Retention time is to disappear from the reception signal containing bit synchronization information
Mistake starts, and the time untill the normal bit synchronization signal interruption of synchronous extraction circuit output in place, describes to tie up synchronizing signal
The ability held；Synchronous thresholding signal-to-noise ratio refers on the premise of certain bit synchronization quality is ensured, receives the minimum that input terminal allows
Signal-to-noise ratio, this index embody adaptability of the bit synchronization to deep fade.
With the continuous improvement of CPFSK modulated data transmittings speed and operating distance, in order to lift demodulation performance,
William P.Osbome etc. propose MSD technologies for the demodulation of CPFSK signals.When receiving a symbol, do not stand
Make decisions, but by the signal waveform received and the related fortune of waveform progress that is locally stored in multiple symbol lengths
Calculate, symbol is adjudicated with this.MSD technologies are mutually tied with Turbo product codes (TPC) technology in the works in the advanced remote measurement in target range in the U.S.
Close, strengthen the performance of telemetry system.In theory, use the telemetry systems of this two technologies in the bit error rate under conditions of, compare
Original system can obtain the channel gain of nearly 9dB.Gain can be obtained using the system of MSD technologies, be so as to carrying out accurate
Timing Synchronization premised on.The environment of low signal-to-noise ratio proposes the time synchronization method of CPFSK signals new requirement.
Existing method carries out the extraction of phase demodulation information using single symbol period lead-lag likelihood detection algorithm, passes through loop
Filter circuit carries out clock regeneration, and controls lead-lag likelihood detection circuit by regeneration time clock, reaches the mesh of sign synchronization
's.However, be detected due to docking the collection of letters number respectively using local ' 1 ' and ' 0 ' likelihood detection sequence, under low signal-to-noise ratio
The phase demodulation curve arrived is not ideal enough, and net synchronization capability cannot meet the requirement of MSD demodulation.
The content of the invention
In order to solve the above-mentioned technical problem, the present invention is directed to arbitrary velocity Continuous phase frequency shift keying CPFSK modulated signals,
The advantage demodulated using MSD, there is provided one kind is based on MSD decision-feedbacks, and phase mistake is obtained by detecting likelihood function envelope
Poor information, still can be normal in the case where signal-to-noise ratio is relatively low using delay lock ring structure to code Doppler into line trace
The time synchronization method of work.
The above-mentioned purpose of the present invention can be reached by following measures, and a kind of arbitrary velocity CPFSK signal timings are synchronous
Method, includes the following steps：
1. arbitrarily than down-sampled：The arteries and veins in the range of whole sample clock frequency produced with improved digital controlled oscillator NCO
It is enable signal to rush signal, and arbitrary velocity Continuous phase frequency shift keying CPFSK baseband signals are appointed using resampling unit
The sampling rate of CPFSK baseband signals is reduced to D times of character rate, D is integer than down-sampled by meaning；
2.MSD decision-feedbacks：Using the existing multiple-symbol detection MSD units of receiving terminal to after down-sampled processing
CPFSK signals make decisions, by feedback signal unit using the conjugated signal of the corresponding CPFSK modulated signals of court verdict as
D CPFSK baseband signal data, in whole process, is first mapped as a symbol, then the symbol is mapped as by feedback signal
D feedback signal data；
It is 3. parallel related：Time delay module carries out delay process to the CPFSK signals after down-sampled processing, respectively obtains
In advance, instant and three branches of hysteresis, under the control of effective enable signal, three road signals carry out symbol week with feedback signal respectively
Parallel related operation in phase, coherent integration unit respectively carry out three road correlation results the correlation intergal of a period of time.
4. error-detecting：Three road coherent integration results are sent into code ring discriminator detection likelihood function envelope, obtain CPFSK letters
Number phase error information.
5. it is based on delay locked loop structural adjustment signal phase：Phase error information is filtered by loop filter
Ripple, filter result are sent into improved NCO, are added to obtain the control word of NCO with fixed accumulation amount by loop filter output, jointly
Control the frequency of NCO output signals；Then traditional numeric-control oscillator NCO is improved, when the control word of NCO is adopted more than system
During the half of sample clock frequency, traditional NCO pulse signals obtained are negated, frequency is obtained and is more than half sampling clock
The pulse signal of frequency；Integrate-dump of the pulse signal of NCO outputs at the same time as resampling unit enables and Timing Synchronization ring
Effective enable signal of other units, is adjusted the phase of CPFSK signals in road, and how general control Timing Synchronization loop is to code
Strangle into line trace.
The present invention has the advantages that compared with the prior art：
The present invention is directed to the CPFSK signals of arbitrary velocity, it is made decisions first with MSD technologies, then according to judgement
As a result feedback signal is obtained, the storage gain to add up using feedback signal after related to corresponding modulated signal, by detecting seemingly
Right function envelope obtains phase error information, relatively low in signal-to-noise ratio using delay lock ring structure to code Doppler into line trace
In the case of can still complete accurate Timing Synchronization.
The present invention is improved traditional NCO structures, enables to produce the arteries and veins in the range of whole sample clock frequency
Signal is rushed, resampling unit is using the pulse signal as enable signal, it is possible to achieve to any than down-sampled of CPFSK signals.NCO
Control word exported by loop filter and be added to obtain with fixed accumulation amount, fixed accumulated value is the integral multiple of character rate, NCO
The pulse signal of output at the same time as resampling unit integrate-dump enable with Timing Synchronization loop other units it is effective
Enable signal, is conducive to Timing Synchronization loop and is handled according to CPFSK symbol periods, improves Timing Synchronization precision.
The present invention obtains feedback signal using the court verdict of the existing MSD units of receiving terminal, extra hard without paying
Part Resources Consumption, the phase information of CPFSK signals is obtained by detecting likelihood function envelope, is aided in without data, is not increased and lead
Pin is drawn away, implementation complexity is low.
Brief description of the drawings
Fig. 1 is arbitrary velocity CPFSK signal timings synchronization structure circuit theory schematic diagram of the present invention.
Fig. 2 is the principle schematic of the step one in Fig. 1.
Fig. 3 is the principle schematic of the step two in Fig. 1.
Fig. 4 is the principle schematic of the step three in Fig. 1.
Fig. 5 is the principle schematic of the step four in Fig. 1.
Fig. 6 is the principle schematic of the step five in Fig. 1.
Fig. 7 is that the NCO in Fig. 1 improves circuit theory schematic diagram.
In figure：1 resampling unit, 2MSD units, 3 feedback signal units, 4 related operation units, 5 coherent integration units, 6
Code ring discriminator, 7 loop filters, 8 digital controlled oscillator NCO.
In figure：1 resampling unit, 2MSD units, 3 feedback signal units, 4 related operation units, 5 coherent integration units, 6
Code ring discriminator, 7 loop filters, 8 digital controlled oscillator NCO.
Embodiment
Invention is further illustrated with reference to the accompanying drawings and examples.
Refering to Fig. 1.Arbitrary velocity CPFSK signal timing synchronization structures based on MSD decision-feedbacks include：Resampling unit
1st, MSD units 2, feedback signal unit 3, related operation unit 4, coherent integration unit 5, code ring discriminator 6, loop filter 7
And digital controlled oscillator NCO8, wherein, CPFSK baseband signal of the resampling unit 1 according to the enable signal that NCO is exported to reception
Carry out any than down-sampled, the sampling rate of CPFSK baseband signals is reduced to the integral multiple of character rate；After resampling
Signal is sent into multiple-symbol detection MSD units 2, and court verdict is obtained using MSD technologies, feedback signal unit 3 to court verdict into
Row processing, obtains feedback signal；Related operation unit 4 to feedback signal respectively with CPFSK signals it is advanced, immediately and hysteresis three
Bar tributary signal carries out related operation；Correlated results is sent into code ring discriminator 6 after coherent integration unit 5, obtains phase demodulation letter
Breath；Loop filter 7 is filtered phase demodulation information, and filter result is sent into NCO8；NCO8 is with loop filter output and admittedly
Determine the sum of accumulation amount word in order to control, resampling unit (1) carries out integrating range under the control of NCO (8) output enable signals
Adjustment, changes the phase of CPFSK signals, realizes Timing Synchronization.
According to the present invention, the arbitrary velocity CPFSK signal timing synchronous method based on MSD decision-feedbacks, specific steps bag
Include：
Step 1, refering to Fig. 2.Arbitrarily than down-sampled：Resampling unit using CPFSK baseband signals as input, first with
Accumulator adds up input, then accumulation result is sampled when enable signal is effective to obtain output signal, at the same time
Accumulator is reset, this process is then circulated, completes the down-sampled operation to input signal.The step believes CPFSK base band
Number sampling rate be reduced to D times of character rate.
Step 2 refers to Fig. 3.MSD decision-feedbacks：The CPFSK signals obtained after resampling unit is down-sampled correspond to D data
Set (capitalization represents the set of the corresponding D data of a CPFSK symbol respectively) sequentially enter MSD units, MSD is mono-
Member makes decisions input signal according to symbol period, output symbol sequence is (small under the control of the enable signal of NCO outputs
The mother stock that writes does not represent a symbol), feedback signal unit under the control of the NCO enable signals exported, to each symbol into
Row processing, obtains feedback signal.Feedback signal unit therein is with the conjugated signal of the corresponding CPFSK modulated signals of court verdict
As feedback signal, due to symbol, the corresponding CPFSK signals in ' 0 ' and ' 1 ' are conjugated each other, and feedback signal can be by following two
Implementation obtains：
A. feedback signal unit first docks received symbol and is negated：Symbol ' 0 ' is changed into ' 1 ', symbol ' 1 ' is changed into ' 0 '；
Then, CPFSK modulation is carried out to symbol of the inverted, obtains feedback signal；
B. feedback signal directly docks received symbol and carries out CPFSK modulation, and conjugation is then taken to modulated signal, obtains anti-
Feedback signal.
MSD units just make decisions current sign after each N number of symbol before and after continuous observation, so except MSD is mono-
Outside the hardware delay that member and feedback signal unit are brought, there is N number of symbol period between feedback signal and corresponding CPFSK signals
Delay.Since initial phase is different, feedback signal is not conjugated each other with corresponding CPFSK signals, but still is met related
Operation result occurs the rule of maximum in phase alignment, can obtain phase error letter by detecting likelihood function envelope
Breath.
Refering to Fig. 4.It is parallel related：Parallel correlation step includes time delay module, complex multiplier, accumulator and correlation product
Subdivision, complex multiplier and accumulator therein form digital correlator.First, time delay module prolongs CPFSK signals
When operate, obtain it is advanced, immediately and hysteresis three branches, make a symbol it is corresponding immediately branch phase it is corresponding with the symbol
Feedback signal phase alignment, the phase d symbol period more advanced than the phase of instant branch of advanced branch, lags branch
Phase falls behind d symbol period than the phase of instant branch, and d represents digital correlator spacing.Then, three digital correlators point
Tri- road CPFSK signals of Bie Dui carry out complex multiplication operations with feedback signal.Then, accumulator is under enable signal control, every
Add up in a symbol period to complex multiplier output signal.Finally, coherent integration unit carries out length to correlated results
For coherent integration.Coherent integration can eliminate high frequency signal components and noise in signal, improve signal-to-noise ratio, gain is with being concerned with
The time of integration is directly proportional.
Refering to Fig. 5.Error-detecting：Three road coherent integration results are admitted to code ring discriminator, obtain the phase of CPFSK signals
Control information.Optional discriminator algorithm includes incoherent advanced subtracting hysteresis amplitude method, the incoherent advanced after-power method, seemingly of subtracting
Relevant dot product power method and relevant dot product power method etc..Every kind of method can be normalized.Normalization can remove amplitude sensitive
Property, improve performance of the loop under the conditions of signal-to-noise ratio quickly changes, help to make loop tracks and thresholding performance independent of AGC
Performance.
Power computation module, incoherent is included using the normalized incoherent advanced code ring discriminator for subtracting after-power method
Integral unit and error detection unit, wherein, power computation module seeks the coherent integration results of advanced branch and hysteresis branch
Power, non-coherent integration unit carry out the performance number of coherent integration results the non-coherent integration that length is, error detection unit
Phase error information is obtained using non-coherent integration results：
E (n) and L (n) represents advanced branch and lags the coherent integration results of branch respectively, is returned by what error-detecting obtained
One phase error changed is expressed as：
The identified result of current sign and the initial phase of the front and rear symbol of current sign and each symbol suffer from directly
Relation, the phase demodulation curve that distinct symbols obtain are different.Non-coherent integration module carries out the performance number of coherent integration results
Accumulation is added, the identified result of multiple symbols can be carried out smoothly, while can also offset the shake of grass, improves letter
Make an uproar ratio.Correlated results is zoomed in or out into multiple and does not interfere with signal-to-noise ratio and phase error information, in order to avoid in incoherent product
/ after link in occur numerical value overflow, coefficient 1/N can be multiplied by non-coherent integration resultscor 2Nnc。
Refering to Fig. 6.Based on delay locked loop structural adjustment signal phase：The step includes loop filter and improved
NCO, first, loop filter are filtered phase error signal, then, filter output signal and fixed accumulated value phase
Add, obtain the control word of NCO, finally, improved NCO adds up control word, can obtain the pulse signal of specific frequency,
The pulse signal at the same time as resampling unit integrate-dump enable with Timing Synchronization loop other units effectively enable
Signal, control Timing Synchronization loop accurately track code Doppler.The fixation accumulated value σ of NCO is character rate RbD
Times, i.e. σ=DRb。
Loop filter can reduce the shake of phase error signal, reduce the influence of high-frequency noise, carried for phase-locked loop
For a short-term memory, in system due to instantaneous noise and during losing lock, it is ensured that the rapid recapture signal of loop is, it can be achieved that right
The tracking of the code Doppler of dynamic change.Exponent number and noise bandwidth determine dynamic response of the loop filter to signal.This hair
Bright to be directed to different application environments, single order ring, second order loop or third order PLL may be selected in loop filter, is there is the system of frequency locking ring
In, the phase locked loop filter aided in by frequency locking ring can be selected.After selected filter order, it can be required according to receiver
The most weak signal of the intensity of receiving and highest user's dynamic stress of required support select an appropriate noise bandwidth.
Noise bandwidth is bigger, and the convergence rate of loop is faster；Conversely, tracking of the loop to signal is more accurate.On the other hand, noise bandwidth
Bigger, loop update cycle just must be shorter, in the case where character rate is certain, it is necessary to the selection shorter time of integration, no
Then loop can be made to become unstable.
Refering to Fig. 7.Traditional NCO is realized by phase accumulator, is overturn in accumulated phase from negative angle to positive-angle
Moment exports pulse, and system sampling clock frequency is fsWhen, traditional NCO can produce frequency range as [0, fs/ 2] pulse letter
Number.The frequency f of traditional NCO outputs signaloWith frequency word fiRelation be：
The frequency for the enable signal that resampling unit needs is possible to the half more than system sampling clock frequency.To be terrible
To the enable signal met the requirements, the present invention improves the structure of traditional NCO.
MOD modules in improved NCO represent to ask accumulation result divided by system sampling clock frequency fsRemainder；AND and
NOT represents to ask respectively and and inversion operation；As control word fi∈[0,fsWhen/2], the frequency of signal A is fi, the frequency of signal B is
(fs-fi), selecting module output signal A；As control word fi∈(fs/2,fs] when, the frequency of signal A is (fs-fi), signal B's
Frequency is fi, selecting module output signal B.
The embodiment of the present invention is described in detail above, embodiment used herein carries out the present invention
Illustrate, the explanation of above example is only intended to help to understand the method and apparatus of the present invention；Meanwhile for the one of this area
As technical staff, according to the thought of the present invention, there will be changes in specific embodiments and applications, to sum up institute
State, this specification content should not be construed as limiting the invention.
Claims (10)
1. a kind of arbitrary velocity CPFSK signal timing synchronous method, includes the following steps：
1) arbitrarily than down-sampled：The pulse in the range of whole sample clock frequency produced with improved digital controlled oscillator NCO is believed
Number it is enable signal, any ratio is carried out to arbitrary velocity Continuous phase frequency shift keying CPFSK baseband signals using resampling unit
It is down-sampled, the sampling rate of CPFSK baseband signals is reduced to D times of character rate, D is integer；
2) MSD decision-feedbacks：Using the existing multiple-symbol detection MSD units of receiving terminal to the CPFSK after down-sampled processing
Signal makes decisions, and feedback is used as using the conjugated signal of the corresponding CPFSK modulated signals of court verdict by feedback signal unit
D CPFSK baseband signal data, in whole process, is first mapped as a symbol, then the symbol is mapped as D by signal
Feedback signal data；
3) it is parallel related：Time delay module carries out delay process to the CPFSK signals after down-sampled processing, respectively obtains super
Before, immediately and hysteresis three branches, effective enable signal control under, three road signals respectively with feedback signal carry out symbol period
Interior parallel related operation, coherent integration unit respectively carry out three road correlation results the correlation intergal of a period of time；
4) error-detecting：Three road coherent integration results are sent into code ring discriminator detection likelihood function envelope, obtain CPFSK signals
Phase error information；
5) it is based on delay locked loop structural adjustment signal phase：Phase error information is filtered by loop filter,
Filter result is sent into improved NCO, is added to obtain the control word of NCO with fixed accumulation amount by loop filter output, common control
The frequency of NCO outputs signal processed；Then traditional numeric-control oscillator NCO is improved, when the control word of NCO is more than systematic sampling
During the half of clock frequency, traditional NCO pulse signals obtained are negated, frequency is obtained and is more than half sampling clock frequency
The pulse signal of rate；Traditional NCO pulse signals exported while the integrate-dump as resampling unit are enabled and timing is same
Effective enable signal of other units in loop is walked, the phase of CPFSK signals is adjusted, control Timing Synchronization loop is to code
Doppler is into line trace.
2. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterised in that：Resampling unit with
CPFSK baseband signals add up input first with accumulator, then when enable signal is effective to cumulative as input
As a result sampled to obtain output signal, while accumulator is reset, then circulated this process, complete the drop to input signal
Sampling operation.
3. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterised in that：Feedback signal passes through
Following two implementations obtain：
A. feedback signal unit first docks received symbol and is negated：Symbol ' 0 ' is changed into ' 1 ', symbol ' 1 ' is changed into ' 0 '；So
Afterwards, CPFSK modulation is carried out to symbol of the inverted, obtains feedback signal；
B. feedback signal unit directly docks received symbol and carries out CPFSK modulation, then takes conjugation to obtain to modulated signal anti-
Feedback signal.
4. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterised in that：MSD units are continuing
Before and after observation after each N number of symbol, just current sign is made decisions, except MSD units and feedback signal unit bring it is hard
Outside part delay, there is the delay of N number of symbol period between feedback signal and corresponding CPFSK signals.
5. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterised in that：Parallel correlation step
In, complex multiplier and accumulator composition digital correlator, time delay module carry out delay operation to CPFSK signals, obtain it is advanced,
Immediately and three branches are lagged, makes the phase of the corresponding phase feedback signal corresponding with the symbol of branch immediately of a symbol
Alignment, the phase d symbol period more advanced than the phase of instant branch of advanced branch, lags the phase of branch than instant branch
Phase falls behind d symbol period, and d represents digital correlator spacing.
6. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 5, it is characterised in that：Three digital correlations
Device carries out complex multiplication operations to three road CPFSK signals and feedback signal respectively；Then, accumulator enable signal control under,
Add up in each symbol period to complex multiplier output signal；Finally, coherent integration unit carries out correlated results
Length is NcorCoherent integration, coherent integration can eliminate high frequency signal components and noise in signal, improve signal-to-noise ratio, increase
Benefit is directly proportional to coherent integration time.
7. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterised in that：Code ring discriminator bag
Power computation module, non-coherent integration unit and error detection unit are included, wherein, power computation module is to advanced branch and hysteresis
The coherent integration results of branch seek power, and non-coherent integration unit carries out the performance number of coherent integration results the non-phase that length is
Dry integration, error detection unit obtain phase error information using non-coherent integration results.
8. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterised in that：Loop filter pair
Phase error signal is filtered, and the filtering signal of output is added to obtain the control word of NCO with fixed accumulated value；The fixation of NCO
Accumulated value σ is character rate RbD times, i.e. σ=DRb。
9. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterised in that：Shake to traditional numeric-control
Swing device NCO to be improved, when control word is more than the half of sampling rate, traditional NCO pulse signals obtained are negated, are obtained
Frequency is more than the pulse signal of half sampling speed；In improved NCO, as control word fi∈[0,fsWhen/2], signal
The frequency of A is fi, the frequency of signal B is (fs-fi), selecting module output signal A；As control word fi∈(fs/2,fs] when, signal
The frequency of A is (fs-fi), the frequency of signal B is fi, selecting module output signal B, wherein, fsFor system sampling clock frequency.
10. arbitrary velocity CPFSK signal timing synchronous method as claimed in claim 1, it is characterised in that：There is frequency locking ring
In system, the phase locked loop filter aided in by frequency locking ring is selected, after selected filter order, is required to receive according to receiver
Intensity most weak signal and highest user's dynamic stress of required support select noise bandwidth.
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| CN107124204B (en) * | 2017-05-26 | 2018-03-13 | 北京理工大学 | A kind of ultra wide band synchronization method of numerical model analysis |
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Effective date of registration: 20190530 Address after: 610036 No. 48 East Street, Chadianzi, Jinniu District, Chengdu City, Sichuan Province Co-patentee after: Beijing mechanical and electrical engineering general design department Patentee after: 10th Research Institute of China Electronics Technology Group Corporation Address before: 610036 No. 48 East Street, Chadianzi, Jinniu District, Chengdu City, Sichuan Province Patentee before: 10th Research Institute of China Electronics Technology Group Corporation |