CN105185823A - Manufacturing method of ring-fence non-junction nanowire transistor - Google Patents
Manufacturing method of ring-fence non-junction nanowire transistor Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title abstract description 6
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- 239000000758 substrate Substances 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000010703 silicon Substances 0.000 claims abstract description 17
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- 238000005516 engineering process Methods 0.000 claims abstract description 11
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- 238000000034 method Methods 0.000 claims description 26
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- 239000011241 protective layer Substances 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 10
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- 238000003384 imaging method Methods 0.000 claims description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66522—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with an active layer made of a group 13/15 material
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66409—Unipolar field-effect transistors
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- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
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Abstract
The invention relates to a manufacturing method of a transistor and especially relates to a manufacturing method of a ring-fence non-junction nanowire transistor. MOCVD is used to epitaxially grow a doped nanowire array on an III-V family material. Through a thermal peeling adhesive tape and a fixing panel, the nanowire is transferred. A non-junction nanowire transistor with a ring-fence structure is manufactured on a silicon-based substrate. By using the manufacturing method of the ring-fence non-junction nanowire transistor provided in the invention, compatibility of an III-V family material nanowire and a plane silicon technology can be realized; simultaneously, mobility degeneration is effectively restrained and a current driving capability of the transistor is increased.
Description
Technical field
The present invention relates to micro & nano technology field, particularly a kind ofly enclose the preparation method of grid without junction nanowire transistor.
Background technology
Silicon-based semiconductor obtains immense success in low cost large scale integrated circuit, but along with the significantly raising of microelectronic component integrated level and the speed of service, brings the increasing considerably of device power consumption, Moore's Law faces the bottleneck problems such as inefficacy.III-V material not only has very outstanding photoelectric properties, in electron mobility, also there is clear superiority, in ultrahigh speed microelectronic component, photoelectric device, obtain extensive use, but III-V group semi-conductor material combined elements is day by day rare, manufacturing cost is higher etc., and problem constrains it further develops.Based on silica-based III-V material high electron mobility microelectronics integrated device, likely realize iii-v and silicon-based semiconductor mutual supplement with each other's advantages, low cost, high-performance integrated optoelectronic device, be international significant development direction in recent years, realizing preparation on silica-base material, to have the electronic device of III-V material raceway groove significant.
Vertical-growth III-V material nano wire is relatively easy, can reduce the contact area with growth substrates, effectively can discharge the stress due to lattice mismatch introducing.But the nano wire of vertical stratification makes transistor fabrication process complexity, and incompatible with silicon planner technology, the iii-v nano wire obtaining cross growth is most important.All realize unified heavy doping without knot silicon nano line transistor channel region and source-drain area, the shutoff of device can be realized by the fully-depleted of channel region, can very high current on/off ratio be realized.Charge carrier is body transport mode at channel region, transports compared to the surface of transoid transistor, effectively can suppress the degeneration of carrier mobility under highfield effect.There is not the problem of doping content gradient in the preparation of its device technology, and device preparation technology and conventional bulk silicon CMOS technology compatibility, device preparation technology is simple, can realize the field-effect transistor of smaller szie while reducing process costs.Horizontal structure iii-v based on silica-base material has an enormous advantage in lifting carrier mobility, simplification preparation technology etc. without junction nanowire transistor.
Summary of the invention
(1) technical problem that will solve
In view of this, main purpose of the present invention is that providing a kind of encloses the preparation method of grid without junction nanowire transistor, to realize the compatibility of iii-v nano wire and planar silicon technique, simultaneously effectively suppresses mobil-ity degradation, promote transistor current driving ability.
(2) technical scheme
For achieving the above object, the invention provides and a kind ofly enclose the preparation method of grid without junction nanowire transistor, comprising:
Step 1: surperficial epitaxial growth one deck sacrificial material layer 12 on the substrate 11, sacrificial material layer 12 is prepared one deck Au catalyst particle 20;
Step 2: at sacrificial material layer 12 upper surface, the nano-wire array 13 of epitaxial growth one deck transverse direction under the effect of Au catalyst particle 20;
Step 3: wet etching removes sacrificial material layer 12, the upper surface of release nano-wire array 13 to substrate 11;
Step 4: prepare one deck nano wire protective layer 30 at the upper surface of substrate 11 and nano-wire array 13, and on nano wire protective layer 30 cover heating stripping tape 40 and fixed panel 41 successively;
Step 5: choose a silicon substrate 50, deposit first medium material layer 61 and second dielectric layer 62 successively on this silicon substrate 50, and utilize hot stripping tape 40 and fixed panel 41 nano wire protective layer 30, nano-wire array 13 and Au catalyst particle 20 to be stripped down from substrate 11 upper surface, then nano wire protective layer 30, nano-wire array 13 and Au catalyst particle 20 is transferred to the upper surface of second dielectric layer 62 by adhering to the mode discharged again;
Step 6: erosion removal nano wire protective layer 30 and Au catalyst particle 20, only retains nano-wire array 13 at second dielectric layer 62 upper surface;
Step 7: at the upper surface of second dielectric layer 62 and nano-wire array 13, prepare the first mask layer 71 and the second mask layer 72 successively, and form gate window 64 by the first mask layer 71 of inverted trapezoidal and the second mask layer 72 wet etching second dielectric layer 62;
Step 8: deposit gate dielectric material successively and gate metal material, gate metal material is wrapped in the skin of gate dielectric material, only retain the part on parcel nano-wire array 13 surface after adopting lift-off to peel off, form gate dielectric layer 80 and gate metal layer 91, realize enclosing grid structure;
Step 9: adopt double-tiered arch dam technology at nano-wire array 13 two ends regional exposure, the second dielectric layer 62 of wet etching exposure beneath window after development, the corrosive liquid chosen on the first medium layer 61 under second dielectric layer 62 without impact; Depositing metal film afterwards, lift-off only retains the part at exposure beneath window parcel nano-wire array 13 two ends after peeling off, form source metal 92 and drain metal layer 93;
Step 10: form one the 3rd dielectric layer 63 on the structure obtained, and at the upper surface spin coating photoresist of the 3rd dielectric layer 63, expose and etch, exposing the contact hole above source metal 92, drain metal layer 93 and gate metal layer 91; Peeled off the test electrode 96 forming the test electrode 94 of source electrode, the test electrode 95 of grid and drain after metallic film deposition by lift-off, complete the preparation of device.
(3) beneficial effect
As can be seen from technique scheme, the present invention has following beneficial effect:
1, provided by the inventionly the preparation method of grid without junction nanowire transistor is enclosed, adopt hot stripping tape from the method for growth substrates transfer iii-v horizontal nano linear array, gate transistor is enclosed in preparation, enclose grid structure and there is outstanding grid-control ability and excellent transport property, effectively can promote the current driving ability of transistor.
2, provided by the inventionly the preparation method of grid without junction nanowire transistor is enclosed, iii-v nano wire has very high electron mobility, the feature that in nodeless mesh body pipe, current-carrying daughter transports simultaneously has good inhibitory action to mobil-ity degradation, is conducive to realizing the big current needed for high-speed computation and high frequency.
3, provided by the inventionly the preparation method of grid without junction nanowire transistor is enclosed, preparation has the transistor of iii-v nanowire channel on a silicon substrate, technological process and CMOS planar technique are compatible, utilize existing technique can realize integrated at silicon substrate of iii-v nano wire.
Accompanying drawing explanation
Fig. 1 is that the method flow diagram of grid without junction nanowire transistor is enclosed in preparation provided by the invention;
Fig. 2 to Figure 11 is the process chart of iii-v without junction nanowire transistor enclosing grid structure according to the preparation of the embodiment of the present invention, is corresponding in turn to step 1 to step 10, wherein Fig. 2 and Fig. 8 corresponding top view and end view respectively up and down.
Embodiment
For making the object, technical solutions and advantages of the present invention clearly understand, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
Provided by the inventionly enclose the preparation method of grid without junction nanowire transistor, adopt the nano-wire array that MOCVD adulterates at III-V material Epitaxial growth, and by hot stripping tape and fixed panel, nano wire is shifted, in silicon-based substrate preparation enclose grid structure without junction nanowire transistor.
Refer to shown in Fig. 1 to Figure 11, the invention provides and a kind ofly enclose the preparation method of grid without junction nanowire transistor, the method comprises:
Step 1: first, on the substrate 11 surperficial epitaxial growth one deck sacrificial material layer 12, then, in sacrificial material layer 12, prepare one deck Au catalyst particle 20 by the method for " photoetching+thin film deposition+stripping ";
In this step, substrate 11 is GaAs or the indium arsenide of (110) crystal face.Sacrificial material layer 12 is compd A l
1-xga
xas or Al
1-xin
xas, x value scope is 0.4-0.6, and thickness is 20-50nm, to guarantee that sacrificial material layer 12 and substrate 11 have relative little lattice mismatch to be easy to corrode simultaneously.In this sacrificial material layer 12, one deck Au catalyst particle 20 is prepared by the method for " photoetching+thin film deposition+stripping ", described Au catalyst particle 20 also can pass through one or more preparations in sputtering method, evaporation, chemical vapor deposition, plasma assisted deposition method, metallo-organic decomposition process or laser-assisted deposition method, and Au catalyst particle 20 diameter is 10-50nm.
Step 2: at sacrificial material layer 12 upper surface, the nano-wire array 13 of epitaxial growth one deck transverse direction under the effect of Au catalyst particle 20;
In this step, the nano-wire array 13 of epitaxial growth one deck transverse direction under the effect of Au catalyst particle 20, be adopt the method for MOCVD to grow, the length of nano-wire array 13 is 0.5-2 μm, include the composition of doped chemical in source of the gas, make the doping content of nano-wire array 13 reach 10
18cm
-3magnitude.
Step 3: wet etching removes sacrificial material layer 12, the upper surface of release nano-wire array 13 to substrate 11;
In this step, wet etching sacrificial material layer 12, the corrosive liquid that corrosion process selects concentration low, the nano-wire array 13 being discharged into substrate 11 upper surface after ensureing corrosion is relatively orderly.
Step 4: prepare one deck nano wire protective layer 30 at the upper surface of substrate 11 and nano-wire array 13, and on nano wire protective layer 30 cover heating stripping tape 40 and fixed panel 41 successively.
In this step, nano wire protective layer 30 can be the harder metal of the materials such as nickel, aluminium, titanium, gold, aluminium or chromium, and thickness is 80-150nm.
Step 5: choose a silicon substrate 50; deposit first medium material layer 61 and second dielectric layer 62 successively on this silicon substrate 50; and utilize hot stripping tape 40 and fixed panel 41 nano wire protective layer 30, nano-wire array 13 and Au catalyst particle 20 to be stripped down from substrate 11 upper surface, then nano wire protective layer 30, nano-wire array 13 and Au catalyst particle 20 is transferred to the upper surface of second dielectric layer 62 by adhering to the mode discharged again.
In this step; nano wire protective layer 30, nano-wire array 13 and Au catalyst particle 20 is transferred to the upper surface of second dielectric layer 62 by adhering to the mode discharged again; dispose procedure is the adhesiveness being reduced hot stripping tape 40 by the mode of heating, makes hot stripping tape 40 depart from the upper surface of nano wire protective layer 30.First medium layer 61 selects silicon nitride, and second dielectric layer 62 selects silicon dioxide, and thickness is 30-100nm, ensures to wrap up gate dielectric layer at nano-wire array 13 after 80s, has enough spaces to fill gate metal layer 91 below it.
Step 6: erosion removal nano wire protective layer 30 and Au catalyst particle 20, only retains nano-wire array 13 at second dielectric layer 62 upper surface.
Step 7: at the upper surface of second dielectric layer 62 and nano-wire array 13, prepare the first mask layer 71 and the second mask layer 72 successively, and form gate window 64 by the first mask layer 71 of inverted trapezoidal and the second mask layer 72 wet etching second dielectric layer 62;
In this step, the first mask layer 71 and the second mask layer 72 all adopt positive photoresist, and gross thickness is 100-200nm, and the first mask layer 71 required exposure dosage is less than the second mask layer 72, form inverted trapezoidal window after ensureing exposure imaging; The corrosive liquid chosen during described corrosion without impact, only corrodes second dielectric layer 62 to the first medium layer 61 under second dielectric layer 62, forms gate window 64 after second dielectric layer 62 is corroded in inverted trapezoidal beneath window.
Step 8: adopt ald (ALD) method deposit gate dielectric material successively and gate metal material, gate metal material is wrapped in the skin of gate dielectric material, the part on parcel nano-wire array 13 surface is only retained after adopting lift-off to peel off, form gate dielectric layer 80 and gate metal layer 91, realize enclosing grid structure; The material that wherein gate dielectric layer 80 adopts is Al
2o
3, nitrogen oxide, HfO
2, Si
3n
4, ZrO
2, Ta
2o
5, BST or PZT, thickness is 2-10nm.
Step 9: adopt the double-tiered arch dam technology described in step 7, at nano-wire array 13 two ends regional exposure, development after wet etching exposure beneath window second dielectric layer 62, the corrosive liquid chosen on the first medium layer 61 under second dielectric layer 62 without impact; Depositing metal film afterwards, lift-off only retains the part at exposure beneath window parcel nano-wire array 13 two ends after peeling off, form source metal 92 and drain metal layer 93; Source metal 92 and drain metal layer 93 adopt ALD method to prepare.
Step 10: form one the 3rd dielectric layer 63 on the structure that step 9 obtains, and at the upper surface spin coating photoresist of the 3rd dielectric layer 63, expose and etch, exposing the contact hole above source metal 92, drain metal layer 93 and gate metal layer 91; Peeled off the test electrode 96 forming the test electrode 94 of source electrode, the test electrode 95 of grid and drain after metallic film deposition by lift-off, complete the preparation of device.Wherein, the 3rd dielectric layer 63 can be the one in silicon dioxide and silicon nitride, plays passivation, preferably adopts the preparation of ALD method.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. enclose the preparation method of grid without junction nanowire transistor, it is characterized in that, comprising:
Step 1: in substrate (11) upper surface epitaxial growth one deck sacrificial material layer (12), sacrificial material layer (12) is prepared one deck Au catalyst particle (20);
Step 2: at sacrificial material layer (12) upper surface, the nano-wire array (13) of epitaxial growth one deck transverse direction under the effect of Au catalyst particle (20);
Step 3: wet etching removes sacrificial material layer (12), release nano-wire array (13) is to the upper surface of substrate (11);
Step 4: prepare one deck nano wire protective layer (30) at the upper surface of substrate (11) and nano-wire array (13), and on nano wire protective layer (30) cover heating stripping tape (40) and fixed panel (41) successively;
Step 5: choose a silicon substrate (50), deposit first medium material layer (61) and second dielectric layer (62) successively on this silicon substrate (50), and utilize hot stripping tape (40) and fixed panel (41) by nano wire protective layer (30), nano-wire array (13) and Au catalyst particle (20) strip down from substrate (11) upper surface, then by nano wire protective layer (30), nano-wire array (13) and Au catalyst particle (20) are transferred to the upper surface of second dielectric layer (62) by adhering to the mode discharged again,
Step 6: erosion removal nano wire protective layer (30) and Au catalyst particle (20), only retains nano-wire array (13) at second dielectric layer (62) upper surface;
Step 7: at the upper surface of second dielectric layer (62) and nano-wire array (13), prepare the first mask layer (71) and the second mask layer (72) successively, and pass through the first mask layer (71) and the second mask layer (72) the wet etching second dielectric layer (62) formation gate window (64) of inverted trapezoidal;
Step 8: deposit gate dielectric material successively and gate metal material, gate metal material is wrapped in the skin of gate dielectric material, the part on parcel nano-wire array (13) surface is only retained after adopting lift-off to peel off, form gate dielectric layer (80) and gate metal layer (91), realize enclosing grid structure;
Step 9: adopt double-tiered arch dam technology at nano-wire array (13) two ends regional exposure, the second dielectric layer (62) of wet etching exposure beneath window after development, the corrosive liquid chosen is on first medium layer (61) the nothing impact under second dielectric layer (62); Depositing metal film afterwards, lift-off only retains the part at exposure beneath window parcel nano-wire array (13) two ends after peeling off, form source metal (92) and drain metal layer (93);
Step 10: form one the 3rd dielectric layer (63) on the structure obtained, and at the upper surface spin coating photoresist of the 3rd dielectric layer (63), expose and etch, exposing the contact hole of source metal (92), drain metal layer (93) and gate metal layer (91) top; Peeled off the test electrode (96) forming the test electrode (94) of source electrode, the test electrode (95) of grid and drain after metallic film deposition by lift-off, complete the preparation of device.
2. according to claim, enclose the preparation method of grid without junction nanowire transistor, it is characterized in that,
Substrate described in step 1 (11) is GaAs or the indium arsenide of (110) crystal face, and described sacrificial material layer (12) is compd A l
1-xga
xas or Al
1-xin
xas, x value scope is 0.4-0.6, and thickness is 20-50nm;
In sacrificial material layer (12), one deck Au catalyst particle (20) is prepared described in step 1, be prepared by one or more in sputtering method, evaporation, chemical vapor deposition, plasma assisted deposition method, metallo-organic decomposition process or laser-assisted deposition method, Au catalyst particle (20) diameter is 10-50nm.
3. according to claim, enclose the preparation method of grid without junction nanowire transistor, it is characterized in that, described in step 2 under the effect of Au catalyst particle (20) nano-wire array (13) of epitaxial growth one deck transverse direction, adopt the method for MOCVD to grow, length is 0.5-2 μm, include the composition of doped chemical in source of the gas, make the doping content of nano-wire array (13) reach 10
18cm
-3magnitude.
4. according to claim, enclose the preparation method of grid without junction nanowire transistor, it is characterized in that, the protective layer of nano wire described in step 4 (30) is metallic nickel, aluminium, titanium, gold, aluminium or chromium, and thickness is 80-150nm.
5. according to claim, enclose the preparation method of grid without junction nanowire transistor; it is characterized in that; described in step 5, nano wire protective layer (30), nano-wire array (13) and Au catalyst particle (20) are transferred to the upper surface of second dielectric layer (62) by adhering to the mode discharged again; dispose procedure is the adhesiveness being reduced hot stripping tape (40) by the mode of heating, makes hot stripping tape (40) depart from the upper surface of nano wire protective layer (30).
6. according to claim, enclose the preparation method of grid without junction nanowire transistor, it is characterized in that, the layer of first medium described in step 5 (61) selects silicon nitride, described second dielectric layer (62) selects silicon dioxide, thickness is 30-100nm, ensure after nano-wire array (13) parcel gate dielectric layer (80), below it, have enough spaces to fill gate metal layer (91).
7. according to claim, enclose the preparation method of grid without junction nanowire transistor, it is characterized in that, first mask layer described in step 7 (71) and the second mask layer (72) all adopt positive photoresist, gross thickness is 100-200nm, and the first mask layer (71) required exposure dosage is less than the second mask layer (72), after ensureing exposure imaging, form inverted trapezoidal window; The corrosive liquid chosen during described corrosion is on first medium layer (61) the nothing impact under second dielectric layer (62), only corrode second dielectric layer (62), after second dielectric layer (62) is corroded, form gate window (64) in inverted trapezoidal beneath window.
8. according to claim, enclose the preparation method of grid without junction nanowire transistor, it is characterized in that, deposit gate dielectric material successively described in step 8 and gate metal material adopt Atomic layer deposition method preparation, and the material that wherein gate dielectric layer (80) adopts is Al
2o
3, nitrogen oxide, HfO
2, Si
3n
4, ZrO
2, Ta
2o
5, BST or PZT, thickness is 2-10nm.
9. according to claim, enclose the preparation method of grid without junction nanowire transistor, it is characterized in that, source metal described in step 9 (92) and drain metal layer (93) adopt the preparation of ALD method.
10. according to claim, enclose the preparation method of grid without junction nanowire transistor, it is characterized in that, described in step 10, the 3rd dielectric layer (63) is silicon dioxide or silicon nitride, plays passivation, adopts the preparation of ALD method.
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| CN111243960A (en) * | 2020-01-20 | 2020-06-05 | 中国科学院上海微系统与信息技术研究所 | Preparation method of semiconductor nanowire and field effect transistor |
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