CN105185771A - Trigger circuit for ESD protection - Google Patents
Trigger circuit for ESD protection Download PDFInfo
- Publication number
- CN105185771A CN105185771A CN201510458487.2A CN201510458487A CN105185771A CN 105185771 A CN105185771 A CN 105185771A CN 201510458487 A CN201510458487 A CN 201510458487A CN 105185771 A CN105185771 A CN 105185771A
- Authority
- CN
- China
- Prior art keywords
- nmos tube
- triggering
- esd
- circuits
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention discloses a trigger circuit for ESD protection, which is used for triggering an output driving tube to be switched on evenly to realize ESD current discharge when an ESD event occurs. The output driving tube comprises a first NMOS transistor; the trigger circuit comprises a first Zener diode, a first resistor, a second resistor and a second NMOS transistor; a cathode of the first Zener diode is connected with an input/output pad, and the first resistor is serially connected between an anode of first Zener diode and the ground; a grid of the second NMOS transistor is connected with the anode of first Zener diode, the second resistor is connected between a drain of the second NMOS transistor and the input/output pad, and a source of the second NMOS transistor is connected with a grid of the first NMOS transistor; and a source of the first NMOS transistor is connected with the input/output pad, and the source of the second NMOS transistor is grounded. The trigger circuit for ESD protection can reduce the area of the output driving tube, so as to reduce area of the input/output circuit and enhance ESD self-protection capability of the output driving tube.
Description
Technical field
The present invention relates to a kind of semiconductor device, particularly relate to a kind of circuits for triggering protected for Electro-static Driven Comb (ElectroStaticDischarge, ESD).
Background technology
As shown in Figure 1; existing esd protection circuit figure; existing esd protection circuit comprises NMOS tube N101 and resistance R101; the drain electrode of NMOS tube N101 connects input and output (IO) liner (PAD) 100; the source ground of NMOS tube N101, resistance R101 is connected between the grid of NMOS tube N101 and source electrode.When ESD positive pulse produces, ESD positive pulse can make high pressure be coupled to grid by the drain-gate capacitance of NMOS tube N101 NMOS tube N101 is opened, thus realizes Electro-static Driven Comb.
N-type driving tube (N_driver) i.e. NMOS tube N102 as output circuit in Fig. 1 also can directly touch ESD positive pulse, the drain electrode of NMOS tube N102 connects input and output liner 100, source ground, the grid of NMOS tube N102 connects drive singal Pre-drive, and drive singal Pre-drive is provided by internal circuit (not shown).NMOS tube N102 was the driving tube as output circuit originally, be connected, therefore NMOS tube N102 itself will have ESD self-shield ability between the drain electrode due to NMOS tube N102 with input and output liner 100.
In prior art; in order to make N_driver pipe and NMOS tube 102, there is ESD self-shield ability; General N _ driver pipe needs to design according to the rule (rule) of ESD, namely by designing according to the rule (rule) of ESD the ability making N_driver have ESD self-shield.Because the ESD self-shield ability of the NMOS of normal conventional (normal) is quite weak.And in the rule of ESD, generally all need NMOS to increase silicide barrier layer (silicideblock, SB) at drain region (drain) end.As shown in Figure 2; it is the domain of driving tube when adopting esd protection circuit shown in Fig. 1; p type diffusion region (Pdif) 102 is formed in P trap (PW) 101; inside is formed with the N-type diffusion region (Ndif) 103 as source region and drain region; polysilicon gate 104 comprises many that are arranged side by side; two polysilicon gates 104 are illustrated in Fig. 2; drain region is between two polysilicon gates 104; source region is positioned at the outside of two polysilicon gates 104; region shown in dotted line frame 105 is silicide barrier layer forming region, and dotted line frame 106 is drain electrode lead-out area.Size A be the edge of polysilicon gate 104 to the distance between drain electrode edge, draw-out area, ruleA namely according to the size A of the rule of ESD generally more than 2 microns.
And some application such as large driving, switching tube etc. require that the NMOS used is very large, several thousand even live width of several ten thousand microns usually to be arrived, if this time is designed according to the rule of ESD can need very large IO area.If designed according to normalrule, usually can not evenly open, ESD self-shield ability, causes ESD not reach standard, brings larger difficulty to the design of the esd protection of chip.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of circuits for triggering for esd protection, can reduce the area thus the area of minimizing imput output circuit that export driving tube and the ESD self-shield ability that can increase output driving tube.
For solving the problems of the technologies described above, the circuits for triggering for esd protection provided by the invention are evenly opened for the triggering output driving tube when esd event produces and are realized ESD current drain.
Described output driving tube comprises the first NMOS tube.
Described circuits for triggering comprise the first circuits for triggering.
Described first circuits for triggering comprise the first Zener diode, the first resistance, the second resistance and the second NMOS tube.
The negative electrode of described first Zener diode connects input and output liner, and described first resistant series is between the anode and ground of described first Zener diode.
The grid of described second NMOS tube connects the anode of described first Zener diode, and described second resistance is connected between the drain electrode of described second NMOS tube and described input and output liner, and the source electrode of described second NMOS tube connects the grid of described first NMOS tube.
The drain electrode of described first NMOS tube connects described input and output liner, the source ground of described second NMOS tube.
Further improvement is, the grid of described first NMOS tube connects internal circuit.
Further improvement is, described first resistance is more than 100 ohm, and described second resistance is more than 100 ohm.
Further improvement is, the disruptive potential of described first Zener diode is greater than the applied voltage of described input and output liner.
Circuits for triggering of the present invention can make output driving tube evenly open when esd event produces and namely produces esd pulse, thus by having large-sized output driving tube to carry out ESD current drain, can improve esd protection ability.Relative to the output driving tube not connecing esd event triggering signal in existing esd protection circuit, the present invention can also reduce the area thus the area of minimizing imput output circuit that export driving tube and the ESD self-shield ability that can increase output driving tube.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is existing esd protection circuit figure;
Fig. 2 is the domain of driving tube when adopting esd protection circuit shown in Fig. 1;
Fig. 3 is the circuits for triggering of the embodiment of the present invention for esd protection.
Embodiment
As shown in Figure 3; the circuits for triggering of the embodiment of the present invention for esd protection; the circuits for triggering protected for ESD positive pulse in the embodiment of the present invention are that example is described, and the circuits for triggering for esd protection of the embodiment of the present invention are evenly opened for the triggering output driving tube when esd event produces and realized ESD current drain.
Described output driving tube comprises the first NMOS tube N1.
Described circuits for triggering comprise the first circuits for triggering.
Described first circuits for triggering comprise the first Zener diode D1, the first resistance R1, the second resistance R2 and the second NMOS tube N2.
The negative electrode of described first Zener diode D1 connects input and output liner 1, and described first resistance R1 is connected between the anode of described first Zener diode D1 and ground GND.
The grid of described second NMOS tube N2 connects the anode of described first Zener diode D1, described second resistance R2 is connected between the drain electrode of described second NMOS tube N2 and described input and output liner 1, and the source electrode of described second NMOS tube N2 connects the grid of described first NMOS tube N1.
The drain electrode of described first NMOS tube N1 connects institute's input and output substrate, the source ground GND of described second NMOS tube N2.
The grid of described first NMOS tube N1 connects internal circuit 2.
Be preferably, described first resistance R1 is more than 100 ohm, and described second resistance R2 is more than 100 ohm.
The disruptive potential of described first Zener diode D1 is greater than the applied voltage of described input and output liner 1, and the 5V such as routine applies, and the puncture voltage of described first Zener diode D1 is generally at about 6.5V.When esd event occurs at described input and output liner 1 end, the current potential on input and output liner 1 described in meeting lifting.When the current potential of described input and output liner 1 is lifted to certain value, described first Zener diode D1 can be made to puncture, electric current can flow through described first Zener diode D1 and described first resistance R1, the grid of described second NMOS tube N2 is made to be in high potential, open the raceway groove of described second NMOS tube N2, and clamper is carried out to the voltage of IO end and described input and output liner 1 end.After the raceway groove unlatching of described second NMOS tube N2, the current potential on described input and output liner 1 can be transferred to the N_Driver i.e. gate terminal of the first NMOS tube N1 by the second resistance R2 and the second NMOS tube N2.Because be voltage transmission, therefore damage can not be caused to the grid of internal circuit 2 and N_Driver.The gate terminal of N_Driver is in high potential, and the raceway groove of large-area N_Driver can evenly be opened, and help ESD electric current is releasing to ground GND from IO and described input and output liner 1 end, thus improve the ESD self-shield ability of N_Driver.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (4)
1. for circuits for triggering for esd protection, it is characterized in that, circuits for triggering are evenly opened for the triggering output driving tube when esd event produces and are realized ESD current drain;
Described output driving tube comprises the first NMOS tube;
Described circuits for triggering comprise the first circuits for triggering;
Described first circuits for triggering comprise the first Zener diode, the first resistance, the second resistance and the second NMOS tube;
The negative electrode of described first Zener diode connects input and output liner, and described first resistant series is between the anode and ground of described first Zener diode;
The grid of described second NMOS tube connects the anode of described first Zener diode, and described second resistance is connected between the drain electrode of described second NMOS tube and described input and output liner, and the source electrode of described second NMOS tube connects the grid of described first NMOS tube;
The drain electrode of described first NMOS tube connects described input and output liner, the source ground of described second NMOS tube.
2., as claimed in claim 1 for the circuits for triggering of esd protection, it is characterized in that: the grid of described first NMOS tube connects internal circuit.
3., as claimed in claim 1 for the circuits for triggering of esd protection, it is characterized in that: described first resistance is more than 100 ohm, described second resistance is more than 100 ohm.
4., as claimed in claim 1 for the circuits for triggering of esd protection, it is characterized in that: the disruptive potential of described first Zener diode is greater than the applied voltage of described input and output liner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510458487.2A CN105185771A (en) | 2015-07-30 | 2015-07-30 | Trigger circuit for ESD protection |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510458487.2A CN105185771A (en) | 2015-07-30 | 2015-07-30 | Trigger circuit for ESD protection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105185771A true CN105185771A (en) | 2015-12-23 |
Family
ID=54907758
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510458487.2A Pending CN105185771A (en) | 2015-07-30 | 2015-07-30 | Trigger circuit for ESD protection |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105185771A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106786463A (en) * | 2017-01-04 | 2017-05-31 | 上海华虹宏力半导体制造有限公司 | High pressure ESD protects triggers circuit |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW506111B (en) * | 2001-07-25 | 2002-10-11 | United Microelectronics Corp | On-chip ESD protection circuits with substrate-triggered SCR device |
| TW518737B (en) * | 2001-09-21 | 2003-01-21 | Faraday Tech Corp | ESD protection circuit for protecting input buffer and output buffer |
| CN1414678A (en) * | 2001-10-23 | 2003-04-30 | 联华电子股份有限公司 | Electrostatic discharge protective circuit using base trigger silicon rectifier |
| US7233475B1 (en) * | 2006-02-16 | 2007-06-19 | Novatek Microelectronics Corp. | Integrated circuit with an electrostatic discharge protection circuit |
| CN101192606A (en) * | 2006-12-01 | 2008-06-04 | 旺宏电子股份有限公司 | Esd protection circuit |
| CN201336568Y (en) * | 2009-01-06 | 2009-10-28 | 深圳市明微电子股份有限公司 | Electrostatic protection circuit with detection circuit |
| CN103683235A (en) * | 2012-09-24 | 2014-03-26 | 上海华虹宏力半导体制造有限公司 | Electrostatic discharge self-protection circuit |
| CN104766858A (en) * | 2014-01-06 | 2015-07-08 | 旺宏电子股份有限公司 | Electrostatic discharge protection device |
-
2015
- 2015-07-30 CN CN201510458487.2A patent/CN105185771A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW506111B (en) * | 2001-07-25 | 2002-10-11 | United Microelectronics Corp | On-chip ESD protection circuits with substrate-triggered SCR device |
| TW518737B (en) * | 2001-09-21 | 2003-01-21 | Faraday Tech Corp | ESD protection circuit for protecting input buffer and output buffer |
| CN1414678A (en) * | 2001-10-23 | 2003-04-30 | 联华电子股份有限公司 | Electrostatic discharge protective circuit using base trigger silicon rectifier |
| US7233475B1 (en) * | 2006-02-16 | 2007-06-19 | Novatek Microelectronics Corp. | Integrated circuit with an electrostatic discharge protection circuit |
| CN101192606A (en) * | 2006-12-01 | 2008-06-04 | 旺宏电子股份有限公司 | Esd protection circuit |
| CN201336568Y (en) * | 2009-01-06 | 2009-10-28 | 深圳市明微电子股份有限公司 | Electrostatic protection circuit with detection circuit |
| CN103683235A (en) * | 2012-09-24 | 2014-03-26 | 上海华虹宏力半导体制造有限公司 | Electrostatic discharge self-protection circuit |
| CN104766858A (en) * | 2014-01-06 | 2015-07-08 | 旺宏电子股份有限公司 | Electrostatic discharge protection device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106786463A (en) * | 2017-01-04 | 2017-05-31 | 上海华虹宏力半导体制造有限公司 | High pressure ESD protects triggers circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102214655B (en) | Integrated circuit and method for reduced trigger voltage ofstacked ESD protection circuit | |
| JP5955924B2 (en) | Electrostatic discharge protection circuit | |
| US7110228B2 (en) | Separated power ESD protection circuit and integrated circuit thereof | |
| CN104392989B (en) | A kind of ESD protection circuit based on controllable silicon | |
| US9030791B2 (en) | Enhanced charge device model clamp | |
| CN102263102B (en) | Backward diode-triggered thyristor for electrostatic protection | |
| US20130099297A1 (en) | Electrostatic discharge protection device | |
| CN106786463A (en) | High pressure ESD protects triggers circuit | |
| US9545041B2 (en) | I/O device, method for providing ESD protection for an I/O device and ESD protection device for an I/O device | |
| US7978451B2 (en) | Circuit arrangement comprising an electronic component and an ESD protection arrangement | |
| US8208234B2 (en) | Circuit with ESD protection for a switching regulator | |
| US20150146330A1 (en) | Esd robust mos device | |
| US9991253B2 (en) | Protection element, protection circuit, and semiconductor integrated circuit | |
| US8730624B2 (en) | Electrostatic discharge power clamp with a JFET based RC trigger circuit | |
| CN108063134B (en) | NMOS device based on SOI technology and electrostatic protection circuit formed by NMOS device | |
| JP6398696B2 (en) | Electrostatic protection circuit and semiconductor integrated circuit device | |
| CN102611093A (en) | Static discharging circuit | |
| CN105185771A (en) | Trigger circuit for ESD protection | |
| CN103515944A (en) | Power Clamp for ESD protection between power supply and ground by adopting dual-channel technology | |
| JP6405986B2 (en) | Electrostatic protection circuit and semiconductor integrated circuit device | |
| CN1979842A (en) | Electrostatic discharging protection circuit triggered by lining-bottom | |
| US10454269B2 (en) | Dynamically triggered electrostatic discharge cell | |
| CN102222669B (en) | Silicon controlled rectifier used for ESD protection | |
| CN102270658B (en) | Low-trigger-voltage and low-parasitic-capacitance silicon controlled structure | |
| US7907374B2 (en) | Electrostatic discharge prevention circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151223 |
|
| RJ01 | Rejection of invention patent application after publication |