CN105185692A - Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices - Google Patents

Methods of forming low-defect strain-relaxed layers on lattice-mismatched substrates and related semiconductor structures and devices Download PDF

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CN105185692A
CN105185692A CN201510126114.5A CN201510126114A CN105185692A CN 105185692 A CN105185692 A CN 105185692A CN 201510126114 A CN201510126114 A CN 201510126114A CN 105185692 A CN105185692 A CN 105185692A
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layer
germanium
semiconductor
silicon layer
silicon
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CN105185692B (en
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王维一
马克·S·罗德
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

Methods of forming strain-relaxing semiconductor layers are provided in which a porous region is formed in a surface of a semiconductor substrate. A first semiconductor layer that is lattice-matched with the semiconductor substrate is formed on the porous region. A second semiconductor layer is formed on the first semiconductor layer, the second semiconductor layer being a strained layer as formed. The second semiconductor layer is then relaxed.

Description

The method of deformation relaxation method, formation semiconductor layer and semiconductor device
This application claims the sequence number submitted on March 20th, 2014 is 61,968, the priority of the U.S. Provisional Application of 126, and the full content of this U.S. Provisional Application is contained in this by reference, as this U.S. Patent application is fully set forth at this.
Technical field
The present invention's design relates generally to semiconductor device, more specifically, relates to the method forming deformation relaxation layer in lattice mismatching semiconductor substrate and the semiconductor device comprising such deformation relaxation layer.
Background technology
Existence may need the multiple application of growth strain semiconductor layer.Such as, usually strained silicon layer is used in high-performance complementary metal-oxide semiconductor (MOS) (CMOS) device, this is because strained semiconductor layer can show higher carrier mobility, so the transistor with the raceway groove be formed in such strained silicon layer can show higher switching speed.Strained silicon layer can such as by being formed at the silicon layer of thicker germanium-silicon layer (so-called silicon-germanium " buffering " layer) upper growth relative thin.
Fig. 1 shows the strained silicon layer formed according to conventional art.With reference to Fig. 1, according to this conventional art, body silicon base 10 epitaxially grows grating SiGe (Si 1-xge x) layer 20.At grating Si 1-xge xinterface between layer 20 and body silicon base 10, the value of x can very low (or being 0), and increase along with the distance apart from substrate 10, and x can increase.Due to silicon base 10 and grating Si 1-xge xlattice mismatch between layer 20, so grating Si 1-xge xlayer 20 may produce strain along with growth.At grating Si 1-xge xafter layer 20 growth exceedes specific thicknesses, at body silicon base 10 and grating Si 1-xge xinterface between layer 20 may produce misfit dislocation 22.A pair threading dislocation 24 can from each misfit dislocation 22 towards grating Si 1-xge xthe surface of layer 20 extends up through grating Si 1-xge xlayer 20.Can use the technology being tending towards the length increasing misfit dislocation 22 in growth course, this can help the quantity limiting the threading dislocation 24 formed.The formation of these dislocations 22,24 may be used for relaxation grating Si 1-xge xlayer 20.Grating Si subsequently 1-xge xlayer 20 can by thermal annealing further relaxation.
Then, can at grating Si 1-xge xlayer 20 grows silicon layer 30.Due to the grating Si of relaxation 1-xge xlattice mismatch between layer 20 and silicon layer 30, silicon layer 30 may produce strain along with growth.But, regrettably, arrive grating Si 1-xge xthe threading dislocation 24 of upper surface of layer 20 may cause dislocation in strained silicon layer 30 or other defect.These defect/dislocations in strained silicon layer 30 can affect the performance of any semiconductor device be formed in silicon layer 30 negatively.Although at grating Si 1-xge xthe density of the threading dislocation at the top surface place of layer 20 usually can by increasing grating Si 1-xge xthe thickness of layer 20 reduces, but thicker Si 1-xge xthe growth of layer 20 can increase the growth time of needs significantly, and may cause other problem, such as, makes semiconductor wafer become disabled incidence increase owing to dropping into the particle in wafer in epitaxially grown process.In addition, in order to the level of threading dislocation is reduced to 1 × 10 6/ cm 2or less, may need grating Si 1-xge xlayer 20 grows to the thickness of tens or hundreds of micron.In numerous applications, relevant to the growth of such thick-layer growth time and material cost can be too expensive.
In another way, grow Si by silicon base (silicon-on-insulatorsubstrate) on insulator 1-xge xlayer forms deformation relaxation Si 1-xge xlayer.At the Si that growth is such 1-xge xbefore layer, silicon-on-insulator substrate is eclipsed carves or stands grinding operation, makes the insulator of silicon base on insulator only to retain the thick silicon layer of 50nm.At growth Si 1-xge xafter layer, make its relaxation by thermal anneal process subsequently.But this technique needs more expensive silicon-on-insulator substrate, and has shown only for the Si of relatively low germanium concentration 1-xge xlayer (that is, x=0.15) works.
Summary of the invention
Provide the method forming deformation relaxation semiconductor layer, wherein, in the surface of semiconductor base, form porous region.Porous region is formed the first semiconductor layer with semiconductor base Lattice Matching.Form the second strained semiconductor layer on the first semiconductor layer.Then, the second semiconductor layer relaxation is made.
In certain embodiments, the 3rd semiconductor layer can be formed on the second semiconductor layer of relaxation.3rd semiconductor layer can be the strained layer as formed.Then, the 3rd semiconductor layer relaxation can be made, to provide the semiconductor layer of deformation relaxation.
In certain embodiments, can by utilizing wet etchant and the top surface making electromotive force be applied to wet etching semiconductor base between semiconductor base and wet etchant forms porous region in the top surface of semiconductor base.
In certain embodiments, before making the second semiconductor layer relaxation, the first semiconductor layer can be subject to tensile stress, and the second semiconductor layer can be subject to compression.
In certain embodiments, the thickness of the first semiconductor layer can be less than 20nm.
In certain embodiments, the first semiconductor layer only can be weakly bonded to semiconductor base, thus when tensile stress is applied to the first semiconductor layer, the first semiconductor layer can move relative to semiconductor base.
First semiconductor layer can be formed directly on the porous region in the surface of semiconductor base, and the second semiconductor layer can be formed directly on the first semiconductor layer.
In certain embodiments, semiconductor base can be silicon base, first semiconductor layer can be silicon layer, and the second semiconductor layer can be first germanium-silicon layer with the first germanium concentration, and the 3rd semiconductor layer can be second germanium-silicon layer with the second germanium concentration being greater than the first germanium concentration.
In certain embodiments, the germanium concentration of the second germanium-silicon layer can be greater than 75% (or 85%), and the threading dislocation density in the second germanium-silicon layer can be less than about 1 × 10 5/ cm 2.
In certain embodiments, the gross thickness of silicon layer, the first germanium-silicon layer and the second germanium-silicon layer can be less than 75nm.
In certain embodiments, the second semiconductor layer can be III-V compound semiconductor layer.
In certain embodiments, the 4th semiconductor layer can be formed on the second germanium-silicon layer, semiconductor device can be formed at least in part on the 4th semiconductor layer or in the 4th semiconductor layer.
According to other embodiment of the present invention's design, provide the method forming deformation relaxation semiconductor layer, wherein, first semiconductor layer is formed on the top in the submissive region of semiconductor base, semiconductor base and the first semiconductor layer Lattice Matching, make the first semiconductor layer only be weakly bonded to the submissive region of semiconductor base, and can on the top surface of semiconductor base transverse shifting.Form the second semiconductor layer with the first semiconductor layer lattice mismatch on the first semiconductor layer.Relaxation process is performed to the second semiconductor layer, to produce threading dislocation in the first semiconductor layer, makes the second semiconductor layer substantially not have threading dislocation simultaneously.
In certain embodiments, the 3rd semiconductor layer with the second semiconductor layer lattice mismatch can be formed on the second semiconductor layer, and relaxation process can be performed to the 3rd semiconductor layer, to produce threading dislocation in the second semiconductor layer, make the 3rd semiconductor layer substantially not have threading dislocation simultaneously.
In certain embodiments, the first semiconductor layer can be subject to tensile stress before relaxation, and the second semiconductor layer can be subject to compression before relaxation.
In certain embodiments, first semiconductor layer can be the silicon layer with the first thickness, second semiconductor layer can be the germanium-silicon layer having the first germanium concentration and have the second thickness being greater than the first thickness, and the 3rd semiconductor layer can be the second germanium-silicon layer having the second germanium concentration of being greater than the first germanium concentration and have the 3rd thickness being greater than the second thickness.
In certain embodiments, porous region is formed in the top surface of semiconductor base, and semiconductor base is heated to make at least some surface holes in surface holes to close subsequently, make the inside of porous region be porous simultaneously, with the submissive region being semiconductor base by the regions transform of semiconductor base, then, can by chemical vapour deposition (CVD) at porous region Epitaxial growth first semiconductor layer.
In certain embodiments, the first semiconductor layer and the second semiconductor layer can all have the thickness being less than 25nm.
In certain embodiments, the submissive region of semiconductor base can be the porous region in the top surface of silicon base, first semiconductor layer can be silicon layer, second semiconductor layer can be first germanium-silicon layer with the first germanium concentration, and the 3rd semiconductor layer can be second germanium-silicon layer with the second germanium concentration being greater than the first germanium concentration.
In certain embodiments, the germanium concentration of the second germanium-silicon layer can be greater than 75%, and the threading dislocation density in the second germanium-silicon layer can be less than about 1 × 10 5/ cm 2.
In certain embodiments, the gross thickness of silicon layer, the first germanium-silicon layer and the second germanium-silicon layer can be less than 75nm.
In certain embodiments, the porosity of porous region can be at least 30%.
In certain embodiments, relaxation process can be thermal annealing.
In certain embodiments, the 4th semiconductor layer can be formed on the 3rd semiconductor layer, and semiconductor device can be formed at least in part in the 4th semiconductor layer or on the 4th semiconductor layer.
According to other embodiments of the invention, provide the method forming semiconductor device, wherein, in the surface of silicon base, form porous region.Porous region in the surface of silicon base forms silicon layer.Silicon layer is formed first germanium-silicon layer with the first germanium concentration.Then the first germanium-silicon layer relaxation is made.On the first germanium-silicon layer of relaxation, form the second germanium-silicon layer of the second germanium concentration had higher than the first germanium concentration subsequently, the second germanium-silicon layer is formed as strained layer.Then, the second germanium-silicon layer relaxation is made.Second germanium-silicon layer forms semiconductor layer.Finally, semiconductor device is formed in the semiconductor layer at least in part.
In certain embodiments, the step forming porous region in the surface of silicon base comprises and utilizes wet etchant and make electromotive force be applied to the top surface carrying out wet etching semiconductor base between semiconductor base and wet etchant.The method anneals at least one some holes in the top surface of porous region is closed to silicon base before can also being included in formation first germanium-silicon layer.
In certain embodiments, the first semiconductor layer can have the thickness being less than 20nm, and the gross thickness of silicon layer, the first germanium-silicon layer and the second germanium-silicon layer can be less than 75nm.
In certain embodiments, silicon layer only can be weakly bonded to silicon base, thus when tensile stress is applied to silicon layer, silicon layer can move relative to silicon base.
In certain embodiments, the germanium concentration of the second germanium-silicon layer can be greater than 75%, and the threading dislocation density in the second germanium-silicon layer can be less than about 1 × 10 5/ cm 2.
According to other embodiment of the present invention's design, provide semiconductor structure, described semiconductor structure comprises: silicon base; Porous Silicon area, in the top surface of silicon base; Silicon layer, on the top surface of Porous Silicon area; There is the first germanium-silicon layer of the first germanium concentration, on the top surface of silicon layer; And there is second germanium-silicon layer of deformation relaxation of the second germanium concentration being greater than the first germanium concentration, on the top surface of the first germanium-silicon layer.
In certain embodiments, the porosity of porous silicon region can be at least 30%.
In certain embodiments, more than first misfit dislocation may reside in the interface between silicon layer and the first germanium-silicon layer, and silicon layer can have at least 1 × 10 6/ cm 2threading dislocation density, more than second misfit dislocation may reside in the interface between the first germanium-silicon layer and the second germanium-silicon layer, and the first germanium-silicon layer can have at least 1 × 10 6/ cm 2threading dislocation density, the second germanium-silicon layer can have and is less than 1 × 10 5/ cm 2threading dislocation density.
In certain embodiments, the germanium concentration of the second germanium-silicon layer can be greater than 75%.
In certain embodiments, the gross thickness of silicon layer, the first germanium-silicon layer and the second germanium-silicon layer can be less than 75nm.
In certain embodiments, more than first misfit dislocation may reside in the interface between silicon layer and the first germanium-silicon layer, and multiple threading dislocation can extend downward silicon layer from misfit dislocation.
In certain embodiments, silicon layer can have the thickness being less than 20nm, and silicon layer only can be weakly bonded to silicon base, thus when tensile stress is applied to silicon layer, silicon layer can move relative to silicon base.
In certain embodiments, silicon layer can have the first thickness, and the first germanium-silicon layer can have the second thickness being greater than the first thickness, and the second germanium-silicon layer can have the 3rd thickness being greater than the second thickness.
Accompanying drawing explanation
Fig. 1 is the cutaway view being shown schematically in conventional method deformation relaxation germanium-silicon layer being formed strained silicon layer.
Fig. 2 is the cutaway view comprising the semiconductor structure of deformation relaxation layer of the specific embodiment schematically shown according to the present invention's design.
Fig. 3 is the cutaway view comprising the semiconductor structure of deformation relaxation layer of other embodiment schematically shown according to the present invention's design.
Fig. 4 is the schematic diagram of the formation that issuable misfit dislocation and threading dislocation in the sacrifice layer that formed in the technology according to the embodiment conceived according to the present invention are shown.
Fig. 5 A to Fig. 5 F schematically shows the cutaway view comprising the method for the semiconductor structure of deformation relaxation layer according to the formation of the specific embodiment of the present invention's design.
Fig. 6 A is the schematic cross sectional views that the thin silicon-Germanium layer grown on thin silicone layer is shown.
Fig. 6 B is the schematic cross sectional views that the thicker germanium-silicon layer grown on thin silicone layer is shown.
Fig. 7 is the perspective view comprising the semiconductor device of deformation relaxation layer of the embodiment according to the present invention's design.
Fig. 8 is the flow chart of method of the formation deformation relaxation layer of specific embodiment according to the present invention's design.
Fig. 9 is the flow chart of method of the formation deformation relaxation layer of other embodiment according to the present invention's design.
Embodiment
According to the embodiment of the present invention's design, provide the method forming deformation relaxation layer on a semiconductor substrate.Deformation relaxation layer can be the germanium-silicon layer of such as high germanium concentration, and semiconductor base can be body silicon base.In some embodiments of these methods, the wet etching of hydrofluoric acid such as can be used in the top surface of body silicon base to form porous region by performing.Then heat treatment can be performed closed to the hole in the top surface making the porous region of silicon base.Then can at the top surface Epitaxial growth thin silicone layer of porous region.This thin silicone layer can be used as the first sacrifice layer.Due to the porous region in the top of body silicon base, combination between thin silicon epitaxial loayer and the top surface of silicon base can be more weak than general case, thus the top surface of substrate can be " cunning " or submissive relative to thin silicone layer to a certain extent.
Then, the first germanium-silicon layer of the first germanium concentration can be had at silicon layer Epitaxial growth.First germanium-silicon layer can be thin (such as, 10nm to 20nm is thick).First germanium-silicon layer can have relatively high germanium concentration, such as, and the germanium concentration of 50%.In certain embodiments, the silicon layer of the first germanium-silicon layer and lower floor can be strained fully along with growth, and substantially can not have defect along with growth.Thermal anneal process can be performed subsequently, with relaxed silicon layer and the first germanium-silicon layer.Due to these layer of relaxation, so misfit dislocation is formed along the border between silicon layer and the first germanium-silicon layer, and threading dislocation can propagate across silicon layer, and the first germanium-silicon layer can show lower level threading dislocation or even substantially not have threading dislocation.
In certain embodiments, the second germanium-silicon layer of second germanium concentration higher than the first germanium concentration can be had subsequently at the first germanium-silicon layer Epitaxial growth.Along with growth, the second germanium-silicon layer can be strained fully, and the first germanium-silicon layer of lower floor also will be strained during epitaxial growth technology.Then, thermal anneal process can be performed, with relaxation first germanium-silicon layer and the second germanium-silicon layer.Due to these layer of relaxation, so misfit dislocation is formed along the border between the first germanium-silicon layer and the second germanium-silicon layer, and threading dislocation can propagate across the first germanium-silicon layer, but the second germanium-silicon layer can show lower level defect or even substantially not have defect.Next, second germanium-silicon layer can be used as the crystal seed layer of the extra semi-conducting material growing the active area that such as can be used as semiconductor device, and this semiconductor device comprises the such as epitaxially grown germanium for FIN-FET transistor or SiGe fin or strain silicon channel layer.This extra semi-conducting material also can be used as the donor wafer material of the active area for forming semiconductor device on the insulating barrier stacked with semiconductor base.
According to the deformation relaxation germanium-silicon layer of embodiment manufacture of the present invention's design can be the layer of relative thin (such as, in certain embodiments, the a series of layer of growth can have the gross thickness being less than 50nm to 100nm above the top surface of silicon base), and the defect concentration decreased can be had and (such as, may 1 × 10 be had 5/ cm 2or less threading dislocation density).In addition, can be grown as have very high germanium concentration according to the deformation relaxation germanium-silicon layer of the embodiment of the present invention's design, such as, the germanium concentration of 0.9 or even 1.0 (that is, pure germanium), still shows relatively low threading dislocation density simultaneously.In addition, the traditional chemical vapour deposition (CVD) epitaxial growth technology being suitable for extensive manufacture can be utilized to carry out cost according to the deformation relaxation germanium-silicon layer of the embodiment of the present invention's design to be effectively formed in traditional body silicon base.
Although the example embodiment of above-described the present invention's design comprises growth strain relaxed sige layer on a silicon substrate, will be appreciated that technology disclosed herein can be applied in diversified material system.Such as, in other embodiments, can in the lattice mismatch substrate of such as sapphire, silicon or silicon carbide substrate growth strain relaxation Group III-V compound semiconductor layer.
Method and the semiconductor device of the embodiment conceived according to the present invention is discussed in more detail, the example embodiment of these methods shown in the drawings and semiconductor device and intermediate structure now with reference to accompanying drawing.
Fig. 2 is the cutaway view of the semiconductor structure 100 comprising deformation relaxation layer of the specific embodiment schematically shown according to the present invention's design.Semiconductor structure can comprise a part for such as semiconductor crystal wafer or this semiconductor crystal wafer.
As shown in Figure 2, semiconductor structure 100 comprises silicon base 110, such as body silicon base or thick silicon epitaxy layer.Silicon base 110 can comprise p-type silicon base or N-shaped silicon base, and can doped with impurity or the impurity that can undope.The top surface of silicon base 110 can comprise porous region 120.Porous region 120 can comprise the whole top surface of silicon base 110 or can be formed in one or more discrete porous region of the select location in the top surface of silicon base 110.Hole on the upper space of porous region 120 can be closed by suitable process, makes porous region 120 can be used as good crystal seed layer in follow-up epitaxial growth process.Thin silicone layer 130 is arranged on the top surface of porous region 120.Finally, germanium-silicon layer 140 is arranged on the top surface of thin silicone layer 130.
Germanium-silicon layer 140 can be deformation relaxation germanium-silicon layer 140.Multiple misfit dislocation 132 can mainly be formed in semiconductor structure 100 along the interface between thin silicone layer 130 and germanium-silicon layer 140.Threading dislocation 134 can extend from misfit dislocation 132.As shown in Figure 2, threading dislocation 134 can mainly from misfit dislocation 132 to downward-extension, to extend through thin silicone layer 130.Threading dislocation 134 can only diffuse through silicon layer 130, and does not diffuse in the porous region 120 of silicon base 110.Germanium-silicon layer 140 can have low threading dislocation density or substantially can not have threading dislocation 134.
In certain embodiments, silicon layer 130 can be thickness is the thin silicone layer 130 being such as less than 25nm.In certain embodiments, silicon layer 130 can have the thickness being less than 15nm, such as, and the thickness of about 10nm.Silicon layer 130 can comprise the sacrifice layer being easy to accept the threading dislocation 134 extended from misfit dislocation 132, and misfit dislocation 132 is formed in the interface between the silicon layer 130 of lattice mismatch and germanium-silicon layer 140.
Germanium-silicon layer 140 can have various different germanium concentration.Germanium concentration may be selected certain level, makes silicon layer 130 can relaxed sige layer 140.Therefore, in some cases, this can set the enforceable upper limit to germanium concentration.In certain embodiments, although more typically germanium-silicon layer 140 will have constant germanium concentration, germanium-silicon layer 140 can comprise grating layer.If germanium-silicon layer 140 is grating layers, then the average germanium concentration of layer is considered the germanium concentration of layer.
In certain embodiments, the thickness of germanium-silicon layer 140 can be selected as meeting multiple standard.Such as, germanium-silicon layer 140 can have the thickness that is enough to store enough strain energy to make to carry out relaxation to the silicon layer 130 of lower floor during subsequent relaxation processes.In addition, the thickness of germanium-silicon layer 140 can close to " critical thickness " of germanium-silicon layer 140." critical thickness " represents such thickness of germanium-silicon layer 140, namely this thickness enough little make layer will by flexibly strain but will be stable, be meant to be heated to very high temperature even if stable, layer also will keep elastic strain.The critical thickness of germanium-silicon layer 140 is functions of the germanium concentration of such as layer.The thickness of germanium-silicon layer 140 also can be in germanium-silicon layer 140 maximum metastable thickness or close to maximum metastable thickness.Metastable thickness table is shown in the thickness range of the layer that the lattice-matched layers of lower floor grows, and this thickness range is thicker until will there is the thickness of relaxation in growth course than critical thickness.In other words, for the thickness being greater than maximum metastable thickness, because strain energy is greater than the energy that lattice can bear, so dislocation will be there is along with growth by relaxation in layer.The scope of the layer thickness between critical thickness and maximum metastable thickness is referred to as metastable region.The layer with the thickness in metastable region is strained along with growth, but can in response to such as thermal annealing relaxation (and forming dislocation).The maximum metastable thickness of germanium-silicon layer 140 can depend on temperature during germanium concentration and the layer growth of such as layer.By the thickness that germanium-silicon layer 140 is formed as in metastable region, germanium-silicon layer 140 can have relatively few defect or not have defect along with growth, and can apply to the silicon layer 130 of lower floor tensile stress that silicon layer 130 is strained, thus threading dislocation is formed in silicon layer 130, and in germanium-silicon layer 140, do not form threading dislocation.In certain embodiments, germanium-silicon layer 140 can have the thickness of such as approximately 10nm to about 20nm.Germanium-silicon layer 140 can be thicker than silicon layer 130.
Germanium-silicon layer 140 can be used as such as the growing surface of extra semi-conducting material, and described extra semi-conducting material can be used as the active area of the semiconductor device comprising such as strained silicon layer (not shown).In other cases, germanium-silicon layer 140 can be used as the seed surface for growing extra semi-conducting material, and described extra semi-conducting material can be used as the semiconductor device of the germanium fin comprised for FIN-FET transistor.Other application is possible widely.In addition, as explained with reference to Fig. 3 below, germanium-silicon layer 140 can be used as the sacrifice layer of the germanium-silicon layer growing higher concentration on its top surface.
Fig. 3 is the cutaway view comprising the semiconductor device 100' of deformation relaxation layer of other embodiment schematically shown according to the present invention's design.
As shown in Figure 3, semiconductor device 100' is included in the silicon base 110 of semiconductor device 100, porous region 120 and the silicon layer 130 discussed above with reference to Fig. 2.Semiconductor device 100' also comprises germanium-silicon layer 140'.Germanium-silicon layer 140' can be similar to germanium-silicon layer 140 discussed above.But, germanium-silicon layer 140' comprises multiple misfit dislocations 142 of the interface be formed between germanium-silicon layer 140' and germanium-silicon layer 150 (being formed on germanium-silicon layer 140'), and extends downwardly into the multiple threading dislocations 144 the first germanium-silicon layer 140' from misfit dislocation 142.
Second germanium-silicon layer 150 can have the germanium concentration higher than the germanium concentration of the first germanium-silicon layer 140'.Such as, in certain embodiments, the second germanium-silicon layer 150 can have the germanium concentration of 90% or higher.In certain embodiments, the second germanium-silicon layer 150 can be substituted by pure ge layer.In certain embodiments, the second germanium-silicon layer 150 can be such as thickness is the layer of the relative thin being less than 50nm.In certain embodiments, the second germanium-silicon layer 150 can have the thickness such as approximately between 20nm to about 40nm.Second germanium-silicon layer 150 can be thicker than the first germanium-silicon layer 140'.Second germanium-silicon layer 150 can have low threading dislocation density or substantially can not have threading dislocation.
Fig. 4 illustrates growing when the silicon layer of lower floor or suprabasil strain silicon germanium layer are by relaxation, the perspective schematic view how misfit dislocation and threading dislocation can be formed.As shown in Figure 4, silicon germanium extension layer 220 can grow in body silicon base 210.The silicon base lattice mismatch of germanium-silicon layer 220 and lower floor, therefore germanium-silicon layer 220 will strain along with growth.Germanium-silicon layer 220 can be thermally annealed relaxation, and/or growing in the growth course exceeded after maximum metastable thickness by relaxation.In relaxation process, produce misfit dislocation 222 and threading dislocation 224.As shown in Figure 4, two threading dislocations 224 are produced for each misfit dislocation 222, and threading dislocation 224 penetrates into surface.In the silicon/silicon germanium structure of Fig. 4, threading dislocation 224 is in 60 ° usually, this is because they slide on Si (111) lattice plane.As also shown in Figure 4, because body silicon base 210 is hard often, so relaxation is tending towards only occurring in germanium-silicon layer 220, therefore threading dislocation 224 propagates across germanium-silicon layer 220.When germanium-silicon layer 220 is by relaxation, the threading dislocation density in germanium-silicon layer 220 can be very high.Such as, suppose the strain producing 1% in the process forming germanium-silicon layer 220, then by complete for this strain relaxation, and suppose that each threading dislocation has the Burgers vector size of about 5 dusts, then threading dislocation density (TDD) can be calculated as follows:
TDD＝0.01*1cm/5A＝2×10 5/cm(unitlength)(1)
This corresponds to about 1 × 10 10/ cm 2threading dislocation density.
Under many circumstances, this target can be form the deformation relaxation germanium-silicon layer with low threading dislocation density, thus can form strain device layer subsequently on deformation relaxation germanium-silicon layer.According to the embodiment of the present invention's design, deformation relaxation germanium-silicon layer can grow on a silicon substrate under relatively propagating across the condition of silicon layer with germanium-silicon layer at threading dislocation.This can provide the deformation relaxation germanium-silicon layer with low threading dislocation density.
In order to realize this point, sacrificial silicon layer can be grown on the silicon layer of lower floor (such as, body silicon base).This sacrificial silicon layer can be thin layer, thus it by be unlike in utilize body silicon base when hard like that.In addition, sacrificial silicon layer can be formed to make the interface between sacrificial silicon layer and the silicon base of lower floor can be weak, thus sacrificial silicon layer can move relative to silicon base, instead of substantially becomes the extension of silicon base.This weak interface can by such as forming porous region to realize on the upper surface of silicon base, porous region will only with sacrificial silicon layer weak binding.Under these conditions, the strain in germanium-silicon layer can transfer to the interface of the cunning between sacrificial silicon layer and silicon base in relaxation process, and therefore threading dislocation will through sacrificial silicon layer flowing instead of through germanium-silicon layer flowing.
Fig. 5 A to Fig. 5 F is the cutaway view of the method for the semiconductor device 100' of the formation Fig. 3 of the example embodiment schematically shown according to the present invention's design.
As shown in Figure 5 A, the silicon base 110 of such as body silicon base or thick epitaxially grown silicon layer can be provided.Porous region 120 can be formed in the top surface of silicon base 110.Porous region 120 can be formed on the whole top surface of silicon base 110, or can be the pattern of the porous region be such as formed in the top surface of silicon base 110.In the exemplary embodiment, silicon base 110 can comprise p-type silicon base, and its top surface can change porous region 120 into by electrochemical dissolution, electrochemical dissolution is in 40% hydrofluoric acid solution, utilize the voltage drop be applied between wafer and hydrofluoric acid solution to produce anode reaction.Voltage drop can be selected as producing such as about 1 milliampere/cm 2current density, produce speed with the hole arranging about 0.1nm/ second.In certain embodiments, porous region can have the porosity of about 30% to 60%, and wherein porosity is defined as the cumulative volume of volume divided by region 120 in the space of the sky in porous region 120.Guaranteeing that porous region 120 has the balance that enough mechanical strengths fully weaken shearing force silicon layer 130 being attached to porous region 120 simultaneously by comprising, different porosity value can be used.Porosity also can be selected as enough low, and surface pore easily can be closed in follow-up treatment step.Porosity in porous region 120 can such as control for the electric current reacted by regulating.The thickness of porous region 120 can suitably change.In certain embodiments, the layer of porous region 120 can be thickness be about 50nm to 2000nm.
For N-shaped silicon base 110, above-described identical wet etch techniques can be used, and can be aided with in wet etching process process substrate irradiation light.Photon from light can as catalyst, and to improve etch-rate, if not, etch-rate can be slower than the etch-rate in N-shaped silicon.
Although wet etching is a kind of possible method for the formation of porous region 120, will be appreciated that in other embodiments, other technology can be used.Such as, alternatively, porous region 120 can pass through ion (such as, such as nitrogen (N 2) or helium (He 2) electric neutrality ion) bombardment formed.Also other technology can be used.
Once porous region 120 is formed in the top surface of silicon base 110, then can pass through such as at hydrogen (H 2) in carry out thermal annealing to semiconductor structure 100' closed to the hole in the topmost portion making porous region 120.Annealing temperature can be selected as enough high to be made the top surface of porous region 120 subside by reflux technique, thus, but be also selected as enough low to reduce the sintering effect that internal holes may be made to subside. in close timepiece face at least partiallyIn certain embodiments, by carrying out original position chlorine (Cl to porous region 120 before hydrogen annealing 2) annealing, lower annealing temperature can be used.Hole in the upper space of closed porous region can make porous region 120 be used as good crystal seed layer in the growth course of follow-up silicon epitaxy layer 130.Hydrogen annealing also contributes to removing natural oxide from the top surface of porous region 120.
In certain embodiments, porous region 120 can have the high porosity of such as 50%.This high porosity can make the shear strength between the silicon epitaxy layer 130 of porous region 120 and subsequent growth die down.
With reference to Fig. 5 B, on the upper space of porous region 120, epitaxially thin silicone layer 130 can be grown by such as chemical vapour deposition (CVD).In certain embodiments, the thin layer of silicon layer 130 can be thickness be 5nm to 10nm.Silicon layer 130 can have enough thickness, to guarantee that the hole in porous region 120 is adequately covered.Due to the weak shear strength between porous region 120 and thin silicone layer 130, so when tensile stress is applied to silicon layer 130, silicon layer 130 can show as similar can relative to the film of freely movement relative to porous region 120.Silicon layer 130 and its growth porous region 120 Lattice Matching thereon, therefore silicon layer 130 can along with growth by relaxation.
With reference to Fig. 5 C, next, on the upper surface of thin silicone layer 130, the first germanium-silicon layer 140 of relative thin epitaxially can be grown.First germanium-silicon layer 140 can have relatively high germanium concentration, such as in certain embodiments, and such as 50% (that is, Si 0.5ge 0.5layer) or higher germanium concentration.In certain embodiments, the thickness of the first germanium-silicon layer 140 can be selected as making the first germanium-silicon layer 140 by substantially fully strain along with growth, have low dislocation density, enough thick with in relaxation step process, its strain energy all can be passed to silicon layer 130 and enough thin with by annealing steps by relaxation.First germanium-silicon layer 140 can be thicker than silicon layer 130.In certain embodiments, suppose that germanium concentration is about 40% to 60%, then the first germanium-silicon layer can have the thickness of such as approximately 10nm to 20nm.The thickness of the first germanium-silicon layer 140 can according to comprise its germanium concentration and lower floor silicon layer 130 thickness etc. multiple parameter and change.Can optimum thickness be there is, with make the threading dislocation density in the first germanium-silicon layer 140 reduce and/or minimized.First germanium-silicon layer 140 not with silicon layer 130 lattice mismatch of lower floor.Subsequently, silicon layer 130 and the first germanium-silicon layer 140 all can be strained along with growth fully.In certain embodiments, silicon layer 130 and the first germanium-silicon layer 140 all can not have defect along with growth.
With reference to Fig. 5 D, semiconductor structure 100' thermal annealing can be made subsequently, with relaxed silicon layer 130 and the first germanium-silicon layer 140.This thermal annealing such as can perform at epitaxial growth reactor situ.In the exemplary embodiment, semiconductor structure 100' can with the annealing temperature 0.5 minute to 30 minutes of 800 DEG C in hydrogen environment.After this thermal annealing completes, silicon layer 130 and the first germanium-silicon layer 140 all can by relaxation.Along with growth (that is, before thermal annealing), silicon layer 130 can stand tensile stress and the first germanium-silicon layer 140 be formed thereon can through compression chord.As shown in fig. 5d, along with these layers relaxation in thermal annealing process, misfit dislocation 132 can be formed along the interface between silicon layer 130 and the first germanium-silicon layer 140.The layer standing tensile stress can be easier to form threading dislocation.Silicon layer 130 and the tensile stress from the first germanium-silicon layer 140 formed on top of this work and complete relaxation with height of formation defect layer.On the contrary, because strain is directed to the silicon layer 130 of lower floor, so the first germanium-silicon layer 140 relaxation can be formed to have little defect or not have defect formation.Subsequently, final result is that the threading dislocation 134 that possible extend from each end of each misfit dislocation 132 can be formed in silicon layer 130 generally, and the first germanium-silicon layer 140 can have the threading dislocation density that reduces or even substantially not have threading dislocation.
As discussed above, because porous region 120 can have the weak shear strength with silicon layer 130, thus porous region 120 can be submissive or " sliding " relative to silicon layer 130 in a way, so silicon layer 130 can be tending towards showing as with floating film similar.Silicon layer 130 can react with the tensile stress being applied to it from the first germanium-silicon layer 140 above and can substantially fully relaxation, forms threading dislocation wherein with the appearance along with relaxation.On the other hand, due in thermal annealing process, main strain is directed in silicon layer 130, so the first germanium-silicon layer 140 can relaxation, is formed with that have minimizing or minimum defect.Therefore, silicon layer 130 can as the sacrifice layer of growth contributing to the first germanium-silicon layer 140 decreasing defect, if do not provide the combination reduced, then silicon layer 130 will form the structure integrated with the silicon base 110 of lower floor, and will the structure of relative rigid be shown as, thus in relaxation annealing process, the first germanium-silicon layer 140 can not transmit strain to silicon layer 130/ silicon base 110.
With reference to Fig. 5 E, can epitaxially grow the second germanium-silicon layer 150 on the upper surface of the first germanium-silicon layer 140 subsequently.Second germanium-silicon layer 150 can have the germanium concentration higher than the germanium concentration of the first germanium-silicon layer 140.In certain embodiments, 0.9 or higher the second germanium-silicon layer 150 (such as, Si of germanium concentration 0.1ge 0.9layer) in can comprise very high germanium concentration.In fact, in certain embodiments, the second germanium-silicon layer can be substituted by pure ge layer.Tensile stress can be applied to the first germanium-silicon layer 140 of the lower germanium concentration under it by the higher germanium concentration comprised in the second germanium-silicon layer 150 (or pure ge layer 150).The thickness of the second germanium-silicon layer 150 can be selected as that the second germanium-silicon layer 150 will substantially fully be strained again, have low-dislocation-density and enough thick thus enable it in relaxation step process, its whole strain energy is passed to the first germanium-silicon layer 140.In certain embodiments, the second germanium-silicon layer can have the thickness of the rank of such as approximately 20nm to 40nm.Thickness can be selected as being wide enough so that the second germanium-silicon layer 150 can store enough strain energies, thus make the second germanium-silicon layer 150 grow the first germanium-silicon layer 140 thereon can by relaxation fully in follow-up processing step.Second germanium-silicon layer 150 can be thicker than the first germanium-silicon layer 140.Due to higher germanium concentration, thus the second germanium-silicon layer 150 not with the first germanium-silicon layer 140 lattice mismatch of lower floor.Therefore, the first germanium-silicon layer 140 and the second germanium-silicon layer 150 can strain fully along with growth.Second germanium-silicon layer 150 can not have defect substantially along with growth.
With reference to Fig. 5 F, next, semiconductor structure 100' thermal annealing can be made, with relaxation first germanium-silicon layer 140 and the second germanium-silicon layer 150.This thermal annealing can such as perform at epitaxial growth reactor situ.In the exemplary embodiment, semiconductor base 100' can with the annealing temperature time period of 30 seconds to 30 minutes of about 800 DEG C in hydrogen environment.As shown in Fig. 5 F, after this thermal annealing completes, the first germanium-silicon layer 140 and the second germanium-silicon layer 150 can by relaxation.In thermal annealing process, the first germanium-silicon layer 140 can be subject to tensile stress, and the second germanium-silicon layer 150 be formed thereon can be subject to compression.Along with these layers relaxation in thermal annealing process, misfit dislocation 142 can be formed along the interface between the first germanium-silicon layer 140 and the second germanium-silicon layer 150.Threading dislocation 144 can be easy to due to tensile stress be formed in the first germanium-silicon layer 140, and the second germanium-silicon layer 150 can have the threading dislocation density that decreases or even substantially not have threading dislocation.Second germanium-silicon layer 150 can be used as the crystal seed layer of the formation of follow-up thicker SiGe or germanium layer, or alternatively, second germanium-silicon layer 150 can be used as the crystal seed layer for one or more semiconductor layer, and described semiconductor layer is used as the active area for different semiconductor device.
In certain embodiments, the gross thickness of silicon layer 130 and the first germanium-silicon layer 140 and the second germanium-silicon layer 150 can be less than about 50nm to 100nm, such as, can be less than about 75nm.The order of magnitude that this deformation relaxation germanium-silicon layer (can be tens or hundreds of micron thickness) that can be Billy grows on body silicon wafer with traditional grating growing technology is thin.In addition, deformation relaxation germanium-silicon layer 150 can have very high germanium concentration, low dislocation density, and can grow in such as traditional body silicon base, and does not need the silicon-on-insulator substrate that uses costly.
Can be used to make multiple different technology become possibility according to the high germanium concentration of the embodiment formation of the present invention's design, low defect deformation relaxation germanium-silicon layer, such as, SiGe-CMOS technology N-shaped silicon/p-type germanium system, or SiGe-CMOS technology p-type silicon/N-shaped germanium system.These technology can be implemented in common silicon base.
As mentioned above, porous region 120 can be formed the whole top surface striding across silicon base 110, then the thin silicone layer 130 before one or more germanium-silicon layer 140,150 a series of can grow thereon, wherein, germanium-silicon layer 140,150 can have the germanium concentration increased, and makes top germanium-silicon layer have the germanium concentration of expectation.After forming so final (top) germanium-silicon layer, mask layer can be formed on the top surface of semiconductor structure, and this structure can be etched, to remove a part for a series of germanium-silicon layer from the selected region of this structure, thus exposed silicon areas (or alternatively, exposing the part below porous region of silicon base).Then, silicon layer can epitaxially grow in the more removed regions of germanium-silicon layer wherein or Zone Full, thus provides the structure having and be formed in the silicon area in one silicon base and high germanium concentration silicon Germanium regions (or pure germanium district).
It is believed that, technology according to the embodiment of the present invention's design can provide medium germanium concentration (such as in the body silicon base of standard, the germanium concentration of 40% to 75%) or the germanium-silicon layer of high germanium concentration (such as, the germanium concentration of 75% to 100%), it has and is less than 1 × 10 6/ cm 2even be less than 1 × 10 5/ cm 2or 1 × 10 4/ cm 2threading dislocation density.
The embodiment of the present invention's design can utilize the imbalance of the strain energy between two different semi-conducting materials.Such as, consider the material system 300 shown in Fig. 6 A, wherein, there is thick germanium-silicon layer 320 epitaxial growth of the 3nm of the germanium concentration of 50% on the thick silicon layer 310 of 3nm.Here, the stress caused by lattice mismatch should balance in this two-layer system with contrary sign, that is, germanium-silicon layer 320 will be subject to compression and silicon layer 310 will be subject to tensile stress.In this case, because germanium-silicon layer 320 is subject to compression, so in relaxation annealing process, threading dislocation is not easy to be formed in germanium-silicon layer 320.Be difficult to prediction threading dislocation whether will be formed in silicon layer 310.
As depicted in figure 6b, the situation shown in Fig. 6 A can be revised, make germanium-silicon layer 370 epitaxial growth that the 30nm of the germanium concentration with 50% is thick on the thick silicon layer 360 of 10nm.In this case, the strain energy of thicker germanium-silicon layer 370 is subject in the thinner silicon layer 360 of tensile stress by being forced to enter, with the misfit dislocation 362 producing the interface between two-layer and the threading dislocation 364 extended in silicon layer 360, relaxed sige layer 370 thus.Therefore, Fig. 6 B show may be used for by threading dislocation 364 directly under be directed to mechanism in silicon layer 360.But, in order to realize this point, need to be in by germanium-silicon layer 370 the thin silicon layer 360 being subject to tensile stress state.As discussed above, in certain embodiments, this can, by growing silicon layer 360 on the porous region of silicon base, make silicon layer 360 can show as the similar film floated in substrate.
According to other embodiment of the present invention's design, the basal surface of growth thin silicone layer on a silicon substrate can be manufactured to " cunning ".Can do like this to replace forming porous region on the top surface of silicon base, or can also do like this except forming porous region.In certain embodiments, the basal surface of silicon layer can grow at low temperatures, to form the silicon of the height defect that can not be combined well with silicon base.Remaining silicon layer can grow at a higher temperature, with in order to by the bottom of drawbacks limit in this thin silicone layer.
Will be appreciated that, although above-described embodiment provides one (Fig. 2) or two (Fig. 3 and Fig. 5 A to Fig. 5 F) germanium-silicon layers and is formed example on a silicon substrate, but the germanium-silicon layer of greater number in other embodiments, can be formed.Such as, in another embodiment, a Si 0.7ge 0.3layer can be formed on thin silicone layer, then the 2nd Si 0.4ge 0.6layer can be formed in Si 0.7ge 0.3on layer, then Si 0.1ge 0.9layer can be formed in Si 0.4ge 0.6on layer.Should " three layers " scheme can (1) assist in ensuring that the germanium-silicon layer that can grow and have and be less than maximum metastable thickness and (2) due between adjacent layer closer to Lattice Matching and lower defect level can be shown.Will be appreciated that the germanium concentration of each layer can be different from the germanium concentration quoted in above-mentioned example, the quantity of layer can more than three, and/or identical scheme may be used for the lattice mismatching material system except silicon/silicon germanium material system.
An application according to the device of the embodiment formation of the present invention's design can be applied to the germanium fin forming FIN-FET transistor particularly.The maximum height of the germanium fin that can relatively grow is the function of the germanium concentration of the deformation relaxation germanium-silicon layer of lower floor zero defect.Such as, complete relaxation and flawless Si 0.3ge 0.7deformation relaxation layer can have the growth zero defect germanium fin being less than 10nm thereon.This fin height may be not enough to the integrated level supporting to expect.On the contrary, complete relaxation and flawless Si 0.1ge 0.9deformation relaxation layer can support the zero defect germanium fin more than 100nm grown thereon.This fin height can support significantly higher integrated level.Therefore, utilize the technology of the embodiment according to the present invention's design, growth phase should be used for saying can be very useful to the ability of the deformation relaxation germanium-silicon layer of flawless very high germanium concentration for this.Fig. 7 is the perspective view that the FinFET 400 that can grow on the semiconductor structure (such as, the semiconductor structure 100 of Fig. 2 to Fig. 3 and 100') of some embodiments conceived according to the present invention is shown,
With reference to Fig. 7, FinFET 400 comprises the fin 410 outstanding from the upper surface of semiconductor structure 100' along first direction D1.Fin 410 can be formed on second germanium-silicon layer 150 (or in the Fig. 7 being formed in above germanium-silicon layer 150 unshowned semiconductor layer) of semiconductor 100', second germanium-silicon layer 150 can have the germanium concentration (as mentioned above, or can or even pure ge layer) of such as 90%.Fin 410 can be the semi-conducting material identical with the material of the upper surface of semiconductor structure 100', therefore in this embodiment, also can be germanium concentration be 90% germanium-silicon layer.Therefore, fin 410 can with the semiconductor structure 100' Lattice Matching of lower floor.Fin 410 longitudinally can extend along the second direction D2 perpendicular to first direction D1.The lower wall of fin 410 can be covered by device isolation layer 450, and the upper side wall of fin 410 can expose.
To be arranged on fin 410 along the gate electrode 430 not only extended perpendicular to first direction D1 but also perpendicular to the third direction D3 of second direction D2 and to stride across fin 410.Gate electrode 430 is around the top surface of fin 410 and two upper side walls.Gate electrode 430 can be metal level.Gate insulation layer 440 can be arranged between gate electrode 430 and fin 410.Gate insulation layer 440 can be the metal oxide layer that dielectric constant is greater than the dielectric constant of silica.Source/drain region doped with dopant can be formed in fin 410 in the both sides of gate electrode 430.
The part covered by gate electrode 430 of fin 410 can correspond to channel region.
Fig. 8 is the flow chart of method of the formation deformation relaxation layer of specific embodiment according to the present invention's design.As shown in Figure 8, according to these methods, porous region (frame 500) can be formed in the surface of semiconductor base.Then on the porous region of semiconductor base, the semiconductor layer (frame 510) with semiconductor base Lattice Matching is formed.Then, can be formed on the first semiconductor layer and the second semiconductor layer of the first semiconductor layer lattice mismatch (frame 520).Second semiconductor layer can strain along with growth.Then, the second semiconductor layer can by the relaxation process of such as thermal annealing relaxation (frame 530).Then, the 3rd semiconductor layer (frame 540) with the second semiconductor layer Lattice Matching can optionally be formed on the second semiconductor layer.3rd semiconductor layer can strain along with growth.Then, the 3rd semiconductor layer can by the relaxation process of such as thermal annealing relaxation (frame 550).
Fig. 9 is the flow chart of method of the formation deformation relaxation layer of other embodiment according to the present invention's design.As shown in Figure 9, according to these methods, the first semiconductor layer (frame 600) with submissive semiconductor base Lattice Matching can be formed on submissive semiconductor base.Then, can be formed on the first semiconductor layer and the second semiconductor layer of the first semiconductor layer lattice mismatch (frame 610).Then, the first semiconductor layer and the second semiconductor layer can by the relaxation process of such as thermal annealing relaxation (frame 620).Then, the 3rd semiconductor layer (frame 630) with the second semiconductor layer Lattice Matching can selectively be formed on the second semiconductor layer.Then, the second semiconductor layer and the 3rd semiconductor layer can by the relaxation process of such as thermal annealing relaxation (frame 640).
Therefore, according to the embodiment of the present invention's design, deformation relaxation germanium-silicon layer can be formed in the body silicon base of lattice mismatch, and wherein deformation relaxation germanium-silicon layer (1) can have high germanium concentration and (2) can not have threading dislocation substantially.These strain relaxed buffer can be formed to have relatively little gross thickness, such as, be less than the thickness of 100nm or be even less than the thickness of 50nm.Deformation relaxation layer can very effectively utilize and is suitable for the extensive traditional chemical vapour deposition (CVD) epitaxial growth technology manufactured and is formed in traditional body silicon base by cost.
Here, threading dislocation density is defined as the number of dislocations of every square centimeter.Will be appreciated that threading dislocation density can be measured in many ways, described mode comprises such as measures etch-pit density, TEM, plane graph TEM and HR-XRD.
Although above main with reference to one of them or more the deformation relaxation germanium-silicon layer embodiment be formed on a silicon substrate discuss the present invention's design, will be appreciated that technology disclosed herein can be applied in diversified material system.Such as, in other embodiments, the III-V compound semiconductor layer of technology growth deformation relaxation disclosed herein can be utilized, such as, the In of growth strain relaxation on GaAs xga 1-xthe GaAs layer of As layer, on a silicon substrate growth strain relaxation and/or grow short wavelength II-VI race of race or long wavelength's III-V race laser structure in GaAs substrate.In addition, will be appreciated that technology used herein not only can be provided for the strained channel layer of the semiconductor device showing higher carrier mobility, other object can also be used for, such as, for changing the band gap of semi-conducting material for optics object.
Above with reference to the embodiment drawings describing the present invention's design, illustrated therein is example embodiment.But the present invention's design can be implemented in many different forms, and should not be construed as limited to the embodiment set forth here.On the contrary, provide these embodiments, make the disclosure to be thoroughly with complete, and scope of the present invention will be conveyed to those skilled in the art fully.Same label indicates same element in the accompanying drawings and the description all the time.As used herein, state "and/or" and comprise one or more relevant combination in any of lising and all combinations.
Although will be appreciated that and the term of first, second grade can be used here to describe different elements, these elements should by the restriction of these terms.These terms are only for separating an element with another element region.Such as, without departing from the scope of the invention, the first element can be named as the second element, and similarly, the second element can be named as the first element.
Will be appreciated that, when element be referred to as " being connected to " or " being attached to " another element or " " another element " on " time, this element can be directly connected to or directly be attached to another element described or directly on another element described, or also can there is intermediary element.On the contrary, when element be referred to as " being directly connected to " or " being directly attached to " another element or " directly existing " another element " on " time, there is not intermediary element.Other word for describing the relation between element should be explained in a similar manner (that is, " ... between " with " and directly exist ... between ", " adjacent " and " direct neighbor " etc.).
Here can use such as " ... below " or " in ... top " or " on " or D score or " being parallel to " or " perpendicular to " relative terms element, layer or a region as illustrated in the drawings and the relation between another element, layer or region are described.Will be appreciated that these terms intention comprises the different azimuth of the device except the orientation described in the accompanying drawings.
Term used herein only for describing the object of specific embodiment, and is not intended to limit the present invention.As used herein, unless context is clearly pointed out in addition, otherwise singulative " ", " one " and " being somebody's turn to do " are also intended to comprise plural form.It will also be understood that, " comprise " when using term in this manual and/or " comprising " time, illustrate to there is described feature, element and/or assembly, but do not get rid of and exist or additional one or more further feature, element, assembly and/or their group.
The embodiment of the present invention's design has been described at the cutaway view above with reference to the desirable embodiment (and intermediate structure) schematically showing the present invention's design.For the sake of clarity, the thickness in layer in the accompanying drawings and region can be exaggerated.In addition, the change by there is the illustrated shape occurred due to such as manufacturing technology and/or tolerance is estimated.Therefore, embodiments of the invention should not be construed as limited to the specific shape of shown here and region, but comprise the deviation of the shape caused owing to such as manufacturing.
Whole embodiment by any way and/or can combine and combine.
In the accompanying drawings and the description, disclose exemplary embodiments of the present invention, although employ specific term, but only use them with general with descriptive meaning, instead of for the object limited, scope of the present invention is set forth in the claims.

Claims (20)

1. a deformation relaxation method, described method comprises the steps:
Porous region is formed in the surface of semiconductor base;
Porous region in the surface of semiconductor base is formed the first semiconductor layer with semiconductor base Lattice Matching;
Form the second semiconductor layer on the first semiconductor layer, the second semiconductor layer is formed as strained layer; And
Relaxation second semiconductor layer.
2. the method for claim 1, described method also comprises the steps:
Second semiconductor layer of relaxation forms the 3rd semiconductor layer, and the 3rd semiconductor layer is formed as strained layer; And
Relaxation the 3rd semiconductor layer.
3. the step the method for claim 1, wherein forming porous region in the surface of semiconductor base comprises and utilizes wet etchant and make electromotive force be applied to the top surface carrying out wet etching semiconductor base between semiconductor base and wet etchant.
4., the method for claim 1, wherein before relaxation second semiconductor layer, the first semiconductor layer is subject to tensile stress, and the second semiconductor layer is subject to compression.
5. the method for claim 1, wherein the first semiconductor layer is only weakly bonded to semiconductor base, thus when tensile stress is applied to the first semiconductor layer, the first semiconductor layer can move relative to semiconductor base.
6. the method for claim 1, wherein the first semiconductor layer is formed directly on the porous zone on the surface being arranged in semiconductor base, and the second semiconductor layer is formed directly on the first semiconductor layer.
7. method as claimed in claim 2, wherein, semiconductor base comprises silicon base, and the first semiconductor layer comprises silicon layer, second semiconductor layer comprises the germanium-silicon layer with the first germanium concentration, and the 3rd semiconductor layer comprises second germanium-silicon layer with the second germanium concentration being greater than the first germanium concentration.
8. method as claimed in claim 7, wherein, the germanium concentration of the second germanium-silicon layer is greater than 75%, and the threading dislocation density in the second germanium-silicon layer is less than about 1 × 10 5/ cm 2.
9. method as claimed in claim 7, wherein, the gross thickness of silicon layer, the first germanium-silicon layer and the second germanium-silicon layer is less than 75nm.
10. the method for claim 1, described method also comprises the steps:
Second semiconductor layer forms the 4th semiconductor layer; And
Semiconductor device is formed at least in part on the 4th semiconductor layer or in the 4th semiconductor layer.
11. 1 kinds of methods forming deformation relaxation semiconductor layer, described method comprises the steps:
First semiconductor layer is formed on the top in the submissive region of semiconductor base, semiconductor base and the first semiconductor layer Lattice Matching, make the first semiconductor layer only be weakly bonded to the submissive region of semiconductor base, and can on the top surface in the submissive region of semiconductor base transverse shifting;
Form the second semiconductor layer with the first semiconductor layer lattice mismatch on the first semiconductor layer; And
Perform relaxation process to the second semiconductor layer, described relaxation process produces threading dislocation in the first semiconductor layer, makes the second semiconductor layer substantially not have threading dislocation simultaneously.
12. methods as claimed in claim 11, described method also comprises the steps:
Second semiconductor layer is formed the 3rd semiconductor layer with the second semiconductor layer lattice mismatch; And
Perform relaxation process to the 3rd semiconductor layer, described relaxation process produces threading dislocation in the second semiconductor layer, makes the 3rd semiconductor layer substantially not have threading dislocation simultaneously.
13. methods as claimed in claim 12, wherein, the first semiconductor layer was subject to tensile stress before relaxation, and the second semiconductor layer was subject to compression before relaxation.
14. methods as claimed in claim 11, wherein, the step that the top in the submissive region of semiconductor base is formed the first semiconductor layer comprises the steps:
In the top surface of semiconductor base, form porous region, then heating semiconductor substrate is closed to make at least some surface holes in surface holes, makes the inside of porous region be porous, with the submissive region being semiconductor base by the regions transform of semiconductor base simultaneously; And
Then by chemical vapour deposition (CVD) growth regulation semi-conductor layer on porous region.
15. methods as claimed in claim 12, wherein, the submissive region of semiconductor base is included in the porous region in the top surface of silicon base, first semiconductor layer comprises silicon layer, second semiconductor layer comprises first germanium-silicon layer with the first germanium concentration, and the 3rd semiconductor layer comprises second germanium-silicon layer with the second germanium concentration being greater than the first germanium concentration.
16. methods as claimed in claim 15, wherein, the germanium concentration of the second germanium-silicon layer is greater than 75%, and the threading dislocation density in the second germanium-silicon layer is less than about 1 × 10 5/ cm 2.
17. methods as claimed in claim 16, wherein, the gross thickness of silicon layer, the first germanium-silicon layer and the second germanium-silicon layer is less than 75nm.
18. methods as claimed in claim 15, wherein, porous region has the porosity of at least 30%.
19. 1 kinds of methods forming semiconductor device, described method comprises the steps:
Porous region is formed in the top surface of silicon base;
Porous region in the surface of silicon base forms silicon layer;
Silicon layer is formed first germanium-silicon layer with the first germanium concentration;
Relaxation first germanium-silicon layer;
First germanium-silicon layer of relaxation is formed second germanium-silicon layer with the second germanium concentration being greater than the first germanium concentration, and the second germanium-silicon layer is formed as strained layer;
Relaxation second germanium-silicon layer;
Second germanium-silicon layer forms semiconductor layer; And
Form semiconductor device in the semiconductor layer at least in part.
20. methods as claimed in claim 19, wherein, the step forming porous region in the surface of silicon base comprises and utilizes wet etchant and make electromotive force be applied to the top surface carrying out wet etching semiconductor base between semiconductor base and wet etchant, and described method anneals to make at least one some holes of the top surface of porous region to close to silicon base before being also included in formation first germanium-silicon layer.
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