CN105183431B

CN105183431B - A kind of cpu busy percentage control method and device

Info

Publication number: CN105183431B
Application number: CN201510476043.1A
Authority: CN
Inventors: 郭瑞; 乔强国
Original assignee: Raisecom Technology Co Ltd
Current assignee: Raisecom Technology Co Ltd
Priority date: 2015-08-05
Filing date: 2015-08-05
Publication date: 2018-09-28
Anticipated expiration: 2035-08-05
Also published as: CN105183431A

Abstract

The invention discloses a kind of method and devices of control cpu busy percentage,The utilization rate of central processor CPU is detected first,If the utilization rate of CPU is greater than or equal to first threshold,Then judge that the first buffer queue into grouping chip sends the minimum guaranteed rate for inhibiting the transmission rate of data packet whether to be less than the first buffer queue,If,Then improve the transmission rate for being sent to the first buffer queue and inhibiting data packet,Wherein,First buffer queue is for caching all control data bags for being sent to the CPU,Inhibition data packet in first buffer queue is dropped after going out team from the buffer queue,And the priority of the first inhibition data packet in buffer queue is higher than the priority of the control data bag in the first buffer queue,Therefore it improves and inhibits data packet to send the transmission rate that can reduce the control data bag in the first buffer queue into the first buffer queue,To realize cpu busy percentage is controlled by controlling the rate into the control data bag of CPU.

Description

A kind of cpu busy percentage control method and device

Technical field

The present invention relates to computer communication technology field more particularly to a kind of cpu busy percentage control method and device.

Background technology

In switching equipment and routing device, grouping chip is responsible for the work of data plane, for example, data packet forwarding or Person route, and CPU (Central Processing Unit, central processing unit) is responsible for the work of control plane, such as protocol processes Work, coprocessor can also share the work of some protocol processes.

Cpu busy percentage refers to accounting for the percentage of actual run time the time of CPU actual treatments data in a period of time, is Reflect CPU working conditions and the index for the treatment of effeciency.Mainly there are two aspects for the factor of influence cpu busy percentage, are on the one hand objects Director's part, such as port connect or disconnect, and physical temperature is too high or too low etc.；On the other hand it is impact of the data packet to CPU, one As in the case of, the rate for being sent to the data packet of CPU is higher, bigger to the impact of CPU, and the utilization rate of CPU is higher.

Under switching equipment or routing device normal operating conditions, the number that physical event occurs is impacted much smaller than data packet The number of CPU, therefore the data packet for entering CPU is controlled, become the key of control cpu busy percentage height.

Invention content

The embodiment of the present invention provides a kind of cpu busy percentage control method and device, to the utilization rate for combining CPU current, By the way of inhibiting data packet to tie up control data bag, effective control to cpu busy percentage is realized.

The embodiment of the present application provides a kind of cpu busy percentage control method, and this method includes：

Detect the utilization rate of central processor CPU；

If the utilization rate of the CPU is greater than or equal to first threshold, the first buffer queue into grouping chip is judged Send the minimum guaranteed rate for inhibiting the transmission rate of data packet whether to be less than first buffer queue, wherein described first Buffer queue is for caching all control data bags for being sent to the CPU, the inhibition data packet in first buffer queue It is dropped after going out team from the buffer queue；

If so, improving the transmission rate for being sent to first buffer queue and inhibiting data packet；Wherein, described first is slow Deposit priority of the priority higher than the control data bag in first buffer queue of the inhibition data packet in queue.

The application is that embodiment provides a kind of cpu busy percentage control device, which includes：

Probe unit, the utilization rate for detecting central processor CPU；

Judging unit, for judge CPU utilization rate whether be greater than or equal to first threshold, and judge to grouping chip In the first buffer queue send inhibit data packet transmission rate whether be less than first buffer queue minimum guarantee speed Rate, wherein first buffer queue is for caching all control data bags for being sent to the CPU, first caching team Inhibition data packet in row is dropped after going out team from the buffer queue；

Inhibit unit, for being greater than or equal to first threshold, and the first caching into grouping chip when the utilization rate of CPU Queue sends the minimum guaranteed rate for inhibiting the transmission rate of data packet to be less than first buffer queue, then improves to described the One buffer queue sends the transmission rate for inhibiting data packet；Wherein, the inhibition data packet in first buffer queue is preferential Priority of the grade higher than the control data bag in first buffer queue.

In the embodiment of the present invention, the rate of CPU is entered by control control data bag to reach the effect for reducing cpu busy percentage Fruit, wherein detect the utilization rate of central processor CPU first, if the utilization rate of CPU is greater than or equal to first threshold, judge The first buffer queue into grouping chip, which is sent, inhibits whether the transmission rate of data packet is less than the minimum of the first buffer queue Guaranteed rate, if so, improving the transmission rate for being sent to the first buffer queue and inhibiting data packet, wherein the first buffer queue For caching all control data bags for being sent to the CPU.Since the inhibition data packet in the first buffer queue is slow from this The priority for the inhibition data packet being dropped after queue goes out team and in the first buffer queue is deposited higher than in the first buffer queue The priority of control data bag inhibits data packet to tie up control data bag to be formed, therefore improves to the first caching Data packet is inhibited to send the transmission rate that can reduce the control data bag in the first buffer queue in queue, it is logical to realize Rate of the control into the control data bag of CPU is crossed to control cpu busy percentage.

Description of the drawings

To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment Attached drawing is briefly introduced, it should be apparent that, drawings in the following description are only some embodiments of the invention, for this For the those of ordinary skill in field, without having to pay creative labor, it can also be obtained according to these attached drawings His attached drawing.

Fig. 1 is the equipment inner structure figure that the embodiment of the present invention is applicable in；

Fig. 2 is cpu busy percentage control flow schematic diagram provided in an embodiment of the present invention；

Fig. 3 is cpu busy percentage controling device structure diagram provided in an embodiment of the present invention；

Fig. 4 is cpu busy percentage detection device structural schematic diagram provided in an embodiment of the present invention；

Fig. 5 is the schematic diagram that the cpu busy percentage starting stage is detected in the embodiment of the present invention；

Fig. 6 is the correspondence figure of cpu busy percentage and the residence time of probe data packet in the embodiment of the present invention；

Fig. 7 is cpu busy percentage control flow schematic diagram provided in an embodiment of the present invention；

Fig. 8 is cpu busy percentage control flow schematic diagram provided in an embodiment of the present invention；

Fig. 9 is cpu busy percentage detection device structural schematic diagram provided in an embodiment of the present invention；

Figure 10 is cpu busy percentage detection device structural schematic diagram provided in an embodiment of the present invention；

Figure 11 is the structure principle chart of control cpu busy percentage device provided in an embodiment of the present invention；

Figure 12 is at the first processing stage and second of the process of inhibition of control data bag provided in an embodiment of the present invention The flow chart in reason stage；

Figure 13 is the first processing stage and second of the process of expansion of the control data bag provided in the embodiment of the present invention The flow chart of processing stage；

Figure 14 is that speed limit keg inhibits schematic diagram in the embodiment of the present invention；

Figure 15 is that speed limit drum and speed limit keg inhibit schematic diagram jointly in the embodiment of the present invention；

Figure 16 is the flow chart of cpu busy percentage control method of the embodiment of the present invention；

Figure 17 is the flow chart of the process of inhibition of cpu busy percentage control method of the embodiment of the present invention；

Figure 18 is the flow chart of the process of expansion of cpu busy percentage control method of the embodiment of the present invention；

Figure 19 is the system schematic that the embodiment of the present invention controls cpu busy percentage；

Figure 20 is the system schematic of another control cpu busy percentage of the embodiment of the present invention

Specific implementation mode

To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing to the present invention make into It is described in detail to one step, it is clear that the described embodiments are only some of the embodiments of the present invention, rather than whole implementation Example.Based on the embodiments of the present invention, obtained by those of ordinary skill in the art without making creative efforts All other embodiment, shall fall within the protection scope of the present invention.

Fig. 1 schematically illustrates the internal structure of the applicable equipment of the embodiment of the present invention.The equipment can be router Or interchanger or other equipment that can realize data forwarding function.

As shown in Figure 1, the equipment may include：CPU101, coprocessor 102 and grouping chip 103.CPU101 is responsible for With the normal work of control whole system, grouping chip 103 is responsible for the forwarding or routing of data packet, specifically, business datum After packet enters grouping chip, grouped chip is forwarded processing, is forwarded to corresponding exit port.Coprocessor 102 is used for Some protocol processes work of CPU is shared, or for the upgrading extension of function, coprocessor 102 can (scene can compile by FPGA Journey gate array, Field-Programmable Gate Array) it realizes.

Between CPU and grouping chip, it can realize that data are handed over by data channel respectively between coprocessor and grouping chip It changes, control data bag enters after grouping chip and enters CPU progress protocol processes by the data channel between CPU.CPU can lead to Cross control channel control coprocessor and grouping chip operation, coprocessor and grouping chip can respectively by event channel to CPU101 sends event request.Wherein, carrying control information in control data bag, it is different from business data packet, it is to pass through grouping Chip is transmitted to CPU, may include protocol data packet and management data packet.Protocol data packet, can according to the difference of protocol type Realize different functions, it may include ARP (address resolution protocol, Address Resolution Protocol) message, to root Physical address is obtained according to IP address, for example, can also be OSPF (ospf, Open Shortest Path First) message generates shortest path tree for establishing link state database.Management data packet can realize different management work( It can, it may include SNMP (Simple Network Management Protocol, Simple Network Management Protocol) message, Neng Gouguan The network equipment is managed, finds and solve the growth of network problem and planning network in time, can be TelNet (long-range for another example Terminal protocol, Telecommunications Network) message, it can be achieved that on the local computer control distance host work Make.

In the embodiment of the present invention, in order to realize the control to cpu busy percentage, in equipment running process, it can be worked as according to CPU Preceding utilization rate, using inhibiting data packet to tie up control data bag, to be carried out to the transmission rate of control data bag Control, and then realize the purpose controlled cpu busy percentage.Wherein, in the embodiment of the present invention, the transmission speed of control data bag Rate refers to the rate that control data bag is sent to CPU.

Wherein, the data packet for inhibiting data packet as a kind of specific type defined in the embodiment of the present invention, inhibits number According to packet can be generated and sent by coprocessor to grouping chip, grouping chip processing complete inhibit data packet after abandoned or It is sent to coprocessor, the inhibition data packet discarding that will be returned from grouping chip by coprocessor.Inhibit the priority of data packet Higher than the priority of control data bag, to realize the purpose tied up to control data bag.

Embodiment one

As shown in Fig. 2, a kind of cpu busy percentage control flow schematic diagram provided in an embodiment of the present invention, the flow can assist Processor side executes.

Step 201, the utilization rate of CPU is detected.

Step 202, judge whether the utilization rate of CPU is greater than or equal to first threshold.

Wherein, first threshold is used for weighing the degree of the utilization rate of CPU, if the utilization of the CPU detected in step 201 Rate is greater than or equal to the threshold value, then shows that the utilization rate of current CPU is higher, needs the quantity of the control data bag to entering CPU It is controlled.The value of first threshold can be according to the performance of CPU or equal many factors be set as needed, for example, this One threshold value can value be 80%.

Therefore when the utilization rate of CPU is greater than or equal to first threshold, step 203 is forwarded, step 201 is otherwise gone to, after The utilization rate of detection CPU is held in continuation of insurance.

Step 203, judge that the first buffer queue into grouping chip is sent and inhibit whether the rate of data packet is less than the The minimum guaranteed rate of one buffer queue.

The first buffer queue in chip is grouped for control data bag, inhibition data packet in caching system.First caching There are one the limitations of minimum guaranteed rate for queue, i.e. the data packet number forwarded in the first buffer queue unit interval is up to the The minimum guaranteed rate value of one buffer queue.

After control data bag is sent to the first buffer queue in grouping chip, CPU is forwarded to by grouping chip, by CPU does corresponding processing according to the protocol contents that control data bag carries；Data packet is inhibited to be sent to grouping by coprocessor The first buffer queue in chip, is then forwarded to coprocessor by grouping chip, is abandoned by protocol processor, or directly turns It is sent to and abandons port, data packet discarding will be inhibited by abandoning port.

In the first buffer queue, the priority of data packet is inhibited to be higher than the priority of control data bag, protocol packet core The first buffer queue in piece according to priority data packet in routing forwarding buffer queue.

Therefore, when according to priority orders, the inhibition data packet that the first buffer queue can be in priority processing queue, and first The rate of buffer queue forwarding data packet is up to the minimum guaranteed rate of the first buffer queue, i.e., the first caching in the unit interval Queue forwards the quantity maximum of data packet to be equal to minimum guaranteed rate value, therefore the inhibition data packet in the first buffer queue is got over More, control data bag is processed fewer, and then the agreement school bag for entering CPU in the unit interval will be fewer, therefore CPU profits It will be reduced with rate.

It can be seen that by implementation above mode, inhibit data when first buffer queue of the coprocessor into grouping chip is sent Bao Shi can reduce cpu busy percentage, but be minimum guaranteed rate since the first buffer queue forwards the rate-limit of data packet, because This sends to the first buffer queue before inhibiting data packet, first has to judge that the first buffer queue into grouping chip sends suppression Whether the rate of data packet processed is less than the minimum guaranteed rate of the first buffer queue, if so, step 204 is gone to, if it is not, then turning To step 201, continue the detection for keeping cpu busy percentage.

Step 204, the transmission rate for being sent to the first buffer queue and inhibiting data packet is improved.

In step 203, if judging, the first buffer queue transmission into grouping chip inhibits the rate of data packet to be less than The minimum guaranteed rate of first buffer queue shows that current first buffer queue also not up to forwards the upper limit of data packet, because This can also continue to improve the rate for sending to the first buffer queue and inhibiting data packet, further disinthibite in the first buffer queue Control data bag transmission rate, cpu busy percentage can be further decreased.

Correspondingly, referring to Fig. 3, the embodiment of the present invention also provides a kind of cpu busy percentage control device, including：

Probe unit 301, the utilization rate for detecting central processor CPU；

Judging unit 302 and judges to grouping for judging whether the utilization rate of CPU is greater than or equal to first threshold The first buffer queue in chip sends the most minimum living for inhibiting the transmission rate of data packet whether to be less than first buffer queue Demonstrate,prove rate, wherein for first buffer queue for caching all control data bags for being sent to the CPU, described first is slow The inhibition data packet deposited in queue is dropped after going out team from the buffer queue；

Inhibit unit 303, for being greater than or equal to first threshold, and first into grouping chip when the utilization rate of CPU Buffer queue sends the minimum guaranteed rate for inhibiting the transmission rate of data packet to be less than first buffer queue, then to described the One buffer queue, which is sent, inhibits data packet；Wherein, the priority of the inhibition data packet in first buffer queue is higher than described The priority of control data bag in first buffer queue.

With reference to the cpu busy percentage control system framework in the cpu busy percentage control device and Fig. 1 in Fig. 3, come detailed Cpu busy percentage control method provided in an embodiment of the present invention is described.Referring to Fig. 4, for a kind of CPU profits provided in an embodiment of the present invention With rate control device figure.There are probe unit 301, judging unit 302 and inhibition unit 303 in coprocessor 102 respectively；Grouping There is the first buffer queue 401 in chip 103.

First buffer queue 401, for caching other lists in the inhibition data packet and system that inhibit unit 303 to send The control data bag that member is sent, wherein inhibit data packet to be forwarded to and inhibit unit 303 or directly abandon to inhibit data Packet, control data bag are forwarded to CPU, wherein the priority of the inhibition data packet in the first buffer queue is higher than control data Packet, according to priority sequence forwards data packet to the first buffer queue respectively.

Found out by the above cpu busy percentage control device, the first buffer queue into grouping chip is improved when inhibiting unit When transmission rate, due to inhibiting packet priority to be higher than control data bag in the first buffer queue, unit is inhibited to send It can go to tie up control data bag to the inhibition data packet in the first buffer queue, thus reduce the first buffer queue and be forwarded to The quantity of the control data bag of CPU, to reducing the utilization rate of CPU, further, when due to inhibiting data packet to tie up, When the transmission rate of control data bag in first buffer queue is zero, the utilization rate of CPU can be farthest reduced.

The function of each unit in the step 201 in Fig. 2~204 and above-mentioned apparatus is done in detail with reference to Fig. 4 Description.

For step 202, judge whether the utilization rate of CPU is greater than or equal to first threshold, it can be by sentencing in coprocessor Unit 302 break to execute.Judging unit 302 receives the cpu busy percentage detected that probe unit is sent, which is utilized Rate is compared with first threshold, if the cpu busy percentage is greater than or equal to first threshold, illustrates that CPU current utilizations compare It is high, it is therefore desirable to take measures to reduce cpu busy percentage.

For step 203, judges that the first buffer queue into grouping chip is sent and inhibit the rate of data packet whether small In the minimum guaranteed rate of the first buffer queue, can be executed by judging unit 302.Judging unit 302 will currently inhibit unit 303 transmission rates for sending inhibition data packet are compared with the minimum guaranteed rate that the first buffer queue allows, if inhibiting single Member 303, which is sent, inhibits the transmission rate of data packet to be greater than or equal to the minimum guaranteed rate of the first buffer queue, then shows that first is slow It has been all to inhibit data packet to deposit in queue, is not necessarily to improve the transmission rate for inhibiting unit transmission to inhibit data packet at this time, The detection of holding cpu busy percentage need to only be continued；The transmission rate of data packet is inhibited to be less than first if unit 303 is inhibited to send The minimum guaranteed rate of buffer queue then shows still also have control data bag being forwarded in the first buffer queue, then can be by pressing down Unit 303 processed improves the transmission rate for inhibiting data packet, increases the inhibition data packet number in the first buffer queue, to reduce The quantity of control data bag in first buffer queue so that the quantity that control data bag is forwarded to CPU by the first buffer queue subtracts It is few, thereby reduce the utilization rate of CPU.

For step 204, can be executed by inhibition unit 303.Inhibit unit 303 according to the judging result of judging unit 302 The transmission rate for inhibiting data packet is improved to the first buffer queue to execute.In order not to the width for making cpu busy percentage rise or fall Big, the effectively smooth variation in a certain range of control cpu busy percentage is spent, when raising inhibits data package transmission velocity, often Secondary improved according to setting step-length sends the transmission rate for inhibiting data packet to first buffer queue, and according to the hair after raising Transmission rate is sent to first buffer queue inhibits data packet, specifically includes following steps：

Step A：Detect the utilization rate of CPU；

Step B：If the utilization rate of the CPU is less than first threshold, it is transferred to step C；

Step C：Judge to send whether the transmission rate for inhibiting data packet is more than described first to first buffer queue Otherwise the minimum guaranteed rate of buffer queue is transferred to step D if so, being transferred to step A；

Step D：It is improved according to setting step-length and sends the transmission rate for inhibiting data packet to first buffer queue, and turned Enter step A.

Correspondingly, inhibit unit 303 when sending inhibition data packet to the first buffer queue, carried every time according to setting step-length Height sends the transmission rate for inhibiting data packet to first buffer queue, and according to the transmission rate after raising to described first Buffer queue, which is sent, inhibits data packet, specifically includes following steps：

Step A：Detect the utilization rate of CPU；

The step-length of setting can send that the quantity of data packet is inhibited to increase K in the unit interval, and the quantity of K can be according to reality Depending on the application of border, in this regard, the embodiment of the present invention is not specifically limited this.

In addition, according to the cpu busy percentage control method of step 201~204, can when cpu busy percentage is relatively high, to First buffer queue, which is sent, inhibits data packet, to realize the purpose for reducing cpu busy percentage.But if cpu busy percentage by Control is within the scope of one is smaller, for example cpu busy percentage is at this time already less than second threshold, the second threshold be less than or Equal to first threshold, at this moment, cpu busy percentage can be reduced, specifically, if in step 202, judging to show that cpu busy percentage is small After first threshold, further judge whether cpu busy percentage is less than second threshold, if the utilization rate of CPU is less than second threshold, Then reduce the transmission rate for being sent to the first buffer queue and inhibiting data packet.Above-mentioned flow specifically includes following steps：

Step A：Detect the utilization rate of CPU；

Step B：If the utilization rate of CPU is less than the second threshold, it is transferred to step C；

Step C：Judge to send whether the transmission rate for inhibiting data packet is more than zero to the first buffer queue, if so, turning Enter step D, is otherwise transferred to A；

Step D：It is reduced according to setting step-length and sends the transmission rate for inhibiting data packet to the first buffer queue, and be transferred to step Rapid A.

Correspondingly, the judging unit 302 of cpu busy percentage control device can determine whether cpu busy percentage is less than second threshold； Inhibit unit 303 that can also reduce to the first buffer queue when the utilization rate of CPU is less than second threshold and send inhibition data packet Transmission rate specifically includes following steps：

Step A：Detect the utilization rate of CPU；

The above embodiment of the present invention, the mode that the utilization rate of CPU is detected can there are many, one kind is given below Preferred realization method.

Preferably, the utilization rate of CPU can measure by the following method in the embodiment of the present invention：Detection number is sent to CPU According to packet, and receive the probe data packet of CPU returns；According to the difference of the sending time of probe data packet and receiving time, obtain Go out residence time of the probe data packet in the CPU；It is pre-set according to residence time inquiry of the probe data packet in CPU Residence time and cpu busy percentage correspondence, obtain the utilization rate of CPU.

Specifically, cpu busy percentage is detected, is divided into two stages of starting stage and normal detection phase, mainly at association It manages device and CPU collaborations is completed, grouping chip only serves the effect of forwarding data packet.Starting stage, CPU shieldings connect except coprocessor The ability of the transceiving data packet of other ports except inbound port, makes the live load of CPU in reduced levels；Normal detection rank Section, CPU normal works, handles all types of tasks, at this point, priority of the detection mission in CPU in all tasks is minimum, this It is to ensure other tasks in CPU by priority processing so that residence time of the probe data packet in CPU is by other tasks The occupancy of CPU is counted, observes the execution time of every other task by the residence time of probe data packet with this.

Fig. 5 illustratively shows the schematic diagram of detection cpu busy percentage starting stage of the embodiment of the present invention.Coprocessor is responsible for Probe data packet is sent to CPU, P probe data packet is continuously transmitted to CPU such as in 1S, wraps and stamp in each detection data The sending time of each data packet is stabbed.There are detection missions in CPU, and after being connected to probe data packet, current cpu busy percentage is put Enter in probe data packet, P probe data packet can obtain the cpu busy percentage at P time point, then carry out probe data packet Forwarding sends back coprocessor by being grouped chip.After coprocessor receives P probe data packet, in each detection data It wraps and stamps receiving time stamp respectively, parse probe data packet, the receiving time stamp of each probe data packet subtracts corresponding hair Timestamp is sent to obtain residence time of the probe data packet in CPU, as a result, further according to the cpu busy percentage in probe data packet, The correspondence t of cpu busy percentage and residence time is obtained, as shown in Figure 6.Such as, when cpu busy percentage is 10%, when being resident Between be 10 μ s, when cpu busy percentage be 40% when, residence time be 40 μ s, when cpu busy percentage be 60% when, residence time be 60 μ Thus s obtains the empirical relation between cpu busy percentage and residence time TWherein, M is cpu busy percentage, and T is Residence time of the probe data packet in CPU, 100 μ s are the coefficients obtained the detection cpu busy percentage starting stage..Thus experience Relation formula, when knowing residence time T, you can obtain cpu busy percentage M, or, if it is desired to the utilization rate M of CPU is no more than Threshold value x (for example x is 70%), can find out residence time T no more than tx (i.e. 70 μ s).

The normal detection phase, coprocessor sends a probe data packet with the fixed cycle (such as 1s) to CPU, and is detecting Sending time stamp is stamped in data packet, and after CPU is connected to probe data packet, probe data packet such as is put at the pending team in order In row, the priority of wherein detection mission is minimum.Because the residence time of probe data packet need to be by other tasks to the occupancy of CPU It counts, if the priority of detection mission is higher, then probe data packet can not just pass through residence time by priority processing Observe the whole busy extent of CPU.This stage, CPU are not required to squeeze into current cpu busy percentage in probe data packet, only need Probe data packet is beamed back into coprocessor, prevents probe data packet from increasing extra work to CPU, aggravates the busy of CPU Degree.Coprocessor stamps receiving time stamp again after receiving probe data packet, is stabbed by receiving time stamp and sending time The residence time of probe data packet is obtained, the correspondence t of the residence time and cpu busy percentage that are obtained further according to the starting stage, Obtain cpu busy percentage.For example, according to the correspondence t of previous example, if residence time is 50 μ s, cpu busy percentage is 50%.In addition, coprocessor need to preset a maximum residence time, such as 200 μ s.Because if cpu busy percentage is very high, visit Measured data packet is just returned less than coprocessor for a long time, or can not return to coprocessor, when more than this maximum residence time Later, coprocessor is considered as this time detecting cpu busy percentage being 100%, and starts to start next detection.

During detecting cpu busy percentage, transmission of the probe data packet between CPU and coprocessor need to pass through grouping Chip, priority of the probe data packet in being grouped chip be highest, this be in order to prevent probe data packet in being grouped chip It stays the excessive time because of the interference of other data packets or even is grouped chip and abandon, to which coprocessor cannot be detected accurately Residence time of the data packet in CPU.And if probe data packet is grouped chip discarding, in coprocessor, exactly visit Measured data packet is infinitely resident in CPU, and the utilization rate for being mistakenly considered CPU reaches 100%.

With reference to Fig. 7, the cpu busy percentage control method that the embodiment of the present invention provides is explained in detail.Fig. 7 is provided A kind of cpu busy percentage control flow chart provided in an embodiment of the present invention.

Wherein, the cpu busy percentage that probe unit detects indicates that preset first threshold is M1, second threshold with M For M2, data package transmission velocity is inhibited to be indicated with V, the minimum guaranteed rate of the first buffer queue is Vmax, inhibits unit 303 every It is secondary to increase or decrease transmission rate by setting step-length.Wherein, M1 illustrates that a higher cpu busy percentage, M2 illustrate one Lower cpu busy percentage then improves to the first buffer queue when CPU current utilizations are higher than M1 and sends inhibition data packet Transmission rate reduces cpu busy percentage, when CPU current utilizations are less than M2, then reduce to send to first buffer queue and inhibits The transmission rate of data packet improves cpu busy percentage.

Step 701, data package transmission velocity is inhibited to be initialized as V=0.

In the starting stage, inhibit data packet due to not sent to the first buffer queue, it will be to the first buffer queue It sends and the transmission rate of data packet is inhibited to be initialized as V=0.

Step 702, cpu busy percentage is detected.

The utilization rate M of CPU is detected using probe unit 301.When CPU is busier, if probe unit is sent to CPU's Probe data packet without returning to probe unit, then sets the cpu busy percentage that this is detected to before the deadline 100%, the defined time, which can be 100 μ s or 200 μ s, occurrence, to be determined on a case-by-case basis.

Step 703, judge whether cpu busy percentage M is greater than or equal to M1.

Judge whether cpu busy percentage M is greater than or equal to M1 using judging unit 302, if cpu busy percentage is more than M1, shows Current cpu busy percentage is relatively high, then goes to step 704, otherwise go to step 706.

Step 704, judge to send whether the transmission rate V for inhibiting data packet is greater than or equal to first to the first buffer queue The minimum guaranteed rate of buffer queue.

In the step, judging unit 302 judges that unit 303 is inhibited to send the transmission for inhibiting data packet to the first buffer queue Whether rate V is greater than or equal to the minimum guaranteed rate of the first buffer queue, if so, showing to inhibit unit 303 slow to first Deposit queue transmission inhibit data packet transmission rate have been over the first buffer queue permission maximum value, then no longer need to after It is continuous to improve transmission rate, therefore step 702 is gone to, continue to keep detection cpu busy percentage；Otherwise, show to can also continue to carry Height sends the transmission rate for inhibiting data packet to the first buffer queue, therefore goes to step 705.

Step 705, the transmission rate of data packet will be inhibited to be improved by setting step-length when preceding sent to the first buffer queue.

To ensure that cpu busy percentage is smoothly improved or reduced, inhibits unit 303 to be sent to the first buffer queue and inhibit number It should not be too large according to the rate variation of packet, to inhibiting the transmission rate of data packet to may be configured as increasing in the unit interval in the present embodiment One inhibition data packet transmission, in practical applications, can as the case may be depending on.

Step 706, judge whether cpu busy percentage M is greater than or equal to M2.

In the step, judging unit 302 judges whether cpu busy percentage M is greater than or equal to M2, if so, showing current CPU Utilization rate lowers completely not yet, then goes to step 702, continues that detection cpu busy percentage is kept otherwise then to go to step 707。

Step 707, judge whether current inhibition data package transmission velocity is more than zero.

In step 706, judgement show that current cpu busy percentage is less than or equal to second threshold, it is therefore desirable to improve CPU Utilization rate, the method for improving cpu busy percentage are to reduce that unit 303 is inhibited to send the transmission for inhibiting data packet to the first buffer queue Rate, thus the first buffer queue can be allow to forward more control data bags to CPU.Reducing the suppression for inhibiting unit Before data package transmission velocity processed, it is necessary first to judge, it is current to inhibit whether data package transmission velocity is more than zero, if so, turning To step 708, step 702 is otherwise gone to.

Step 708, the transmission rate of data packet will be inhibited to inhibit within the unit interval when preceding sent to the first buffer queue The quantity forwarded of data packet reduces one.

By above description as can be seen that in the embodiment of the present invention, the speed that control data bag enters CPU is entered by control Rate come achieve the effect that reduce cpu busy percentage, wherein first detect central processor CPU utilization rate, if the utilization rate of CPU More than or equal to first threshold, then judge that the transmission rate that the first buffer queue into grouping chip sends inhibition data packet is The no minimum guaranteed rate for being less than the first buffer queue inhibits data packet if so, being sent to the first buffer queue, wherein the For caching all control data bags for being sent to the CPU, the inhibition data packet in the first buffer queue exists one buffer queue It is dropped after going out team from the buffer queue and the priority of inhibition data packet in the first buffer queue is higher than the first caching The priority of control data bag in queue, therefore improve and inhibit data packet transmission that can reduce by first into the first buffer queue The transmission rate of control data bag in buffer queue, to realize the rate by control into the control data bag of CPU To control cpu busy percentage.

In above-mentioned steps 704, if the judgement of judging unit 302 show that inhibiting unit 303 to be sent to the first buffer queue presses down The transmission rate V of data packet processed is less than the minimum guaranteed rate Vmax of the first buffer queue, then inhibits unit to press down within the unit interval The quantity forwarded of data packet processed increases by one, wherein the control number in inhibition data package transmission velocity V and the first buffer queue When guaranteed rate minimum less than the first buffer queue according to the sum of packet sending speed V1, show the inhibition data in the first buffer queue Packet and control data bag do not take the first buffer queue, therefore, press down when inhibiting unit to improve to send to the first buffer queue When the transmission rate of data packet processed, the control data bag in the first buffer queue can not be inhibited in the incipient stage, directly Inhibit the transmission rate V of unit to be increased to so that when V+V1=Vmax to improving, next improves the transmission rate of inhibition unit When, can just inhibition be generated to the control data bag transmission rate in the first buffer queue.

Embodiment two

In the embodiment of the present invention two, number can be inhibited on the basis of embodiment one to determine in the first buffer queue Whether it is equal to the minimum guaranteed rate of the first buffer queue according to the sum of packet sending speed and control data bag transmission rate, it can be by assisting Processor persistently sends measurement data packet into the first buffer queue, and measurement data packet is sent to the first caching in grouping chip After queue, coprocessor is forwarded to by grouping chip, the transmission rate of the measurement data packet is equal to the first buffer queue most Low guaranteed rate, and priority of the measurement data packet in the first buffer queue is minimum, i.e. by excellent in the first buffer queue First grade is followed successively by from high to low inhibits data packet, control data bag, measurement data packet.

In the starting stage, when the first buffer queue is empty, measurement data packet is persistently sent into the first buffer queue, is sent The transmission rate of measurement data packet is equal to the minimum guaranteed rate of the first buffer queue, therefore in the first buffer queue at this time all It is measurement data packet, when there is control data bag to reach the first buffer queue, control data bag is preferential in the first buffer queue Grade is higher than measurement data packet, therefore the raw inhibition that can partly will contract for fixed output quotas to measurement data, inhibits data packet arrival first to cache when having When queue, due to inhibiting packet priority highest, measurement data packet can be inhibited first, when measurement data coating is suppressed to When zero, data packet is inhibited to enter the first buffer queue if also having, can further disinthibite control data bag at this time.

Therefore, coprocessor can be according to the measurement data packet quantity and reception for being sent to the first buffer queue in the unit interval The quantity of the measurement data packet arrived, can obtain the transmission rate of the measurement data packet in the first buffer queue, and then learn first Inhibit whether the sum of data package transmission velocity and control data bag transmission rate are equal to the first buffer queue in buffer queue Minimum guaranteed rate, because of the transmission rate of the transmission rate V2 of measurement data packet in the first buffer queue, control data bag The V1 and transmission rate V for inhibiting data packet, the sum of three are consistently equal to the minimum guaranteed rate Vmax, i.e. V2 of the first buffer queue + V1+V=Vmax works as V2>When 0, then V1+V is certainly less than Vmax.

Therefore, cpu busy percentage is being detected more than or equal to after first threshold, can be gone to determine how reduction by following methods The utilization rate of CPU, including：

It is returned according to the quantity for the measurement data packet for being sent to first buffer queue and from first buffer queue The quantity of the measurement data packet returned, determines the quantity of the measurement data packet in first buffer queue；Wherein, described first is slow The priority of the measurement data packet in queue is deposited less than the priority of the control data bag in the buffer queue, the measurement data Packet is sent to first buffer queue by coprocessor and is forwarded to the coprocessor, the measurement data after going out team The transmission rate of packet is the minimum guaranteed rate of first buffer queue；

If the quantity of the measurement data packet in first buffer queue is more than zero, it is determined that first buffer queue The transmission rate for inhibiting data packet is sent, and according to the transmission rate for the inhibition data packet determined to first buffer queue It sends and inhibits data packet, wherein the transmission rate determined, which was equal in the unit interval, is sent to first buffer queue The difference of the quantity of measurement data packet and the quantity of the measurement data packet returned from first buffer queue；Or

If the quantity of the measurement data packet in first buffer queue is equal to zero, improved to described according to setting step-length First buffer queue sends the transmission rate for inhibiting data packet, and according to the transmission rate after raising to first buffer queue It sends and inhibits data packet.

With reference to Fig. 8, the cpu busy percentage control method that inventive embodiments two provide is described in detail.

Referring to Fig. 8, for another cpu busy percentage control flow chart provided in an embodiment of the present invention.Wherein, probe unit is visited The cpu busy percentage measured indicates that preset first threshold is M1, second threshold M2, inhibits data package transmission velocity with M It is indicated with V, the minimum guaranteed rate of the first buffer queue is Vmax, and unit 303 is inhibited to inhibit data packet within the unit interval Quantity forwarded increases by one.Wherein, first threshold illustrates a higher cpu busy percentage, second threshold illustrate one compared with Low cpu busy percentage then needs to send to raising to the first buffer queue and press down when CPU current utilizations are higher than first threshold The transmission rate of data packet processed reduces cpu busy percentage, when CPU current utilizations are less than second threshold, then needs to first Buffer queue, which reduces to send, inhibits the transmission rate of data packet to improve cpu busy percentage.

For step 801, step 802 step 701 a kind of with embodiment, step 702 is similar and step 808~810 It is similar with step 706~708 of embodiment one, it repeats no more again.With reference to Figure 10, to provided by Embodiment 2 of the present invention Step 803~807 of cpu busy percentage control method elaborate.

Step 803, judge whether cpu busy percentage M is greater than or equal to first threshold M1.

Judging unit 302 judges whether cpu busy percentage M is greater than or equal to first threshold, if cpu busy percentage is more than the first threshold Value, shows that current cpu busy percentage is relatively high, then goes to step 804, otherwise go to step 808.

Step 804, judge whether the transmission rate of the measurement data packet in the first buffer queue is more than zero.

Judging unit 302 receives the measurement data packet in the first buffer queue that determination subelement inhibits unit to measure Transmission rate V2, judges whether V2 is more than 0, if more than 0, then goes to step 805, otherwise goes to step 806.

Step 805, being arranged to send to the first buffer queue inhibits the transmission rate of data packet to be equal in the first buffer queue Measurement data packet transmission rate.

When measuring the measurement data packet sending speed in the first buffer queue more than zero, then it is arranged to the first caching team Row send the transmission rate for inhibiting the transmission rate of data packet to be equal to the measurement data packet in the first buffer queue, in this way can be first The measurement data packet of the first buffer queue is quickly first suppressed to zero, control data bag of then disinthibiting again is conducive to improve drop The efficiency of low cpu busy percentage.

Step 806, judge whether the transmission rate of the inhibition data packet in the first buffer queue is more than the first buffer queue Minimum guaranteed rate.

When the measurement data packet in the first buffer queue is zero, improves inhibit data packet into the first buffer queue at this time Transmission rate, then can inhibit the transmission rate of control data bag, to reduce the utilization rate of CPU.Before this, pass through step Rapid 806 judge to send whether the transmission rate V for inhibiting data packet is greater than or equal to the first buffer queue to the first buffer queue Minimum guaranteed rate, if so, showing that transmission of the subelement to the first buffer queue is inhibited to inhibit the transmission rate of data packet Maximum value through allowing more than the first buffer queue is then not necessarily to be further continued for improving transmission rate, therefore goes to step 802, Continue to keep detection cpu busy percentage；Otherwise, show to can also continue to improve the hair for sending to the first buffer queue and inhibiting data packet Transmission rate, therefore go to step 807.

It step 807, will be when the preceding hair for being sent to the first buffer queue and data packet being inhibited to inhibit data packet within the unit interval Quantity is sent to increase by one.

Correspondingly, it is a kind of cpu busy percentage control device provided in an embodiment of the present invention, including to place an order referring to Fig. 9 Member：

Probe unit 301, judging unit 302 inhibit unit 303；It further includes determination subelement wherein to inhibit unit 303 904 and inhibit subelement 905.

Determination subelement 904, for according to be sent to first buffer queue measurement data packet quantity and from The quantity for the measurement data packet that first buffer queue returns, determines the number of the measurement data packet in first buffer queue Amount；Wherein, the priority of the measurement data packet in first buffer queue is less than the control data bag in the buffer queue Priority, the measurement data packet are sent to first buffer queue by coprocessor and are forwarded to the association after going out team Processor, the transmission rate of the measurement data packet are the minimum guaranteed rate of first buffer queue；

Inhibit subelement 905, when the quantity for the measurement data packet in first buffer queue is more than zero, will inhibit The transmission rate of data packet is set as being sent to the measurement data packet quantity of first buffer queue and reception in the unit interval The difference of the quantity of the measurement data packet for first buffer queue forwarding arrived, and according to the transmission for the inhibition data packet determined Rate is sent to first buffer queue inhibits data packet；Wherein, first caching team is sent in the unit interval The measurement data packet quantity of row is identical as the minimum guaranteed rate of the first buffer queue, data in first buffer queue The priority of packet is followed successively by inhibition data packet, control data bag, measurement data packet from high to low；Or

When the quantity of measurement data packet is equal to zero in first buffer queue, improved to described the according to setting step-length One buffer queue sends the transmission rate for inhibiting data packet, and is sent out to first buffer queue according to the transmission rate after raising Send inhibition data packet.

Ginseng gives Figure 10 to a kind of installation drawing of detection cpu busy percentage, on the basis of Fig. 4, in inhibiting unit It also adds determination subelement 904 and inhibits subelement 905, the measuring unit is used to measure the survey in the first buffer queue Whether the transmission rate for measuring data packet is more than zero, if more than zero, then shows that the inhibition data packet in the first buffer queue sends speed Rate is less than the minimum guaranteed rate of the first buffer queue with the sum of the transmission rate of control data bag in the first buffer queue.

In the embodiment of the present invention, the rate of CPU is entered to reach reduction cpu busy percentage into control data bag by control Effect, wherein first detect central processor CPU utilization rate, if the utilization rate of CPU be greater than or equal to first threshold, Judge whether the transmission rate of the measurement data report in the first buffer queue is more than zero, it, then will be to the first caching team if more than zero Row send the transmission rate for inhibiting the transmission rate of data packet to be set as the measurement data packet in the first buffer queue, if being equal to Zero, then judge that the first buffer queue into grouping chip is sent and inhibits whether the transmission rate of data packet is less than the first caching team The minimum guaranteed rate of row inhibits data packet, wherein the first buffer queue is for delaying if so, being sent to the first buffer queue All control data bags for being sent to the CPU are deposited, the inhibition data packet in the first buffer queue goes out from the buffer queue It is dropped after team and the priority of inhibition data packet in the first buffer queue is higher than the control data in the first buffer queue The priority of packet, therefore improve and inhibit data packet to send the control that can be reduced in the first buffer queue into the first buffer queue The transmission rate of data packet controls cpu busy percentage to realize by controlling the rate into the control data bag of CPU.

Embodiment three

In another embodiment, in being grouped chip, the control data bag of each classification enter after grouping chip can first into Enter corresponding control data bag buffer queue and waits for grouping chip processing.One control data bag buffer queue is used for caching same The control data bag of classification.Control data bag buffer queue can be the buffer queue of priority mechanism, i.e. the high number of priority Go out team according to the data packet for wrapping low prior to priority.

Further, the control data bag that can be also directed to each classification defines CIR (Committed Information Rate, ensures information rate or is committed information rate), wherein a kind of value of the CIR of the control data bag of classification does not surpass Cross the acceptable maximum rates of CPU.The CIR of different classes of control data bag can be set as needed, for example, according to each The CPU holding times of the agreement of classification determine the CIR of category control data bag, it is preferable that the high control data bag of priority CIR be more than the low control data bag of priority CIR.

Based on structure shown in FIG. 1, cpu busy percentage control program provided in an embodiment of the present invention mainly by coprocessor simultaneously Collaboration is grouped chip to realize.

Figure 11 shows that the schematic diagram of cpu busy percentage control flow provided in an embodiment of the present invention, the flow can be in agreements It realizes processor side.As shown, the flow may include：

Step 1101：Detect the utilization rate of CPU；

Step 1102：Judge whether the utilization rate of CPU is greater than or equal to first threshold, if so, being transferred to step 1203；It is no Then, it is transferred to step 1201；

Wherein, first threshold is used for weighing the degree of the utilization rate of CPU, if the profit of the CPU detected in step 1101 It is greater than or equal to the threshold value with rate, then shows that the utilization rate of current CPU is higher, needs the number of the control data bag to entering CPU Amount is controlled.The value of first threshold can be set according to the performance or equal many factors as needed of CPU, such as should First threshold can value be 80%.

Step 1103：Enlargement discharge is needed to press down according to the priority determination of the control data bag buffer queue in grouping chip The control data bag buffer queue of system, and improve to the control data bag buffer queue transmission for needing enlargement discharge to inhibit and inhibit number According to the rate of packet.

Wherein, grouping chip includes N number of control data bag buffer queue, and N is the integer more than 1, a control data The priority of inhibition data packet in packet buffer queue is higher than the preferential of the control data bag in the control data bag buffer queue Grade, the inhibition data packet in a control data bag buffer queue is lost after going out team from the control data bag buffer queue at place It abandons, the control data bag in a control data bag buffer queue is forwarded to CPU.

Specifically, in step 1103, can according to the priority sequence from low to high of control data bag, determine need plus The control data bag buffer queue that big flow inhibits.In this way, can preferentially to the transmission rate of the control data bag of low priority into Row inhibits, and to while reducing cpu busy percentage, ensure the transmission of the control data bag of high priority as possible, and then ensures Important affairs priority processing.

Further, can according to control data bag priority from low to high, the control data bag minimum from priority is slow It deposits queue to start, increases the rate for sending and inhibiting data packet, until the transmission rate of the minimum control data bag of priority is pressed down It is made as zero.If cpu busy percentage is still greater than first threshold at this time, increase to the low control data bag buffer queue hair of preferential level The rate for inhibiting data packet is sent, until the transmission rate of the low control data bag of preferential level is suppressed to zero.And so on, directly The transmission rate of the control data bag of highest priority is extremely suppressed to zero.

Preferably, in order to ensure processing of the CPU to affairs, the process of inhibition of control data bag can be divided in step 1103 For two processing stages：First processing stage and second processing stage.First processing stage main purpose is to be directed to transmission rate It more than the control data bag of minimum guaranteed rate, is sent to rate and is reduced to the minimum guaranteed rate, complete the first processing On the basis of stage, if the utilization rate of CPU still without being reduced to expected degree, for example is less than first threshold, then enter second Processing stage.The main purpose of second processing stage is to be equal to the control data bag of minimum guaranteed rate for transmission rate, will Its transmission rate is reduced to zero.

In the first processing stage of the process of inhibition of control data bag, control data bag transmission rate can be directed to and be more than most The control data bag buffer queue of low guaranteed rate is cached according to the sequence of control data bag priority from low to high to these Queue, which is sent, inhibits data packet, and the transmission rate of the control data bag in these buffer queues is made to be reduced to minimum guaranteed rate, And when the utilization rate of CPU is reduced to expected degree (such as first threshold) or is more than for all control data bag transmission rates When the control data bag buffer queue of minimum guaranteed rate handles completion, terminate first processing stage.

Figure 12 schematically illustrates the first processing stage and the second processing of a kind of process of inhibition of control data bag The flow chart in stage.

For convenience, the control data bag priority that is cached is sent in buffer queue from low according to control data bag To high sequence, N number of control data bag buffer queue is described as the first buffer queue to N buffer queues.

As shown in figure 12, first processing stage of control data bag process of inhibition may include following step in step 1103 Suddenly：

Step 1201：I is set as 1；

Step 1202：Judge whether the transmission rate of the control data bag in the i-th buffer queue is higher than the control data bag Minimum guaranteed rate be otherwise transferred to step 1205 if so, being transferred to step 1203；

Step 1203：It is sent to the i-th buffer queue and inhibits data packet, the speed for inhibiting data packet is sent to the i-th buffer queue The transmission rate that rate is equal to the control data bag in the i-th buffer queue subtracts obtained by the minimum guaranteed rate of the control data bag Difference；

Step 1204：The utilization rate of CPU is detected, if the utilization rate of CPU is greater than or equal to first threshold, is transferred to step 1205, otherwise terminate the flow of the first processing stage of this process of inhibition；

Step 1205：I is incremented by 1；

Step 1206：If i >=1, it is transferred to step 1202, otherwise, terminates the first processing stage of this process of inhibition Flow, into the second processing stage of process of inhibition.

Sequence from low to high according to priority is can be seen that by above-mentioned flow, inhibits low priority to control data first The rate of the control data bag of the low priority is suppressed to the minimum guaranteed rate of the control data bag by the transmission rate of packet, Then the utilization rate of detection CPU continues the hair to the control data bag of higher priority if cpu busy percentage is still higher at this time Transmission rate is inhibited, so repeatedly above step, until all transmission rates to be higher than to the control data of minimum guaranteed rate The transmission rate of packet is suppressed to corresponding minimum guaranteed rate.

After the completion of the first stage of process of inhibition, if the utilization rate of CPU remains above first threshold, continues to execute and inhibited The second stage of journey.

As shown in figure 12, the second processing stage of control data bag process of inhibition may comprise steps of：

Step 1207：I is set as 1；

Step 1208：Increase the rate for being sent to the i-th buffer queue and inhibiting data packet, so that the control in the i-th buffer queue The transmission rate of data packet processed is zero；

Step 1209：The utilization rate of CPU is detected, if the utilization rate of CPU is greater than or equal to first threshold, is transferred to step 1210, otherwise terminate the second processing stage of this process of inhibition, can subsequently continue to detect the utilization rate of CPU, and root Corresponding flow is triggered according to the utilization rate of the CPU detected；

Step 1210：I is incremented by 1；

Step 1211：If i≤N, it is transferred to step 1208, otherwise terminates the second processing stage of this process of inhibition, after It is continuous to continue to detect the utilization rate of CPU, and corresponding flow is triggered according to the utilization rate of the CPU detected.

Further, after the rate of all control data bags being suppressed to zero, the utilization rate of CPU is still greater than the first threshold Value can then send and be used to indicate the high alarm instruction of cpu busy percentage.

It can be seen that by above-mentioned flow when the transmission rate of all control data bags is suppressed to minimum guarantee speed Rate, the utilization rate of CPU is still greater than first threshold, then since the minimum control data bag of priority, by the control of low priority The transmission rate of data packet is down to zero, the utilization rate of CPU is then detected, if cpu busy percentage is pressed still greater than first threshold at this time The transmission rate of the control data bag of higher priority is reduced to zero by the sequence of priority from low to high, until being controlled all The transmission rate of data packet processed is reduced to zero.

By two processing stages of above-mentioned process of inhibition, control data bag rate is suppressed to minimum guarantee speed first Rate, rather than directly fall the complete inhibition of control data bag rate, the impact that is generated to CPU of protocol data-flow is quickly being reduced, While reducing cpu busy percentage, and processing of the CPU to affairs can be ensured as much as possible.

As previously mentioned, after the completion of the second processing stage of process of inhibition, can continue to detect the utilization rate of CPU, And corresponding flow is triggered according to the utilization rate of the CPU detected.For example, when the utilization rate of the CPU detected is relatively low, can trigger Process of expansion is to improve the transmission rate of control data bag.

Specifically, if the utilization rate of CPU is less than second threshold, needs can be determined according to the priority of control data bag The control data bag buffer queue that flow inhibits is reduced, and is reduced to the control data bag buffer queue for needing reduction flow to inhibit Send the rate for inhibiting data packet.Wherein, second threshold is less than or equal to first threshold, and the value of second threshold can be according to CPU Performance or equal many factors are set as needed, such as the second threshold can value be 40%.

By the above method, in the case where second threshold is less than first threshold, the utilization rate of CPU can be controlled second Threshold value is between first threshold so that and the utilization rate of CPU is neither excessively high only low, avoids the excessive adjustment of cpu busy percentage, Also ensure processing control data bag as much as possible.

Preferably, it can determine according to priority from high to low the sequence of control data bag and need to reduce what flow inhibited Control data bag buffer queue.In this way, can as possible be protected preferentially to the transmission rate derepression of the control data bag of high priority The control data bag of card high priority is sent to CPU, to ensure the processing of high priority affairs.

Process of expansion can equally be divided into two processing stages：First processing stage and second processing stage.First processing rank Section main purpose is the sequence according to priority from high to low, and the transmission speed to control data bag is released according to the step-length of setting The inhibition of rate, on the basis of completing for the first processing stage, if the utilization rate of CPI still without being increased to expected degree, such as Second threshold then enters second processing stage；The main purpose of second processing stage is the sequence according to priority from high to low, To a kind of gradual derepression of the control data bag of classification until complete derepression transmission rate inhibition, until CPU's Until utilization rate is higher than second threshold.

Figure 13 schematically illustrates the first processing stage and the second processing of a kind of process of expansion of control data bag The flow chart in stage.

As shown in figure 13, the first processing stage in control data bag process of expansion may comprise steps of：

Step 1301：Set i to N；

Step 1302：Judge whether the transmission rate of the control data bag in the i-th buffer queue is less than the control data bag Minimum guaranteed rate be otherwise transferred to step 1305 if so, being transferred to step 1303；

Step 1303：It is reduced according to setting step-length and sends the rate for inhibiting data packet to the i-th buffer queue, be transferred to step 1304；Wherein, the value of the step-length can be pre-set as needed, if value is smaller, it is smaller to adjust granularity, on the contrary then adjust Whole grain degree is larger.

Step 1304：The utilization rate of CPU is detected, if the utilization rate of CPU is less than or equal to second threshold, is transferred to step 1305, otherwise, terminate the flow of the first processing stage of this process of expansion；

Step 1305：I is successively decreased 1；

Step 1306：If i≤N, it is transferred to step 1302, otherwise, terminates the first processing stage of this process of expansion Flow, into the second processing stage of process of expansion.

Further, in above-mentioned process of expansion, if the utilization rate of detection CPU is higher than second threshold and is less than first threshold, It can then continue to keep currently to inhibit the transmission rate of data packet constant.

Sequence from high to low according to priority is can be seen that by above-mentioned flow, traverses control data bag buffer queue, if The transmission rate of control data bag in the control data bag buffer queue currently traversed is less than minimum guaranteed rate, then reduces The rate for inhibiting data packet is sent to the control data bag buffer queue, to make the control in the control data bag buffer queue The transmission rate of data packet is promoted, and continues to traverse next control data bag buffer queue, until the utilization rate of CPU reaches Stop ergodic process until second threshold.

After the completion of first processing stage of process of expansion, if the utilization rate of CPU is still below second threshold, expansion is continued to execute The second processing stage for the process of opening.

As shown in figure 13, the second processing stage of control data bag process of expansion may comprise steps of：

Step 1307：Set i to N；

Step 1308：Judge to send whether the transmission rate for inhibiting data packet is more than zero to the i-th buffer queue, if so, It is transferred to step 1309, is otherwise transferred to step 1311；

Step 1309：It is reduced according to setting step-length and sends the rate for inhibiting data packet to the i-th buffer queue；

Step 1310：The utilization rate of CPU is detected, if the utilization rate of CPU is less than or equal to second threshold, is transferred to step 1311, otherwise terminate the second processing stage of this process of expansion, can subsequently continue to detect the utilization rate of CPU, and root Corresponding flow is triggered according to the utilization rate of the CPU detected；

Step 1311：I is successively decreased 1；

Step 1312：If i >=1, it is transferred to step 1308, otherwise terminates the second processing stage of this process of expansion, after It is continuous to continue to detect the utilization rate of CPU, and corresponding flow is triggered according to the utilization rate of the CPU detected.

If can be seen that the first processing by process of expansion by the flow of the second processing stage of the above process of expansion After stage, the utilization rate of CPU does not promote second threshold also, then sequence from high to low according to priority, traverses control data bag Buffer queue walks the transmission rate of the inhibition data packet into the control data bag buffer queue currently traversed according to setting Length continuously decreases, and until the utilization rate of CPU reaches second threshold, otherwise, traverses next control data bag buffer queue, and press It is handled according to the same manner, until the utilization rate of CPU reaches second threshold or has traversed all control data bag buffer queues Position.

By two processing stages of above-mentioned process of expansion, data will be controlled first, in accordance with the sequence of priority from high to low Packet rate is promoted, rather than directly by a kind of complete derepression of control data bag rate, to ensure CPU to all types of affairs Processing can be according to the sequence of priority from high to low, by one and further when the utilization rate of CPU is still in reduced levels The transmission rate solution of control data bag after the complete derepression of transmission rate of kind control data bag, then to next priority Except inhibition, to ensure the processing of high priority affairs as far as possible.In this way, in the case where ensureing that the utilization rate of CPU is not excessively high, CPU can be made full use of again, to ensure processing of the CPU to affairs as much as possible.

The expansionary phase in the inhibition stage and control data bag of above-mentioned control data bag is required to determine control data bag Transmission rate, the embodiment of the present invention is according to the CIR of control data bag and is sent to corresponding buffer queue and inhibits data The rate of packet calculates the transmission rate of control data bag in a control data bag buffer queue.Specifically, it is retouched according to aforementioned It states, in the same control data bag buffer queue, data packet is inhibited to tie up control data bag, if the i-th buffer queue Guarantee information rate is CIR_i, then inhibit data packet transmission rate and the transmission rate of control data bag there are following relationships：

Rf_i=CIR_i-Df_i…………………………………………… (1)

Wherein, Rf_iFor the transmission rate of the control data bag in the i-th buffer queue, CIR_iFor the guarantor in the i-th buffer queue Demonstrate,prove information rate, Df_iFor the transmission rate of the inhibition data packet in the i-th buffer queue.

It, can for the more acurrate transmission rate for more easily determining control data bag in another preferred embodiment Measurement data packet is sent from coprocessor to grouping chip, the priority of measurement data packet is less than control in the same buffer queue The priority of data packet, and the address that the destination address of measurement data packet is coprocessor, coprocessor can pass through measurement data The transmission rate and receiving velocity of packet obtain the rate of control data bag.In this way, being measured in such a way that measurement data packet flows back The transmission rate of control data bag, this mode configure simply, measure simply, without being grouped the register of chip by reading, By way of external chip internal loopback, you can to complete the measurement to control data bag transmission rate.

Specifically, measurement data transmission rate is limited as the CIR of buffer queue, and the guarantee information in the i-th buffer queue is fast Rate is CIR_i, then there are following relationships for the transmission rate of the transmission rate and control data bag of measurement data packet：

Rf_i=CIR_i-Hf_i…………………………………………… (2)

Wherein, Rf_iFor the transmission rate of the control data bag in the i-th buffer queue, CIR_iFor the guarantor in the i-th buffer queue Demonstrate,prove information rate, Hf_iFor the receiving velocity of the measurement data packet in the i-th buffer queue, i.e., coprocessor receives in the unit interval The quantity for the measurement data packet reflux arrived.Special, work as Rf_i≥CIR_iWhen, the rate that measurement data packet flows back into coprocessor is 0, i.e. it is taken completely by control data bag in the i-th buffer queue.

After coprocessor is sent to grouping chip inhibits data packet, control number will be existed simultaneously in the same buffer queue According to packet, inhibit data packet and measurement data packet, due to inhibiting the priority of data packet to be higher than the priority of control data bag, control The priority of data packet is higher than the priority of measurement data packet again, then the transmission rate of the control data bag in the i-th buffer queue For：

Rf_i=CIR_i-Df_i-Hf_i…………………………………………… (3)

Wherein, Rf_iFor the transmission rate of the control data bag in the i-th buffer queue, CIR_iFor the guarantor in the i-th buffer queue Demonstrate,prove information rate, Df_iFor the transmission rate of the inhibition data packet in the i-th buffer queue, Hf_iFor the measurement number in the i-th buffer queue According to the receiving velocity of packet.

In the above embodiment of the present invention, mode that the utilization rate of CPU is detected can there are many, be given below one The preferred realization method of kind.

Cpu busy percentage control strategy provided in an embodiment of the present invention, when cpu busy percentage is higher than the expected upper limit, Xiang Huan It deposits to increase to send in queue and inhibits data packet, the utilization rate of CPU is made to decline, when cpu busy percentage is less than expected lower limit, reduce Inhibit data packet in buffer queue, so that the utilization rate of CPU is increased, make the timely processing of guarantee affairs.This is in the following manner It realizes, grouping chip provides ACL (accesses control list, Access Control List), can be to the control number that receives Lookup classification is carried out according to packet, is put it into corresponding control data bag buffer queue, each buffer queue can be to therein Packet rate is limited.From effect, it can regard that grouping chip makes each type of control data bag flow through one as Speed limit bucket, as shown in figure 14.After control data bag enters grouping chip, ACL makes different types of control data bag pass through respectively Corresponding speed limit keg, is up to CIR by the rate of the data packet of i-th of speed limit keg_i, i.e., each speed limit keg has one A maximum stream flow.In speed limit bucket, the data flow of high priority can tie up the data flow of low priority, data flow here As pass through the total amount of the data packet of speed limit bucket in certain time.Coprocessor in the embodiment of the present invention is for different types of Control data bag, the inhibition data packet of different rates is sent to grouping chip, wherein inhibiting the priority of data packet higher than control The priority of data packet.Grouping chip so that inhibition data packet is flowed into corresponding control data bag where speed limit keg, due to suppression The priority of data flow processed is relatively high, inhibits data flow that can be tied up to protocol data-flow, to reach inhibition protocol data The purpose of stream.

It further, can also be to entering CPU's on the basis of to each type of control data bag, speed limit keg is set A speed limit drum is arranged in all control data bags, i.e., when all types of control data bags come out from respective keg respectively Afterwards, it is made all to flow into speed limit drum, as shown in figure 15.This is allowed for when cpu busy percentage is more than third threshold value (third threshold Value is more than first threshold) when, preferentially the control data bag rate for entering CPU can be lowered using speed limit drum.Speed limit drum Principle it is similar with keg, be all that the data flow of high priority ties up the data flow of low priority, therefore, setting flow into The priority of the inhibition data packet of speed limit drum is higher than the priority of all control data bags, and the priority of measurement data packet is less than The priority of all control data bags.In speed limit drum, the utilization of the sum of rate of measurement data packet and inhibition data packet CPU Rate is related, is indifferent to the rate of specific control data bag, and speed limit keg is respectively calculated, and speed limit keg carries out each type of The Exact calculation of the rate of control data bag, speed limit drum carry out the control that all control data bags enter the total rates of CPU.Speed limit Drum is responsible for the utilization rate of CPU being reduced under third threshold value, and speed limit keg is responsible for the utilization rate of CPU being reduced to the first threshold Under value.

For a clearer understanding of the present invention, above-mentioned flow is described in detail with specific example below.The specific reality Flow described in example can be divided into initialization A, detection process B1 and B2, process of inhibition C and process of expansion D, as shown in figure 16.

Initialize A：To all parameter initializations.Specifically, process of inhibition and process of expansion are initialized to 1, that is, represent It is to be executed since the first stage of process of inhibition or the first stage of process of expansion.Find_i is that the priority in inhibition stage is looked into Variable is looked for, if there is the control data bag of N number of type, there are one priority for the control data bag of each type, such as (the addresses ARP Analysis protocol, Address Resolution Protocol) and APS (automatic protection switching, Automatic Protection Switched priority is different between), and the priority that the priority of ARP is 1, APS is 2, and setting find_i is initialized as 1, table Show from the inhibition stage from the minimum a type of control data bag of priority and begin look for measuring, is i.e. the low control number of priority Can first it be inhibited in the inhibition stage according to packet.Add_i is the priority lookup variable of expansionary phase, is initialized as N, indicates expansion rank Section is since the control data bag of highest priority.Long-term busy alarm instruction is initialized as 0, indicates CPU currently without place In long-term busy state.After having executed initialization, detection process B1 is executed.

Step B1：Detect cpu busy percentage.Specifically, according to description before it is known that probe data packet can be utilized It residence time T and empirical equation in CPU and obtains cpu busy percentage M, therefore need to only measure the residence time of probe data packet T。

Step B2：By T and tM₁、tM₂It is compared, if T>t M₁, then flow C, i.e. process of inhibition are executed；If T<tM₂, then Execute flow D, i.e. process of expansion.

Process of inhibition particularly may be divided into following steps, as shown in figure 17, wherein step C3~C9 is the first rank of process of inhibition Section, step C10~C15 are process of inhibition second stage：

Step C1：First by the initialization of variable of process of expansion one time, it is ready to switch to execute process of expansion.Specifically The first rank of process of expansion is first carried out when expression switchs to process of expansion from process of inhibition in ground, expansionary phase=1, add_i=N Section, and executed since the control data bag of highest priority.

Step C2：The first stage or second stage for judging progress process of inhibition then follow the steps if the first stage C3；If second stage, C10 is thened follow the steps.

Step C3：It is 0 by long-term busy alarm cue mark.Because what is executed at present is the process of inhibition first stage, also There is method that the utilization rate of CPU lowers, therefore is not necessarily to carry out long-term busy alarm.

Step C4：Measure the rate of the i-th two priority classes data packet.Since in initialization procedure, find_i is initialized It is 1, therefore in process of inhibition, it is measured since the minimum control data bag of priority.

Step C5：Judge whether the rate of the i-th two priority classes data packet is more than the minimum guarantee band of the control data bag Width, if so, thening follow the steps C6；If it is not, thening follow the steps C7.

Step C6：It is sent to the i-th two priority classes data packet and inhibits data packet, the rate of the control data bag is suppressed to Corresponding most low guaranteed bandwidth.

Step C7：Find_i adds 1, that is, goes to the control data bag of next priority.

Step C8：Judge whether find_i is more than N, if so, thening follow the steps C9；If it is not, thening follow the steps B1.

Step C9：It sets the inhibition stage to 2, find_i and is set as 1, then execute step B1.Specifically, previous step It is judged as "Yes", shows that the rate of the control data bag of all priority is suppressed to most low guaranteed bandwidth, if CPU at this time Utilization rate still greater than threshold value, then need the second stage for going to process of inhibition, inhibit since lowest priority again.Anti- mistake Come, if previous step is judged as "No", shows still to have the rate of control data bag not to be suppressed to most low guaranteed bandwidth, can continue Inhibit the control data bag of next priority.

Step C10：It is sent to the i-th two priority classes data packet and inhibits data packet, the rate of the control data bag is inhibited It is zero.

Step C11：Find_i adds 1, that is, goes to the control data bag of next priority.

Step C12：Judge whether find_i is more than N, if so, thening follow the steps C13；If it is not, thening follow the steps B1.

Step C13：It sets find_i to N, and long-term busy alarm instruction is added 1, then execute step C14.Specifically For, after the rate of highest priority control data bag is suppressed to zero, long-term busy alarm instruction is carried out plus 1 operates, Show the inhibition by front, without good effect, the utilization rate of CPU has been the of process of inhibition at this time still greater than threshold value M Two-stage, and the rate of all control data bags has all been suppressed to 0, still in process of inhibition, illustrates that CPU is still very busy, It needs long-term busy alarm instruction to be increased.

Step C14：Judge that long-term busy alarm indicates whether to be more than threshold value L, if so, C15 is thened follow the steps, if it is not, then Step B1 is executed, wherein L is the integer more than 0.

Step C15：Long-term busy alarm is sent, and goes to step B1.

Process of inhibition, which has been introduced, as a result, finishes, and process of expansion is described below, and as shown in figure 18, can be divided into following steps, In, step D3~D8 is the process of expansion first stage, and step D9~D13 is process of expansion second stage.

Step D1：First by the initialization of variable of process of inhibition one time, it is ready to switch to execute process of inhibition.Specifically Ground inhibits stage=1, find_i=1 that the first of process of inhibition is first carried out when expression switchs to process of inhibition from process of expansion Stage, and executed since the minimum control data bag of priority.

Step D2：The first stage or second stage for judging progress process of expansion then follow the steps if the first stage D3；If second stage, D9 is thened follow the steps.

Step D3：Measure the rate of the i-th two priority classes data packet.Since in initialization procedure, add_i is initialized as N, therefore in process of expansion, it is measured since the control data bag of highest priority.

Step D4：Judge whether the rate of the i-th two priority classes data packet is more than the minimum guarantee band of the control data bag Width, if so, thening follow the steps D5；If it is not, thening follow the steps D6.

Step D5：It reduces to the i-th two priority classes data packet and sends an inhibition data packet, then execute step B1.Effect On fruit, the rate of the control data bag of the i-th priority can be made to slowly rise to corresponding most low guaranteed bandwidth, then change one The step of control data bag of priority executes below.

Step D6：Add_i subtracts one, that is, goes to the lower control data bag of next priority.

Step D7：Judge whether add_i is less than 1, if so, thening follow the steps D8；If it is not, thening follow the steps B1.

Step D8：It will be set as 2, add_i the expansionary phases and be set as N, and then execute step B1.Specifically, previous step It is judged as "Yes", shows that the rate of the control data bag of all priority has been made to be raised to most low guaranteed bandwidth, if the profit of CPU at this time With rate still less than threshold value, then the second stage for going to process of expansion is needed, reduces and inhibit since highest priority again.Anti- mistake Come, if previous step is judged as "No", shows still to have the rate of control data bag not to be raised to most low guaranteed bandwidth, can continue to reduce Inhibit the control data bag of next priority.

Step D9：It reduces to the i-th two priority classes data packet and sends an inhibition data packet.

Step D10：Judge whether the inhibition data packet sent to the i-th two priority classes data packet has been reduced to zero, if so, Execute step D11；If it is not, thening follow the steps B1.

Step D11：Add_i subtracts 1, that is, goes to the control data bag of next priority.Specifically, forward direction i-th is preferential The inhibition data packet that grade control data bag is sent has been reduced to zero, i.e., is not sent to the i-th two priority classes data packet and inhibit data packet, If the utilization rate of CPU shows CPU still in idle state still less than threshold value at this time, then reduce to the lower control of next priority Data packet processed, which is sent, inhibits data packet.

Step D12：Judge whether add_i is less than 1, if so, thening follow the steps D13；If it is not, thening follow the steps B1.

Step D13：Add_i is set as 1, then executes step B1.

The control method of the embodiment of the present invention provides a kind of two step control strategies, and for process of inhibition and expanded Controlling extents different Cheng Caiyong can quickly reduce impact of the excessive data packet to CPU, be slowly increased CPU processing load Ability provides good protection to CPU.Meanwhile, it is capable to take into account the priority of different agreement, make the control data of high priority First recovery is inhibited to handle after coating.

Based on the same technical idea, the embodiment of the present invention also provides a kind of cpu busy percentage control device, and Figure 19 is shown Control cpu busy percentage system schematic, cpu busy percentage control device as shown in I in Figure 19, including：Detecting module 1 is sentenced Disconnected module 2 and suppression module 3；

The detecting module 1, the utilization rate for detecting central processor CPU；

The judgment module 2, for judging whether the utilization rate of the CPU is greater than or equal to first threshold；

The suppression module 3 is used for when the utilization rate of the CPU is greater than or equal to the first threshold, according to control The priority of data packet determines the control data bag buffer queue for needing enlargement discharge to inhibit, and improves to increase to the needs and flow The control data bag buffer queue that amount inhibits sends the rate for inhibiting data packet；Wherein, the grouping chip includes N number of control Data pack buffer queue, N are the integer more than 1, and the priority of the inhibition data packet in a control data bag buffer queue is high The priority of control data bag in the buffer queue, inhibition data packet in a control data bag buffer queue is from institute Control data bag buffer queue go out team after be dropped, the control data bag in a control data bag buffer queue is forwarded To the CPU.

Preferably, the suppression module 3 is used for：According to the priority sequence from low to high of control data bag, determining needs The control data bag buffer queue for wanting enlargement discharge to inhibit.

Preferably, the sequence according to the control data bag priority cached from low to high, N number of control data bag is slow It deposits queue and includes the first buffer queue to N buffer queues；

The suppression module 3 is specifically used for executing following steps：

Step 1201：I is set as 1；

Step 1202：Judge whether the transmission rate of the control data bag in the i-th buffer queue is higher than the control data Otherwise the minimum guaranteed rate of packet is transferred to step 1205 if so, being transferred to step 1203；

Step 1203：It is sent to the i-th buffer queue and inhibits data packet, the speed for inhibiting data packet is sent to the i-th buffer queue The transmission rate that rate is equal to the control data bag in the i-th buffer queue subtracts obtained by the minimum guaranteed rate of the control data bag The difference arrived；

Step 1204：The utilization rate of the CPU is detected, if the utilization rate of the CPU is greater than or equal to the first threshold, Then it is transferred to step 1205；

Step 1205：I is incremented by 1；

Step 1206：If i≤N is transferred to step 1202.

Preferably, the suppression module 3 is additionally operable to execute following steps：

In the step 1205, if i>N is then transferred to step 1207；

Step 1207：I is set as 1；

Step 1208：Increase the rate for being sent to the i-th buffer queue and inhibiting data packet, sends and inhibit to the i-th buffer queue The increased rate of data packet is equal to the transmission rate of the control data bag in the i-th buffer queue；

Step 1209：The utilization rate of the CPU is detected, if the utilization rate of the CPU is greater than or equal to the first threshold, Then it is transferred to step 210；

Step 1210：I is incremented by 1；

Step 1211：If i≤N is transferred to step 1208.

Preferably, the suppression module 3 is additionally operable to：

In the step 1211, if i>N then sends and is used to indicate the high alarm instruction of cpu busy percentage.

Preferably, the suppression module 3 is additionally operable to：

If the utilization rate of the CPU is less than second threshold, is determined according to the priority of control data bag and need to reduce stream The control data bag buffer queue inhibited is measured, and is reduced to the control data bag buffer queue hair for needing to reduce flow inhibition Send the rate for inhibiting data packet；Wherein, the second threshold is less than or equal to the first threshold.

Preferably, the suppression module 3 is additionally operable to：According to the priority sequence from high to low of control data bag, determine It needs to reduce the control data bag buffer queue that flow inhibits.

Preferably, the priority of N number of buffer queue is different each other, according to the sequence of priority from low to high, N number of buffer queue includes the first buffer queue to N buffer queues；

The suppression module 3 is specifically used for executing following steps：

Step 1301：Set i to N；

Step 1302：Judge whether the transmission rate of the control data bag in the i-th buffer queue is less than the control data Otherwise the minimum guaranteed rate of packet is transferred to step 1305 if so, being transferred to step 1303；

Step 1303：It is reduced according to setting step-length and sends the rate for inhibiting data packet to the i-th buffer queue, be transferred to step 1304；

Step 1304：The utilization rate of the CPU is detected, if the utilization rate of the CPU is less than or equal to the second threshold, Then it is transferred to step 1302；

Step 1305：I is successively decreased 1；

Step 1306：If i >=1 is transferred to step 1302.

Preferably, the suppression module is additionally operable to execute following steps：

In the step 1306, if i<1, then it is transferred to step 1307；

Step 1307：Set i to N；

Step 1308：Judge that the i-th buffer queue is sent and inhibit whether the rate of data packet is more than zero, if so, being transferred to step Rapid 1309, otherwise it is transferred to step 1311；

Step 1309：It reduces to send to the i-th buffer queue according to setting step-length and inhibits data packet；

Step 1310：The utilization rate of the CPU is detected, if the utilization rate of the CPU is less than or equal to the second threshold, Then it is transferred to step 1311；

Step 1311：I is successively decreased 1；

Step 1312：If i >=1 is transferred to step 1308.

Preferably, device further includes measurement module 4, as shown in the II of Figure 20, measurement module 4 is for measuring the control number According to the transmission rate of packet, the transmission rate of the control data bag in i-th buffer queue is：

Rf_i=CIR_i-Df_i-Hf_i

Wherein, Rf_iFor the transmission rate of the control data bag in the i-th buffer queue, CIR_iFor the guarantor in the i-th buffer queue Demonstrate,prove information rate, Df_iFor the transmission rate of the inhibition data packet in the i-th buffer queue, Hf_iFor the measurement number in the i-th buffer queue According to the receiving velocity of packet；The priority of measurement data packet in one buffer queue is less than the control data bag in the buffer queue Priority.

Preferably, detecting module 1 is specifically used for：

Probe data packet is sent to the CPU, and receives the probe data packet that the CPU is returned；

According to the difference of the sending time of the probe data packet and receiving time, obtain the probe data packet described Residence time in CPU；

Pre-set residence time and CPU profits are inquired according to residence time of the probe data packet in the CPU With the correspondence of rate, the utilization rate of the CPU is obtained.

Example IV

In the above-described embodiments, embodiment one or example two cache all types of control data using single buffer queue Packet, when cpu busy percentage is greater than or equal to first threshold, coprocessor inhibits data packet by improving to send to the buffer queue Transmission rate, thus the rate that control data bag in the buffer queue is sent to CPU is reduced, to reduce cpu busy percentage； When cpu busy percentage is less than second threshold, coprocessor inhibits the transmission of data packet by reducing to the transmission of the buffer queue Rate, thus the rate that control data bag in the buffer queue is sent to CPU is improved, to improve cpu busy percentage.

Embodiment three is to use N number of buffer queue, the control data bag of N types is cached respectively, when cpu busy percentage is more than Or when equal to first threshold, coprocessor is respectively increased according to the priority orders of control data bag in buffer queue to N number of slow It deposits team and sends the transmission rate for inhibiting data packet, i.e., since the corresponding buffer queue of the minimum control data bag of priority, point It is indescribably high that the transmission rate for inhibiting data packet is sent to N number of buffer queue, it is sent out in N number of buffer queue to reduce on the whole It send to the transmission rate of the control data bag of CPU, to reduce cpu busy percentage；When cpu busy percentage is less than second threshold, Coprocessor is sent to reduction to N number of buffer queue respectively according to the priority orders of control data bag in buffer queue inhibits number According to the transmission rate of packet, i.e., since the corresponding buffer queue of the control data bag of highest priority, reduced respectively to N number of caching Queue sends the transmission rate for inhibiting data Ah Bai, to improve the control number that N number of buffer queue is sent to CPU on the whole According to the transmission rate of packet, to improve cpu busy percentage.

Above two method, individually implements, and can efficiently control cpu busy percentage.Wherein, embodiment one or real Apply example two offer single buffer queue method due to not divided according to priority to control data bag, can be relatively quickly Reduce or improve cpu busy percentage；And embodiment three is due to considering that according to priority sequence is cached respectively to N number of team by control data bag Row, when needing to control the transmission rate of control data bag, it may be considered that controlled successively according to priority orders, to have Good actual application value.Therefore, the method that the embodiment of the present invention four provides another control cpu busy percentage, i.e., will be real It applies example one and embodiment three combines, or embodiment two and example IV are combined, formed as shown in figure 15 The method of cpu busy percentage control.

In example IV, for example, when cpu busy percentage is when more than first threshold, needing to reduce, first with embodiment One or the method for single buffer queue of embodiment two cpu busy percentage is reduced to second threshold, then reuse embodiment three and carry Cpu busy percentage is continued to reduce by the method for confession, and herein, the first threshold in the method that embodiment two provides is equivalent to implement Then second threshold in embodiment three can be regarded as the third in example IV by the second threshold in example one or embodiment two Threshold value.

For ease of understanding, the relationship between each threshold value in example IV is explained with reference to specific example.Example If current cpu busy percentage is 90%, the method that embodiment one or embodiment two provide can be used to be reduced to cpu busy percentage 80%, the method for then reusing the offer of embodiment two controls cpu busy percentage 70%, therefore 90% here is equivalent to reality It applies example one or implements the first threshold in two, 80% is equivalent to embodiment one or second threshold in embodiment two and is equivalent to First threshold in embodiment three, 70% is equivalent to the second threshold in embodiment three.In example IV, 70% is regarded as Third threshold value.

Referring to Fig. 7, in step 706, if judging, obtaining cpu busy percentage is greater than or equal to second threshold M2, using real The method in example three is applied to further decrease cpu busy percentage, second threshold M2 here is equivalent to the first threshold of embodiment three.

It is above-mentioned one method of embodiment and three method of embodiment are combined by way of, or by two method of embodiment and The mode that three method of embodiment combines by cpu busy percentage by single buffer queue, it can be achieved that be quickly reduced to some threshold first Within value, the transmission rate of control data bag is then reduced successively according still further to the priority orders of control data bag, realize into one Step control cpu busy percentage, the method which provides takes into account efficiently control cpu busy percentage and actual application ability, therefore has There is excellent characteristics.

The present invention be with reference to according to the method for the embodiment of the present invention, the flow of equipment (system) and computer program product Figure and/or block diagram describe.It should be understood that can be realized by computer program instructions every first-class in flowchart and/or the block diagram The combination of flow and/or box in journey and/or box and flowchart and/or the block diagram.These computer programs can be provided Instruct the processor of all-purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce A raw machine so that the instruction executed by computer or the processor of other programmable data processing devices is generated for real The device for the function of being specified in present one flow of flow chart or one box of multiple flows and/or block diagram or multiple boxes.

These computer program instructions, which may also be stored in, can guide computer or other programmable data processing devices with spy Determine in the computer-readable memory that mode works so that instruction generation stored in the computer readable memory includes referring to Enable the manufacture of device, the command device realize in one flow of flow chart or multiple flows and/or one box of block diagram or The function of being specified in multiple boxes.

These computer program instructions also can be loaded onto a computer or other programmable data processing device so that count Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, in computer or The instruction executed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one The step of function of being specified in a box or multiple boxes.

Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as It selects embodiment and falls into all change and modification of the scope of the invention.

Obviously, various changes and modifications can be made to the invention without departing from essence of the invention by those skilled in the art God and range.In this way, if these modifications and changes of the present invention belongs to the range of the claims in the present invention and its equivalent technologies Within, then the present invention is also intended to include these modifications and variations.

Claims

1. a kind of cpu busy percentage control method, which is characterized in that including：

Detect the utilization rate of central processor CPU；

If the utilization rate of the CPU is greater than or equal to first threshold, judge that the first buffer queue into grouping chip is sent Inhibit whether the transmission rate of data packet is less than the minimum guaranteed rate of first buffer queue, wherein first caching Queue for caching all control data bags for being sent to the CPU, the inhibition data packet in first buffer queue from First buffer queue is dropped after going out team, and the minimum guaranteed rate is forwarding in the first buffer queue unit interval Data packet number maximum value；

If so, improving the transmission rate for being sent to first buffer queue and inhibiting data packet；Wherein, first caching team The priority of inhibition data packet in row is higher than the priority of the control data bag in first buffer queue.

2. the method as described in claim 1, which is characterized in that described improve to first buffer queue sends inhibition data The transmission rate of packet, including：

It is returned according to the quantity for the measurement data packet for being sent to first buffer queue and from first buffer queue The quantity of measurement data packet determines the quantity of the measurement data packet in first buffer queue；Wherein, first caching team The priority of measurement data packet in row is less than the priority of the control data bag in first buffer queue, the measurement data Packet is sent to first buffer queue by coprocessor and is forwarded to the coprocessor, the measurement data after going out team The transmission rate of packet is the minimum guaranteed rate of first buffer queue；

If the quantity of the measurement data packet in first buffer queue is more than zero, it is determined that sent to first buffer queue Inhibit the transmission rate of data packet, and is sent to first buffer queue according to the transmission rate for the inhibition data packet determined Inhibit data packet, wherein the transmission rate determined is equal to the measurement that first buffer queue is sent in the unit interval The difference of the quantity of data packet and the quantity of the measurement data packet returned from first buffer queue；Or

If the quantity of the measurement data packet in first buffer queue is equal to zero, improved to described first according to setting step-length Buffer queue sends the transmission rate for inhibiting data packet, and is sent to first buffer queue according to the transmission rate after raising Inhibit data packet.

3. method as claimed in claim 2, which is characterized in that described to be improved to first buffer queue according to setting step-length The transmission rate for inhibiting data packet is sent, and is sent to first buffer queue according to the transmission rate after raising and inhibits data Packet, including：

Step A：Detect the utilization rate of CPU；

Step C：Judge to send whether the transmission rate for inhibiting data packet is more than first caching to first buffer queue Otherwise the minimum guaranteed rate of queue is transferred to step D if so, being transferred to step A；

Step D：It is improved according to setting step-length and sends the transmission rate for inhibiting data packet to first buffer queue, and be transferred to step Rapid A.

4. the method as described in claim 1, which is characterized in that further include：

If the utilization rate of the CPU is less than second threshold, the hair for being sent to first buffer queue and inhibiting data packet is reduced Transmission rate；Wherein, the second threshold is less than or equal to the first threshold.

5. method as claimed in claim 4, which is characterized in that if the utilization rate of the CPU be less than second threshold, reduce to First buffer queue sends the transmission rate for inhibiting data packet, including：

Step A：Detect the utilization rate of CPU；

Step B：If the utilization rate of the CPU is less than the second threshold, it is transferred to step C；

Step C：Judge to send whether the transmission rate for inhibiting data packet is more than zero to first buffer queue, if so, turning Enter step D, is otherwise transferred to step A；

Step D：It is reduced according to setting step-length and sends the transmission rate for inhibiting data packet to first buffer queue, and be transferred to step Rapid A.

6. the method as described in any one of claim 1 to 5, which is characterized in that further include：

If the cpu busy percentage is less than the first threshold and is greater than or equal to second threshold, according to the control in grouping chip The priority of data packet processed determines the control data bag buffer queue for needing enlargement discharge to inhibit, and improves and need to increase to described The control data bag buffer queue that flow inhibits sends the rate for inhibiting data packet；Wherein, the grouping chip includes N number of control Data pack buffer queue processed, N are the integer more than 1, the priority of the inhibition data packet in a control data bag buffer queue Higher than the priority of the control data bag in the buffer queue, inhibition data packet in a control data bag buffer queue from The control data bag buffer queue at place is dropped after going out team, and the control data bag in a control data bag buffer queue goes out team Enter the first buffer queue afterwards.

7. method as claimed in claim 6, which is characterized in that the control data bag buffer queue in the chip according to grouping Priority determine need enlargement discharge inhibit control data bag buffer queue, including：

According to the priority sequence from low to high of control data bag, the control data bag caching for needing enlargement discharge to inhibit is determined Queue.

8. method as claimed in claim 6, which is characterized in that further include：

If the utilization rate of the CPU is less than the second threshold, is determined according to the priority of control data bag and need to reduce stream The control data bag buffer queue inhibited is measured, and is reduced to the control data bag buffer queue hair for needing to reduce flow inhibition Send the rate for inhibiting data packet.

9. method as claimed in claim 8, which is characterized in that described to need to reduce according to the determination of the priority of control data bag The control data bag buffer queue that flow inhibits, including：

It is determined according to the priority sequence from high to low of the buffer queue in the grouping chip and needs to reduce what flow inhibited Control data bag buffer queue.

10. a kind of cpu busy percentage control device, which is characterized in that including：

Probe unit, the utilization rate for detecting central processor CPU；

Judging unit, for judge CPU utilization rate whether be greater than or equal to first threshold, and judge to grouping chip in First buffer queue sends the minimum guaranteed rate for inhibiting the transmission rate of data packet whether to be less than first buffer queue, In, first buffer queue is for caching all control data bags for being sent to the CPU, in first buffer queue Data packet is inhibited to be dropped after going out team from first buffer queue, the minimum guaranteed rate is first buffer queue The maximum value of the data packet number forwarded in unit interval；

Inhibit unit, for being greater than or equal to first threshold, and the first buffer queue into grouping chip when the utilization rate of CPU The minimum guaranteed rate for inhibiting the transmission rate of data packet to be less than first buffer queue is sent, then is improved slow to described first It deposits queue and sends the transmission rate for inhibiting data packet；Wherein, the priority of the inhibition data packet in first buffer queue is high The priority of control data bag in first buffer queue.

11. device as claimed in claim 10, which is characterized in that the inhibition unit includes：

Determination subelement, for according to the measurement data packet for being sent to first buffer queue quantity and from described first The quantity for the measurement data packet that buffer queue returns, determines the quantity of the measurement data packet in first buffer queue；Wherein, The priority of measurement data packet in first buffer queue is less than the preferential of the control data bag in first buffer queue Grade, the measurement data packet are sent to first buffer queue by coprocessor and are forwarded to association's processing after going out team Device, the transmission rate of the measurement data packet are the minimum guaranteed rate of first buffer queue；

Inhibit subelement, when the quantity for the measurement data packet in first buffer queue is more than zero, data packet will be inhibited Transmission rate be set as being sent to the measurement data packet quantity of first buffer queue and the institute received in the unit interval State the first buffer queue forwarding measurement data packet quantity difference, and according to the transmission rate for the inhibition data packet determined to First buffer queue, which is sent, inhibits data packet；Wherein, the survey of first buffer queue is sent in the unit interval Amount data packet number is identical as the minimum guaranteed rate of the first buffer queue, and data packet is excellent in first buffer queue First grade is followed successively by inhibition data packet, control data bag, measurement data packet from high to low；Or

When the quantity of measurement data packet is equal to zero in first buffer queue, improved according to setting step-length slow to described first It deposits queue and sends the transmission rate for inhibiting data packet, and send and press down to first buffer queue according to the transmission rate after raising Data packet processed.

12. device as claimed in claim 11, which is characterized in that the inhibition subelement is specifically used for executing following below scheme：

Step A：Detect the utilization rate of CPU；

13. device as claimed in claim 10, which is characterized in that the inhibition unit is additionally operable to：

14. device as claimed in claim 13, which is characterized in that the inhibition unit is specifically used for executing following below scheme：

Step A：Detect the utilization rate of CPU；

15. the device as described in any one of claim 10 to 14, which is characterized in that the inhibition unit is additionally operable to：

16. device as claimed in claim 15, which is characterized in that the inhibition unit is specifically used for：

17. device as claimed in claim 15, which is characterized in that the inhibition unit is specifically used for：

When the utilization rate of the CPU is less than the second threshold, is determined according to the priority of control data bag and need to reduce stream The control data bag buffer queue inhibited is measured, and is reduced to the control data bag buffer queue hair for needing to reduce flow inhibition Send the rate for inhibiting data packet.

18. device as claimed in claim 17, which is characterized in that the inhibition unit is specifically used for：