CN105183431A

CN105183431A - Method and apparatus for controlling CPU utilization ratio

Info

Publication number: CN105183431A
Application number: CN201510476043.1A
Authority: CN
Inventors: 郭瑞; 乔强国
Original assignee: Raisecom Technology Co Ltd
Current assignee: Raisecom Technology Co Ltd
Priority date: 2015-08-05
Filing date: 2015-08-05
Publication date: 2015-12-23
Anticipated expiration: 2035-08-05
Also published as: CN105183431B

Abstract

The present invention discloses a method and apparatus for controlling a CPU utilization ratio. At first, the utilization ratio of a central processing unit CPU is detected. If the CPU utilization ratio is greater than or equal to a first threshold value, whether a transmission rate of a suppression data packet sent to a first cache queue in a grouped chip is less than the minimum guaranteed rate of the first cache queue is determined. If yes, the transmission rate of the suppression data packet sent to the first cache queue is enhanced. The first cache queue is used to cache all of control data packets sent to the CPU. The suppression data packet in the first cache queue is discarded after dequeuing from the cache queue. Furthermore, the priority of the suppression data packet in the first cache queue is higher than that of the control data packet in the first cache queue. Therefore, the enhancement of the suppression data packet sent to the first cache queue can reduce the transmission rate of the control data packet in the first cache queue, thereby controlling the CPU utilization ratio by controlling a rate of the control data packet entering into the CPU.

Description

A kind of cpu busy percentage control method and device

Technical field

The present invention relates to computer communication technology field, particularly relate to a kind of cpu busy percentage control method and device.

Background technology

In switching equipment and routing device, grouping chip is responsible for the work of datum plane, the forwarding of such as packet or route, CPU (CentralProcessingUnit, central processing unit) be responsible for the work of control plane, such as protocol processes work, coprocessor also can share some protocol processes work.

Cpu busy percentage refers to that the time of CPU actual treatment data in a period of time accounts for the number percent of actual run time, is the index of reflection CPU duty and treatment effeciency.The factor affecting cpu busy percentage mainly contains two aspects, is physical event on the one hand, and such as port connects or disconnects, and physical temperature is too high or too low; Be the impact of packet to CPU on the other hand, generally, send to the speed of the packet of CPU higher, larger to the impact of CPU, the utilization factor of CPU is higher.

Under switching equipment or routing device normal operating conditions, the number of times that physical event occurs impacts the number of times of CPU much smaller than packet, therefore controls the packet entering CPU, becomes the key controlling cpu busy percentage height.

Summary of the invention

The embodiment of the present invention provides a kind of cpu busy percentage control method and device, in order in conjunction with the current utilization factor of CPU, adopts the mode suppressing packet to tie up control data bag, realizes the effective control to cpu busy percentage.

The embodiment of the present application provides a kind of cpu busy percentage control method, and the method comprises:

The utilization factor of detection central processor CPU;

If the utilization factor of described CPU is more than or equal to first threshold, then judge to send to the first buffer queue in grouping chip the minimum guaranteed rate suppressing the transmission rate of packet whether to be less than described first buffer queue, wherein, described first buffer queue is used for all control data bags that buffer memory sends to described CPU, and the suppression packet in described first buffer queue is dropped after going out team from described buffer queue;

If so, then improve and send to described first buffer queue the transmission rate suppressing packet; Wherein, the priority of the suppression packet in described first buffer queue is higher than the priority of the control data bag in described first buffer queue.

The application is that embodiment provides a kind of cpu busy percentage control device, and this device comprises:

Probe unit, for detecting the utilization factor of central processor CPU;

Judging unit, for judging whether the utilization factor of CPU is more than or equal to first threshold, and judge to send to the first buffer queue in grouping chip the minimum guaranteed rate suppressing the transmission rate of packet whether to be less than described first buffer queue, wherein, described first buffer queue is used for all control data bags that buffer memory sends to described CPU, and the suppression packet in described first buffer queue is dropped after going out team from described buffer queue;

Suppress unit, first threshold is more than or equal to for the utilization factor as CPU, and send to the first buffer queue in grouping chip the minimum guaranteed rate suppressing the transmission rate of packet to be less than described first buffer queue, then improve and send to described first buffer queue the transmission rate suppressing packet; Wherein, the priority of the suppression packet in described first buffer queue is higher than the priority of the control data bag in described first buffer queue.

In the embodiment of the present invention, the speed entering CPU by controlling control data bag reaches the effect reducing cpu busy percentage, wherein, first the utilization factor of central processor CPU is detected, if the utilization factor of CPU is more than or equal to first threshold, then judge to send to the first buffer queue in grouping chip the minimum guaranteed rate suppressing the transmission rate of packet whether to be less than the first buffer queue, if, then improve and send to the first buffer queue the transmission rate suppressing packet, wherein, the first buffer queue is used for all control data bags that buffer memory sends to described CPU.Because the suppression packet in the first buffer queue is dropped after going out team from this buffer queue, and first the priority of suppression packet in buffer queue higher than the priority of the control data bag in the first buffer queue, thus formation suppresses packet paired domination number to tie up according to bag, therefore improve and suppress Packet Generation can reduce the transmission rate of the control data bag in the first buffer queue in the first buffer queue, thus the speed achieved by controlling to enter the control data bag of CPU controls cpu busy percentage.

Accompanying drawing explanation

In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly introduced, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

Fig. 1 is the equipment inner structure figure that the embodiment of the present invention is suitable for;

The cpu busy percentage control flow schematic diagram that Fig. 2 provides for the embodiment of the present invention;

The cpu busy percentage control device structural representation that Fig. 3 provides for the embodiment of the present invention;

The cpu busy percentage sniffer structural representation that Fig. 4 provides for the embodiment of the present invention;

Fig. 5 is the schematic diagram detecting the cpu busy percentage starting stage in the embodiment of the present invention;

Fig. 6 is the corresponding relation figure of the residence time of cpu busy percentage and probe data packet in the embodiment of the present invention;

The cpu busy percentage control flow schematic diagram that Fig. 7 provides for the embodiment of the present invention;

The cpu busy percentage control flow schematic diagram that Fig. 8 provides for the embodiment of the present invention;

The cpu busy percentage sniffer structural representation that Fig. 9 provides for the embodiment of the present invention;

The cpu busy percentage sniffer structural representation that Figure 10 provides for the embodiment of the present invention;

The structure principle chart of the control cpu busy percentage device that Figure 11 provides for the embodiment of the present invention;

The process of inhibition of the control data bag that Figure 12 provides for the embodiment of the present invention first processing stage and second processing stage process flow diagram;

Figure 13 is the process of expansion of control data bag that provides in the embodiment of the present invention first processing stage and second processing stage process flow diagram;

Figure 14 is that in the embodiment of the present invention, speed limit keg suppresses schematic diagram;

Figure 15 is that in the embodiment of the present invention, speed limit drum and speed limit keg suppress schematic diagram jointly;

Figure 16 is the process flow diagram of embodiment of the present invention cpu busy percentage control method;

Figure 17 is the process flow diagram of the process of inhibition of embodiment of the present invention cpu busy percentage control method;

Figure 18 is the process flow diagram of the process of expansion of embodiment of the present invention cpu busy percentage control method;

Figure 19 is the system schematic that the embodiment of the present invention controls cpu busy percentage;

Figure 20 is the system schematic of another control cpu busy percentage of the embodiment of the present invention

Embodiment

In order to make the object, technical solutions and advantages of the present invention clearly, below in conjunction with accompanying drawing, the present invention is described in further detail, and obviously, described embodiment is only a part of embodiment of the present invention, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.

Fig. 1 schematically illustrates the inner structure of the equipment that the embodiment of the present invention is suitable for.This equipment can be router or switch, or other can realize the equipment of data retransmission function.

As shown in Figure 1, this equipment can comprise: CPU101, coprocessor 102 and grouping chip 103.CPU101 is in charge of and controls the normal work of whole system, and grouping chip 103 is responsible for forwarding or the route of packet, specifically, after business data packet enters grouping chip, carries out forward process, be forwarded to corresponding outbound port through grouping chip.Coprocessor 102 for sharing some protocol processes work of CPU, or is expanded for the upgrading of function, and coprocessor 102 can be realized by FPGA (field programmable gate array, Field-ProgrammableGateArray).

Between CPU and grouping chip, can realize exchanges data between coprocessor and grouping chip respectively by data channel, control data bag enters CPU by the data channel between CPU after entering grouping chip and carries out protocol processes.CPU controls coprocessor and grouping chip operation by control channel, and coprocessor and grouping chip can send event request respectively by event channel to CPU101.Wherein, bear control information in control data bag, different from business data packet, be transmitted to CPU by grouping chip, protocol data bag and management data bag can be comprised.Protocol data bag is according to the difference of protocol type, different functions can be realized, ARP (address resolution protocol can be comprised, AddressResolutionProtocol) message, in order to according to IP address acquisition physical address, such as, it can also be OSPF (ospf, OpenShortestPathFirst) message, for setting up LSD, generates shortest path tree.Management data bag can realize different management functions, SNMP (Simple Network Management Protocol can be comprised, SimpleNetworkManagementProtocol) message, can managing network device, Timeliness coverage also solves the growth of network problem and planning network, for another example, can be TelNet (remote terminal protocol, TelecommunicationsNetwork) message, can realize controlling distance host work on the local computer.

In the embodiment of the present invention, in order to realize the control to cpu busy percentage, in equipment running process, utilization factor that can be current according to CPU, utilize and suppress packet paired domination number to tie up according to bag, thus paired domination number controls according to the transmission rate of wrapping, and then the object that realization controls cpu busy percentage.Wherein, in the embodiment of the present invention, the transmission rate of control data bag refers to that control data bag is sent to the speed of CPU.

Wherein, described suppression packet is the packet of a kind of specific type defined in the embodiment of the present invention, suppress packet can generate and send to grouping chip by coprocessor, the process of grouping chip is abandoned after completing and suppressing packet or is sent to coprocessor, the suppression data packet discarding will returned from grouping chip by coprocessor.Suppress the priority of priority higher than control data bag of packet, thus realize paired domination number according to wrapping the object carrying out tying up.

Embodiment one

As shown in Figure 2, a kind of cpu busy percentage control flow schematic diagram that the embodiment of the present invention provides, this flow process can perform in coprocessor side.

Step 201, the utilization factor of detection CPU.

Step 202, judges whether the utilization factor of CPU is more than or equal to first threshold.

Wherein, first threshold is used for weighing the degree of utilization factor of CPU, if the utilization factor of the CPU detected in step 201 is more than or equal to this threshold value, then shows that the utilization factor of current C PU is higher, needs to control the quantity of the control data bag entering CPU.The value of first threshold can according to the performance of CPU or as required etc. many factors set, such as this first threshold can value be 80%.

Therefore when the utilization factor of CPU is more than or equal to first threshold, forward step 203, otherwise forward step 201 to, continue the utilization factor keeping detection CPU.

Step 203, judges to send to the first buffer queue in grouping chip the minimum guaranteed rate suppressing the speed of packet whether to be less than the first buffer queue.

The first buffer queue in grouping chip is used for control data bag in caching system, suppresses packet.First buffer queue has the restriction of a minimum guaranteed rate, and the data packet number namely forwarded in the first buffer queue unit interval mostly is the minimum guaranteed rate value of the first buffer queue most.

After control data bag is sent to the first buffer queue in grouping chip, is forwarded to CPU by grouping chip, does corresponding process by CPU according to the protocol contents that control data bag carries; Suppress packet to be sent to the first buffer queue in grouping chip by coprocessor, be then forwarded to coprocessor by grouping chip, abandoned by protocol processor, or be directly forwarded to and abandon port, abandoning port will suppress data packet discarding.

In the first buffer queue, suppress the priority of packet higher than the priority of control data bag, the packet of the first buffer queue in protocol packet chip according to priority in routing forwarding buffer queue.

Therefore, when according to priority orders, suppression packet in first buffer queue meeting priority processing queue, and the speed of the first buffer queue forwarding data bag is the minimum guaranteed rate of the first buffer queue to the maximum, namely in the unit interval, the quantity of the first buffer queue forwarding data bag is maximum equals minimum guaranteed rate value, therefore when the suppression packet in the first buffer queue is more, it is fewer that control data bag is processed, and then the agreement school bag entering CPU in the unit interval will be fewer, therefore cpu busy percentage will reduce.

Can be found out by above implementation, when coprocessor sends suppression packet to the first buffer queue in grouping chip, cpu busy percentage can be reduced, but because the rate-limit of the first buffer queue forwarding data bag is minimum guaranteed rate, therefore before sending suppression packet to the first buffer queue, first to judge to send to the first buffer queue in grouping chip the minimum guaranteed rate suppressing the speed of packet whether to be less than the first buffer queue, if, then forward step 204 to, if not, then forward step 201 to, continue the detection keeping cpu busy percentage.

Step 204, improves and sends to the first buffer queue the transmission rate suppressing packet.

In step 203, send to the first buffer queue in grouping chip the minimum guaranteed rate suppressing the speed of packet to be less than the first buffer queue if judge, namely show that current first buffer queue does not also reach the upper limit of forwarding data bag, therefore can also continue to improve and send to the first buffer queue the speed suppressing packet, to disinthibite further the transmission rate of the control data bag in the first buffer queue, cpu busy percentage can be reduced further.

Correspondingly, see Fig. 3, the embodiment of the present invention also provides a kind of cpu busy percentage control device, comprising:

Probe unit 301, for detecting the utilization factor of central processor CPU;

Judging unit 302, for judging whether the utilization factor of CPU is more than or equal to first threshold, and judge to send to the first buffer queue in grouping chip the minimum guaranteed rate suppressing the transmission rate of packet whether to be less than described first buffer queue, wherein, described first buffer queue is used for all control data bags that buffer memory sends to described CPU, and the suppression packet in described first buffer queue is dropped after going out team from described buffer queue;

Suppress unit 303, first threshold is more than or equal to for the utilization factor as CPU, and send to the first buffer queue in grouping chip the minimum guaranteed rate suppressing the transmission rate of packet to be less than described first buffer queue, then send to described first buffer queue and suppress packet; Wherein, the priority of the suppression packet in described first buffer queue is higher than the priority of the control data bag in described first buffer queue.

Below in conjunction with the cpu busy percentage control device in Fig. 3 and the cpu busy percentage control system framework in Fig. 1, describe the cpu busy percentage control method that the embodiment of the present invention provides in detail.See Fig. 4, be a kind of cpu busy percentage control device figure that the embodiment of the present invention provides.Probe unit 301 is had respectively, judging unit 302 and suppression unit 303 in coprocessor 102; The first buffer queue 401 is had in grouping chip 103.

First buffer queue 401, for the suppression packet that buffer memory suppresses unit 303 to send, and the control data bag that in system, other unit sends, wherein, suppress packet to be forwarded to suppress unit 303 or directly abandon suppression packet, control data bag is forwarded to CPU, wherein, the priority of the suppression packet in the first buffer queue is higher than control data bag, and the first buffer queue is order forwarding data bag respectively according to priority.

Found out by above cpu busy percentage control device, when the first buffer queue transmission rate suppressing unit to improve to dividing into groups in chip, owing to suppressing packet priority higher than control data bag in the first buffer queue, therefore, suppress the unit suppression packet be sent in the first buffer queue can go to tie up control data bag, thus the quantity that the first buffer queue is forwarded to the control data bag of CPU is decreased, thus reduce the utilization factor of CPU, further, when tying up due to suppression packet, when the transmission rate of the control data bag in the first buffer queue is zero, farthest can reduce the utilization factor of CPU.

Below in conjunction with Fig. 4, the function of the unit in the step 201 in Fig. 2 ~ 204 and said apparatus is described in detail.

For step 202, judge whether the utilization factor of CPU is more than or equal to first threshold, can be performed by the judging unit 302 in coprocessor.Judging unit 302 receives the cpu busy percentage detected that probe unit sends, this cpu busy percentage and first threshold are compared, if this cpu busy percentage is more than or equal to first threshold, then illustrate that CPU current utilization is higher, therefore need to take measures to reduce cpu busy percentage.

For step 203, judge to send to the first buffer queue in grouping chip the minimum guaranteed rate suppressing the speed of packet whether to be less than the first buffer queue, can be performed by judging unit 302.Current suppression unit 303 is sent the minimum guaranteed rate suppressing the transmission rate of packet and the first buffer queue to allow and compares by judging unit 302, the transmission rate of packet is suppressed to be more than or equal to the minimum guaranteed rate of the first buffer queue if suppress unit 303 to send, then show it has been all suppress packet in the first buffer queue, now suppressing unit to send the transmission rate suppressing packet without the need to improving, only need continue the detection keeping cpu busy percentage; The transmission rate of packet is suppressed to be less than the minimum guaranteed rate of the first buffer queue if suppress unit 303 to send, then show that still also having control data to wrap in the first buffer queue is forwarded, then can improve by suppressing unit 303 transmission rate suppressing packet, increase the suppression data packet number in the first buffer queue, thus reduce the quantity controlling packet in the first buffer queue, the quantity of control data Packet forwarding to CPU is reduced by the first buffer queue, and then reduces the utilization factor of CPU.

For step 204, can be performed by suppression unit 303.Suppress unit 303 to perform according to the judged result of judging unit 302 and improve to the first buffer queue the transmission rate suppressing packet.The amplitude risen to not make cpu busy percentage or decline is excessive, the change within the specific limits that effective control cpu busy percentage is level and smooth, when improving suppression data package transmission velocity, improve according to setting step-length at every turn and send to described first buffer queue the transmission rate suppressing packet, and send suppression packet according to the transmission rate after improving to described first buffer queue, specifically comprise the following steps:

Steps A: the utilization factor of detection CPU;

Step B: if the utilization factor of described CPU is less than first threshold, then proceed to step C;

Step C: judge to send to described first buffer queue the minimum guaranteed rate suppressing the transmission rate of packet whether to be greater than described first buffer queue, if so, then proceed to steps A, otherwise proceed to step D;

Step D: improve according to setting step-length and send to described first buffer queue the transmission rate suppressing packet, and proceed to steps A.

Correspondingly, suppress unit 303 when sending suppression packet to the first buffer queue, improve according to setting step-length at every turn and send to described first buffer queue the transmission rate suppressing packet, and send suppression packet according to the transmission rate after improving to described first buffer queue, specifically comprise the following steps:

Steps A: the utilization factor of detection CPU;

The step-length of setting can be send in the unit interval to suppress the quantity of packet to increase K, and the quantity of K can be determined according to practical application, and to this, the embodiment of the present invention is not specifically limited this.

In addition, according to the cpu busy percentage control method of step 201 ~ 204, when cpu busy percentage is higher, can sends to the first buffer queue and suppress packet, thus realize the object reducing cpu busy percentage.But within if cpu busy percentage has been controlled in a less scope, such as cpu busy percentage is now less than Second Threshold, described Second Threshold is less than or equal to first threshold, at this moment, can reduce cpu busy percentage, specifically, if in step 202, after judgement show that cpu busy percentage is less than first threshold, judge whether cpu busy percentage is less than Second Threshold further, if the utilization factor of CPU is less than Second Threshold, then reduces and send to the first buffer queue the transmission rate suppressing packet.Above-mentioned flow process specifically comprises the following steps:

Steps A: the utilization factor of detection CPU;

Step B: if the utilization factor of CPU is less than described Second Threshold, then proceed to step C;

Step C: judge to send to the first buffer queue to suppress the transmission rate of packet whether to be greater than zero, if so, then proceed to step D, otherwise proceed to A;

Step D: reduce according to setting step-length and send to the first buffer queue the transmission rate suppressing packet, and proceed to steps A.

Correspondingly, the judging unit 302 of cpu busy percentage control device can judge whether cpu busy percentage is less than Second Threshold; Suppress unit 303 also when the utilization factor of CPU is less than Second Threshold, can reduces and send to the first buffer queue the transmission rate suppressing packet, specifically comprise the following steps:

Steps A: the utilization factor of detection CPU;

The above embodiment of the present invention, can have multiple to the mode that the utilization factor of CPU detects, and provides a kind of preferred implementation below.

Preferably, in the embodiment of the present invention, the utilization factor of CPU can record by the following method: send probe data packet to CPU, and receives the described probe data packet that CPU returns; According to the transmitting time of probe data packet and the difference of time of reception, show that detection data wraps in the residence time in described CPU; The residence time wrapped in CPU according to detection data inquires about the corresponding relation of residence time and the cpu busy percentage pre-set, and obtains the utilization factor of CPU.

Specifically, detection cpu busy percentage, be divided into starting stage and two stages of normal detection phase, mainly coprocessor and CPU have worked in coordination with, and grouping chip only plays the effect of forwarding data bag.Starting stage, the ability of the transceiving data bag of other port of CPU shielding except coprocessor access interface, makes the working load of CPU at reduced levels; The normal detection phase, CPU normally works, process all types of task, now, the priority of detection mission in CPU in all tasks is minimum, this is that other tasks count taking of CPU by the residence time that detection data is wrapped in CPU, are observed the execution time of every other task with this by the residence time of probe data packet in order to ensure other tasks by priority processing in CPU.

What Fig. 5 was exemplary illustrates that the embodiment of the present invention detects the schematic diagram of cpu busy percentage starting stage.Coprocessor is responsible for sending probe data packet to CPU, as sent P probe data packet continuously to CPU in 1S, wraps the transmitting time stamp stamping each packet at each detection data.Detection mission is there is in CPU, after receiving probe data packet, current cpu busy percentage is put into probe data packet, P probe data packet can obtain the cpu busy percentage of P time point, then probe data packet is forwarded, send it back coprocessor by grouping chip.After coprocessor receives P probe data packet, wrap at each detection data and stamp time of reception stamp respectively, resolve probe data packet, the time of reception stamp of each probe data packet deducts corresponding transmitting time stamp and obtains this detection data and wrap in residence time in CPU, thus, again according to the cpu busy percentage in probe data packet, obtain the corresponding relation t of cpu busy percentage and residence time, as shown in Figure 6.As, when cpu busy percentage is 10%, residence time is 10 μ s, and when cpu busy percentage is 40%, residence time is 40 μ s, and when cpu busy percentage is 60%, residence time is 60 μ s, obtains the empirical relationship between cpu busy percentage and residence time T thus wherein, M is cpu busy percentage, and T is the residence time that detection data wraps in CPU, and 100 μ s are the coefficients drawn the detection cpu busy percentage starting stage.。Empirical relationship formula thus, when knowing residence time T, cpu busy percentage M can be drawn, or, if wish that the utilization factor M of CPU is no more than threshold value x (such as x is 70%), can obtain residence time T can not more than tx (i.e. 70 μ s).

The normal detection phase, coprocessor sends a probe data packet with the fixed cycle (as 1s) to CPU, and detection data wrap stamp transmitting time stamp, after CPU receives probe data packet, the pending queue such as in order probe data packet to be put into, wherein the priority of detection mission is minimum.Because other task need count taking of CPU by the residence time of probe data packet, if the priority of detection mission is higher, so probe data packet by priority processing, just can cannot observe the overall busy extent of CPU by residence time.In this stage, CPU does not need current cpu busy percentage to squeeze in probe data packet, only probe data packet need be beamed back coprocessor, prevent probe data packet from increasing extra work to CPU, increase the weight of the busy extent of CPU.Time of reception stamp stamped again by coprocessor after receiving probe data packet, by the residence time obtaining probe data packet that time of reception stamp and transmitting time stab, the residence time obtained according to the starting stage again and the corresponding relation t of cpu busy percentage, draw cpu busy percentage.Such as, according to the corresponding relation t of previous example, if residence time is 50 μ s, so cpu busy percentage is 50%.In addition, coprocessor need preset a maximum residence time, as 200 μ s.Because if cpu busy percentage is very high, probe data packet is just returned less than coprocessor for a long time, or cannot coprocessor be got back to, after exceeding this maximum residence time, coprocessor just thinks that this time detection cpu busy percentage is 100%, and starts to start detection next time.

In the process of detection cpu busy percentage, the transmission that detection data wraps between CPU and coprocessor need through grouping chip, the detection data priority wrapped in grouping chip is the highest, this is even grouped chip abandons to prevent from detection data from wrapping in staying the too much time because of the interference of other packet in grouping chip, thus coprocessor can not get detection data accurately wraps in residence time in CPU.And if probe data packet is grouped chip abandons, at coprocessor, is exactly that detection data wraps in by infinitely resident in CPU, thinks that the utilization factor of CPU reaches 100% by mistake.

Below in conjunction with Fig. 7, the cpu busy percentage control method provided the embodiment of the present invention is done and is explained in detail.Fig. 7 gives a kind of cpu busy percentage control flow chart that the embodiment of the present invention provides.

Wherein, the cpu busy percentage that probe unit detects represents with M, and the first threshold preset is M1, Second Threshold is M2, suppress data package transmission velocity V to represent, the minimum guaranteed rate of the first buffer queue is Vmax, suppresses unit 303 improve by setting step-length at every turn or reduce transmission rate.Wherein, M1 illustrates a higher cpu busy percentage, M2 illustrates a lower cpu busy percentage, when CPU current utilization is higher than M1, then improve and send the transmission rate of suppression packet to reduce cpu busy percentage to the first buffer queue, when CPU current utilization is lower than M2, then reduces and send the transmission rate of suppression packet to improve cpu busy percentage to the first buffer queue.

Step 701, suppresses data package transmission velocity to be initialized as V=0.

In the starting stage, suppressing packet owing to not sending to the first buffer queue, therefore suppressing the transmission rate of packet to be initialized as V=0 by sending to the first buffer queue.

Step 702, detection cpu busy percentage.

Probe unit 301 is utilized to detect the utilization factor M of CPU.When CPU is busier, if the detection data that probe unit is sent to CPU wraps in official hour do not return probe unit, then the cpu busy percentage that this detects is set to 100%, described official hour can be 100 μ s, or 200 μ s, occurrence can be determined on a case-by-case basis.

Step 703, judges whether cpu busy percentage M is more than or equal to M1.

Whether cpu busy percentage M is more than or equal to M1 to utilize judging unit 302 to judge, if cpu busy percentage is greater than M1, shows that current C PU utilization factor is higher, then forwards step 704 to, otherwise forward step 706 to.

Step 704, judges to send to the first buffer queue the minimum guaranteed rate suppressing the transmission rate V of packet whether to be more than or equal to the first buffer queue.

In this step, judging unit 302 judges to suppress unit 303 to send the minimum guaranteed rate suppressing the transmission rate V of packet whether to be more than or equal to the first buffer queue to the first buffer queue, if, then show to suppress unit 303 to suppress the transmission rate of packet to exceed the maximal value of the first buffer queue permission to the transmission of the first buffer queue, then improve transmission rate without the need to continuing again, therefore forward step 702 to, continue to keep detection cpu busy percentage; Otherwise, show can also continue to improve to send to the first buffer queue the transmission rate suppressing packet, therefore forward step 705 to.

Step 705, suppresses the transmission rate of packet to improve by setting step-length by sending when forward direction first buffer queue.

For ensureing that cpu busy percentage improves smoothly or reduces, suppressing unit 303 to send to the first buffer queue suppresses the rate variation of packet unsuitable excessive, to suppressing the transmission rate of packet can be set to increase the transmission that is suppressed packet in the unit interval in the present embodiment, in actual applications, can determine as the case may be.

Step 706, judges whether cpu busy percentage M is more than or equal to M2.

In this step, judging unit 302 judges whether cpu busy percentage M is more than or equal to M2, if so, then shows that current C PU utilization factor does not also lower completely, then forwards step 702 to, continues to keep detection cpu busy percentage, otherwise, then forward step 707 to.

Step 707, judges whether current suppression data package transmission velocity is greater than zero.

In step 706, judge to show that current C PU utilization factor is less than or equal to Second Threshold, therefore need to improve cpu busy percentage, the method improving cpu busy percentage is reduce to suppress unit 303 to send the transmission rate suppressing packet to the first buffer queue, and the first buffer queue thus can be made can to forward more control data bag to CPU.Before reducing the suppression data package transmission velocity suppressing unit, first need to judge, whether current suppression data package transmission velocity is greater than zero, if so, then forwards step 708 to, otherwise forwards step 702 to.

Step 708, suppresses the transmission rate of packet within the unit interval, suppress the quantity forwarded of packet to reduce one by sending when forward direction first buffer queue.

By describing above and can finding out, in the embodiment of the present invention, the speed entering CPU by controlling to enter control data bag reaches the effect reducing cpu busy percentage, wherein, first the utilization factor of central processor CPU is detected, if the utilization factor of CPU is more than or equal to first threshold, then judge to send to the first buffer queue in grouping chip the minimum guaranteed rate suppressing the transmission rate of packet whether to be less than the first buffer queue, if, then send to the first buffer queue and suppress packet, wherein, first buffer queue is used for all control data bags that buffer memory sends to described CPU, suppression packet in first buffer queue is dropped after going out team from described buffer queue, and first the priority of suppression packet in buffer queue higher than the priority of the control data bag in the first buffer queue, therefore improve and suppress Packet Generation can reduce the transmission rate of the control data bag in the first buffer queue in the first buffer queue, thus the speed achieved by controlling to enter the control data bag of CPU controls cpu busy percentage.

In above-mentioned steps 704, if judging unit 302 judges to draw that suppressing unit 303 to send to the first buffer queue suppresses the transmission rate V of packet to be less than the minimum guaranteed rate Vmax of the first buffer queue, then suppress unit within the unit interval, suppress the quantity forwarded of packet to increase by one, wherein, when suppressing the control data packet sending speed V1 sum in data package transmission velocity V and the first buffer queue to be less than the first minimum guaranteed rate of buffer queue, show that suppression packet in the first buffer queue and control data bag do not take the first buffer queue, therefore, when the transmission rate suppressing unit to improve to the first buffer queue transmission suppression packet, control data bag in first buffer queue can not be suppressed in the incipient stage, until improve when suppressing the transmission rate V of unit to bring up to make V+V1=Vmax, next, improve when suppressing the transmission rate of unit, just can produce the control data packet sending speed in the first buffer queue and suppress.

Embodiment two

In the embodiment of the present invention two, can on the basis of embodiment one, for determining to suppress data package transmission velocity and control data packet sending speed sum whether to equal the minimum guaranteed rate of the first buffer queue in the first buffer queue, can be continued to send measurement data bag in the first buffer queue by coprocessor, after measurement data bag is sent to the first buffer queue in grouping chip, coprocessor is forwarded to by grouping chip, the transmission rate of described measurement data bag equals the minimum guaranteed rate of the first buffer queue, and the priority that described measurement data wraps in the first buffer queue is minimum, namely according to priority suppression packet is followed successively by from high to low in the first buffer queue, control data bag, measurement data bag.

In the starting stage, when first buffer queue is empty, continue to send measurement data bag in the first buffer queue, the transmission rate sending measurement data bag equals the minimum guaranteed rate of the first buffer queue, therefore be all now measurement data bag in the first buffer queue, when there being control data bag to arrive the first buffer queue, the priority of packet is controlled higher than measurement data bag in first buffer queue, therefore part can be contracted for fixed output quotas raw the suppression to measurement data, when there being suppression packet to arrive the first buffer queue, owing to suppressing packet priority the highest, therefore measurement data bag can first be suppressed, when measurement data bag is suppressed to zero, packet is suppressed to enter the first buffer queue if also have, then now can disinthibite control data bag further.

Therefore, coprocessor can according to the quantity of the measurement data bag quantity being sent to the first buffer queue in the unit interval with the measurement data bag received, the transmission rate of the measurement data bag in the first buffer queue can be drawn, and then learn whether suppression data package transmission velocity in the first buffer queue and control data packet sending speed sum equal the minimum guaranteed rate of the first buffer queue, because the transmission rate V2 of the measurement data bag in the first buffer queue, transmission rate V1 and the transmission rate V suppressing packet of control data bag, three's sum equals the minimum guaranteed rate Vmax of the first buffer queue all the time, i.e. V2+V1+V=Vmax, as V2>0, then V1+V must be less than Vmax.

Therefore, detecting after cpu busy percentage is more than or equal to first threshold, can go by following methods the utilization factor determining how to reduce CPU, comprise:

According to being sent to the quantity of measurement data bag of described first buffer queue and the quantity of measurement data bag that returns from described first buffer queue, determine the quantity of the measurement data bag in described first buffer queue; Wherein, the priority of the measurement data bag in described first buffer queue is lower than the priority of the control data bag in this buffer queue, described measurement data bag is sent to described first buffer queue by coprocessor and after going out team, is forwarded to described coprocessor, and the transmission rate of described measurement data bag is the minimum guaranteed rate of described first buffer queue;

If the quantity of the measurement data bag in described first buffer queue is greater than zero, then determine to send to described first buffer queue the transmission rate suppressing packet, and send suppression packet according to the transmission rate of the suppression packet determined to described first buffer queue, wherein, the transmission rate determined equals the quantity of the measurement data bag being sent to described first buffer queue in the unit interval and the difference of the quantity of the measurement data bag returned from described first buffer queue; Or

If the quantity of the measurement data bag in described first buffer queue equals zero, then send to described first buffer queue the transmission rate suppressing packet according to the raising of setting step-length, and send suppression packet according to the transmission rate after improving to described first buffer queue.

Below in conjunction with Fig. 8, the cpu busy percentage control method that inventive embodiments two provides is described in detail.

See Fig. 8, it is the another kind of cpu busy percentage control flow chart that the embodiment of the present invention provides.Wherein, the cpu busy percentage that probe unit detects represents with M, the first threshold preset is M1, Second Threshold is M2, data package transmission velocity V is suppressed to represent, the minimum guaranteed rate of the first buffer queue is Vmax, suppresses unit 303 within the unit interval, suppress the quantity forwarded of packet to increase by one.Wherein, first threshold illustrates a higher cpu busy percentage, Second Threshold illustrates a lower cpu busy percentage, when CPU current utilization is higher than first threshold, then need to send the transmission rate of suppression packet to reduce cpu busy percentage to improving to the first buffer queue, when CPU current utilization is lower than Second Threshold, then need to reduce to send to the first buffer queue to suppress the transmission rate of packet to improve cpu busy percentage.

Similar for a kind of step 701 of step 801, step 802 and embodiment, step 702, and step 808 ~ 810 are similar with step 706 ~ 708 of embodiment one, again repeat no more.Below in conjunction with Figure 10, step 803 ~ 807 of the cpu busy percentage control method that the embodiment of the present invention two provides are elaborated.

Step 803, judges whether cpu busy percentage M is more than or equal to first threshold M1.

Judging unit 302 judges whether cpu busy percentage M is more than or equal to first threshold, if cpu busy percentage is greater than first threshold, shows that current C PU utilization factor is higher, then forwards step 804 to, otherwise forward step 808 to.

Step 804, judges whether the transmission rate of the measurement data bag in the first buffer queue is greater than zero.

The transmission rate V2 of the measurement data bag in the first buffer queue that subelement suppresses unit to measure is determined in judging unit 302 reception, judges whether V2 is greater than 0, if be greater than 0, then forwards step 805 to, otherwise forward step 806 to.

Step 805, arranges and sends to the first buffer queue the transmission rate suppressing the transmission rate of packet to equal the measurement data bag in the first buffer queue.

When measuring the measurement data packet sending speed in the first buffer queue and being greater than zero, then arrange and send to the first buffer queue the transmission rate suppressing the transmission rate of packet to equal the measurement data bag in the first buffer queue, can first the measurement data bag of the first buffer queue be suppressed to be zero fast like this, and then the control data bag that disinthibites, be conducive to improving the efficiency reducing cpu busy percentage.

Step 806, judges whether the transmission rate of the suppression packet in the first buffer queue is greater than the minimum guaranteed rate of the first buffer queue.

When the measurement data bag in the first buffer queue is zero, now improve the transmission rate suppressing packet in the first buffer queue, then can the transmission rate of inhibitory control packet, thus reduce the utilization factor of CPU.Before this, judge to send to the first buffer queue the minimum guaranteed rate suppressing the transmission rate V of packet whether to be more than or equal to the first buffer queue by step 806, if, then show to suppress subelement to suppress the transmission rate of packet to exceed the maximal value of the first buffer queue permission to the transmission of the first buffer queue, then improve transmission rate without the need to continuing again, therefore forward step 802 to, continue to keep detection cpu busy percentage; Otherwise, show can also continue to improve to send to the first buffer queue the transmission rate suppressing packet, therefore forward step 807 to.

Step 807, suppresses packet within the unit interval, suppress the quantity forwarded of packet to increase by one by sending when forward direction first buffer queue.

Correspondingly, see Fig. 9, be a kind of cpu busy percentage control device that the embodiment of the present invention provides, comprise with lower unit:

Probe unit 301, judging unit 302, suppresses unit 303; Wherein suppress unit 303 also to comprise determine subelement 904 and suppress subelement 905.

Determining subelement 904, for according to being sent to the quantity of measurement data bag of described first buffer queue and the quantity of measurement data bag that returns from described first buffer queue, determining the quantity of the measurement data bag in described first buffer queue; Wherein, the priority of the measurement data bag in described first buffer queue is lower than the priority of the control data bag in this buffer queue, described measurement data bag is sent to described first buffer queue by coprocessor and after going out team, is forwarded to described coprocessor, and the transmission rate of described measurement data bag is the minimum guaranteed rate of described first buffer queue;

Suppress subelement 905, when quantity for measurement data bag in described first buffer queue is greater than zero, the difference of the quantity of the measurement data bag that the measurement data bag quantity suppressing the transmission rate of packet to be set to be sent to described first buffer queue in the unit interval is forwarded with described first buffer queue received, and send suppression packet according to the transmission rate of the suppression packet determined to described first buffer queue; Wherein, the measurement data bag quantity being sent to described first buffer queue in the described unit interval is identical with the minimum guaranteed rate of described first buffer queue, in described first buffer queue, the priority of packet is followed successively by suppression packet from high to low, control data bag, measurement data bag; Or

When in described first buffer queue, the quantity of measurement data bag equals zero, send to described first buffer queue the transmission rate suppressing packet according to the raising of setting step-length, and send suppression packet according to the transmission rate after improving to described first buffer queue.

Ginseng is by Figure 10, give a kind of installation drawing detecting cpu busy percentage, it is on the basis of Fig. 4, also add in suppression unit and determine subelement 904 and suppress subelement 905, whether described measuring unit is greater than zero for the transmission rate measuring the measurement data bag in the first buffer queue, if be greater than zero, then show that the transmission rate sum of the suppression data package transmission velocity in the first buffer queue and the control data bag in the first buffer queue is less than the minimum guaranteed rate of the first buffer queue.

In the embodiment of the present invention, the speed entering CPU by controlling to enter control data bag reaches the effect reducing cpu busy percentage, wherein, first the utilization factor of central processor CPU is detected, if the utilization factor of CPU is more than or equal to first threshold, then judge whether the transmission rate of the measurement data report in the first buffer queue is greater than zero, if be greater than zero, then will send the transmission rate suppressing the transmission rate of packet to be set to the measurement data bag in the first buffer queue to the first buffer queue, if equal zero, then judge to send to the first buffer queue in grouping chip the minimum guaranteed rate suppressing the transmission rate of packet whether to be less than the first buffer queue, if, then send to the first buffer queue and suppress packet, wherein, first buffer queue is used for all control data bags that buffer memory sends to described CPU, suppression packet in first buffer queue is dropped after going out team from described buffer queue, and first the priority of suppression packet in buffer queue higher than the priority of the control data bag in the first buffer queue, therefore improve and suppress Packet Generation can reduce the transmission rate of the control data bag in the first buffer queue in the first buffer queue, thus the speed achieved by controlling to enter the control data bag of CPU controls cpu busy percentage.

Embodiment three

In another embodiment, in grouping chip, first the control data bag of every kind can enter corresponding control data bag buffer queue and wait for the process of grouping chip after entering the chip that divides into groups.A control data bag buffer queue is used for other control data bag of buffer memory same class.Control data bag buffer queue can be the buffer queue of priority mechanism, and the data that the packet that namely priority is high is low prior to priority contract out team.

Further, also can for the control data package definition CIR (CommittedInformationRate of every kind, guarantee information speed or be committed information rate), wherein, the value of the CIR of the control data bag of a kind is no more than the acceptable maximum rate of CPU.The CIR of different classes of control data bag can be set as required, such as, determine the CIR of this classification control data bag according to the CPU holding time of the agreement of every kind, preferably, the CIR of the control data bag that priority is high is greater than the CIR of the low control data bag of priority.

Based on the structure shown in Fig. 1, the cpu busy percentage control program that the embodiment of the present invention provides also is worked in coordination with grouping chip primarily of coprocessor and is realized.

Figure 11 shows the schematic diagram of the cpu busy percentage control flow that the embodiment of the present invention provides, and this flow process can realize in protocol processor side.As shown in the figure, this flow process can comprise:

Step 1101: the utilization factor of detection CPU;

Step 1102: judge whether the utilization factor of CPU is more than or equal to first threshold, if so, then proceeds to step 1203; Otherwise, proceed to step 1201;

Wherein, first threshold is used for weighing the degree of utilization factor of CPU, if the utilization factor of the CPU detected in step 1101 is more than or equal to this threshold value, then shows that the utilization factor of current C PU is higher, needs to control the quantity of the control data bag entering CPU.The value of first threshold can according to the performance of CPU or as required etc. many factors set, such as this first threshold can value be 80%.

Step 1103: determine the control data bag buffer queue needing enlargement discharge to suppress according to the priority of the control data bag buffer queue in grouping chip, and improve the speed sending suppression packet to the control data bag buffer queue needing enlargement discharge to suppress.

Wherein, grouping chip comprises N number of control data bag buffer queue, N be greater than 1 integer, the priority of the suppression packet in a control data bag buffer queue is higher than the priority of the control data bag in this control data bag buffer queue, suppression packet in a control data bag buffer queue is dropped after going out team from the control data bag buffer queue at place, and the control data bag in a control data bag buffer queue is forwarded to CPU.

Specifically, in step 1103, according to the priority of control data bag order from low to high, the control data bag buffer queue needing enlargement discharge to suppress can be determined.Like this, preferentially can suppress the transmission rate of the control data bag of low priority, thus while reduction cpu busy percentage, ensure the transmission of the control data bag of high priority as far as possible, and then ensure important affairs priority processing.

Further, according to the priority of control data bag from low to high, from the control data bag buffer queue that priority is minimum, the speed sending and suppress packet can be increased, until the transmission rate of control data bag minimum for priority suppressed to be zero.If now cpu busy percentage is still greater than first threshold, then increases and send to priority time low control data bag buffer queue the speed suppressing packet, until the transmission rate of secondary for priority low control data bag is suppressed to be zero.By that analogy, until the transmission rate of control data bag the highest for priority is suppressed to be zero.

Preferably, in order to ensure the process of CPU to affairs, the processing stage that in step 1103, paired domination number can being divided into two according to the process of inhibition of bag: the processing stage of first and second processing stage.The processing stage of first, fundamental purpose is the control data bag being greater than minimum guaranteed rate for transmission rate, its transmission rate is reduced to this minimum guaranteed rate, on basis completing first processing stage, if the utilization factor of CPU is not still reduced to the degree of expection, such as lower than first threshold, then the processing stage of entering second.The fundamental purpose processing stage of second is the control data bag equaling minimum guaranteed rate for transmission rate, and its transmission rate is reduced to zero.

In first of the process of inhibition of control data bag processing stage, the control data bag buffer queue of minimum guaranteed rate can be greater than for control data packet sending speed, according to control data packet priority order from low to high, send to these buffer queues and suppress packet, the transmission rate of the control data bag in these buffer queues is made to be reduced to minimum guaranteed rate, and when the utilization factor of CPU is reduced to expected degree (such as first threshold) or has all processed for the control data bag buffer queue that all control data packet sending speeds are greater than minimum guaranteed rate, terminate this first processing stage.

The processing stage that Figure 12 schematically illustrating first of a kind of process of inhibition of control data bag and second processing stage process flow diagram.

For convenience, send the control data packet priority order from low to high of institute's buffer memory in buffer queue according to control data bag, N number of control data bag buffer queue is described as the first buffer queue to N buffer queue.

As shown in figure 12, in step 1103 control data bag process of inhibition first processing stage can comprise the following steps:

Step 1201: i is set to 1;

Step 1202: judge that the transmission rate of the control data bag in the i-th buffer queue is whether higher than the minimum guaranteed rate of this control data bag, if so, then proceeds to step 1203, otherwise proceeds to step 1205;

Step 1203: send to the i-th buffer queue and suppress packet, the difference that the minimum guaranteed rate that the transmission rate sending the control data bag suppressing the speed of packet to equal in the i-th buffer queue to the i-th buffer queue deducts this control data bag obtains;

Step 1204: the utilization factor of detection CPU, if the utilization factor of CPU is more than or equal to first threshold, then proceeds to step 1205, otherwise the flow process processing stage of terminating first of this process of inhibition;

Step 1205: i is increased progressively 1;

Step 1206: if i >=1, then proceed to step 1202, otherwise, terminate the flow process processing stage of first of this process of inhibition, the processing stage of entering second of process of inhibition.

Can be found out by above-mentioned flow process, according to priority order from low to high, first the transmission rate of low priority control data bag is suppressed, the speed of the control data bag of this low priority is suppressed to the minimum guaranteed rate of this control data bag, then the utilization factor of CPU is detected, if now cpu busy percentage is still higher, then continue to suppress the transmission rate of the control data bag of higher priority, so repeat above step, until all transmission rates are all suppressed to corresponding minimum guaranteed rate higher than the transmission rate of the control data bag of minimum guaranteed rate.

After first stage of process of inhibition completes, if the utilization factor of CPU is still higher than first threshold, then continue the subordinate phase performing process of inhibition.

As shown in figure 12, control data bag process of inhibition second processing stage can comprise the following steps:

Step 1207: i is set to 1;

Step 1208: increase and send the speed suppressing packet, to make the transmission rate of the control data bag in the i-th buffer queue for zero to the i-th buffer queue;

Step 1209: the utilization factor of detection CPU, if the utilization factor of CPU is more than or equal to first threshold, then proceed to step 1210, otherwise the processing stage of terminating second of this process of inhibition, follow-up continuation detects the utilization factor of CPU, and triggers corresponding flow process according to the utilization factor of the CPU detected;

Step 1210: i is increased progressively 1;

Step 1211: if i≤N, then proceed to step 1208, otherwise the processing stage of terminating second of this process of inhibition, follow-up continuation detects the utilization factor of CPU, and triggers corresponding flow process according to the utilization factor of the CPU detected.

Further, the speed of all control data bags all suppressed to be after zero, the utilization factor of CPU is still greater than first threshold, then can send and be used to indicate the high alarm instruction of cpu busy percentage.

Can be found out by above-mentioned flow process, when the transmission rate of all control data bags is all suppressed to minimum guaranteed rate, the utilization factor of CPU is still greater than first threshold, then unwrap the beginning from the control data that priority is minimum, the transmission rate of the control data bag of low priority is down to zero, then the utilization factor of CPU is detected, if now cpu busy percentage is still greater than first threshold, then according to priority order from low to high, the transmission rate of the control data bag of higher priority is reduced to zero, until the transmission rate of all control data bags is reduced to zero.

The processing stage of by above-mentioned process of inhibition two, first control data packet rate is suppressed to minimum guaranteed rate, instead of directly control data packet rate is curbed completely, in the quick impact reducing protocol data-flow and produce CPU, while reducing cpu busy percentage, the process of CPU to affairs can be ensured as much as possible again.

As previously mentioned, after completing second of process of inhibition processing stage, can continue to detect the utilization factor of CPU, and trigger corresponding flow process according to the utilization factor of the CPU detected.Such as, when the utilization factor of the CPU detected is lower, process of expansion can be triggered to improve the transmission rate of control data bag.

Specifically, if the utilization factor of CPU is less than Second Threshold, then can determine according to the priority of control data bag the control data bag buffer queue needing the suppression of reduction flow, and reduce the speed to needing to reduce the control data bag buffer queue transmission suppression packet that flow suppresses.Wherein, Second Threshold is less than or equal to first threshold, the value of Second Threshold can according to the performance of CPU or as required etc. many factors set, such as this Second Threshold can value be 40%.

Pass through said method, when Second Threshold is less than first threshold, can the utilization factor of CPU be controlled between Second Threshold to first threshold, make the utilization factor of CPU neither too high low only, avoid the too much adjustment of cpu busy percentage, also ensure that processing controls packet as much as possible.

Preferably, according to the priority of control data bag order from high to low, the control data bag buffer queue needing to reduce flow suppression can be determined.Like this, preferentially to the transmission rate derepression of the control data bag of high priority, can ensure that the control data bag of high priority is sent to CPU, to ensure the process of high priority affairs as far as possible.

The processing stage that process of expansion can being divided into two equally: the processing stage of first and second processing stage.The processing stage of first, fundamental purpose is according to priority order from high to low, and remove the suppression of paired domination number according to the transmission rate of bag according to the step-length of setting, on basis completing first processing stage, if the utilization factor of CPI does not still bring up to the degree of expection, such as Second Threshold, then the processing stage of entering second; The fundamental purpose processing stage of second is according to priority order from high to low, to the control data bag of a kind gradually derepression until the suppression of derepression transmission rate completely, until the utilization factor of CPU is higher than Second Threshold.

The processing stage that Figure 13 schematically illustrating first of a kind of process of expansion of control data bag and second processing stage process flow diagram.

As shown in figure 13, in control data bag process of expansion first processing stage can comprise the following steps:

Step 1301: i is set to N;

Step 1302: judge that the transmission rate of the control data bag in the i-th buffer queue is whether lower than the minimum guaranteed rate of this control data bag, if so, then proceeds to step 1303, otherwise proceeds to step 1305;

Step 1303: reduce according to setting step-length and send to the i-th buffer queue the speed suppressing packet, proceed to step 1304; Wherein, the value of this step-length can pre-set as required, if value is less, then adjust granularity less, otherwise it is larger then to adjust granularity.

Step 1304: the utilization factor of detection CPU, if the utilization factor of CPU is less than or equal to Second Threshold, then proceeds to step 1305, otherwise, terminate the flow process processing stage of first of this process of expansion;

Step 1305: i is successively decreased 1;

Step 1306: if i≤N, then proceed to step 1302, otherwise, terminate the flow process processing stage of first of this process of expansion, the processing stage of entering second of process of expansion.

Further, in above-mentioned process of expansion, if the utilization factor of detection CPU is higher than Second Threshold and lower than first threshold, then can continue to keep the transmission rate of current suppression packet constant.

Can be found out by above-mentioned flow process, according to priority order from high to low, traversal control data bag buffer queue, if the transmission rate of the control data bag in the control data bag buffer queue traversed current is lower than minimum guaranteed rate, then reduce and send to this control data bag buffer queue the speed suppressing packet, thus the transmission rate of the control data bag in this control data bag buffer queue is promoted, and continue the next control data bag buffer queue of traversal, until the utilization factor of CPU reaches Second Threshold stop ergodic process.

Process of expansion first processing stage complete after, if the utilization factor of CPU is still lower than Second Threshold, then continue perform process of expansion second processing stage.

As shown in figure 13, control data bag process of expansion second processing stage can comprise the following steps:

Step 1307: i is set to N;

Step 1308: judge to send to the i-th buffer queue to suppress the transmission rate of packet whether to be greater than zero, if so, then proceed to step 1309, otherwise proceed to step 1311;

Step 1309: reduce according to setting step-length and send to the i-th buffer queue the speed suppressing packet;

Step 1310: the utilization factor of detection CPU, if the utilization factor of CPU is less than or equal to Second Threshold, then proceed to step 1311, otherwise the processing stage of terminating second of this process of expansion, follow-up continuation detects the utilization factor of CPU, and triggers corresponding flow process according to the utilization factor of the CPU detected;

Step 1311: i is successively decreased 1;

Step 1312: if i >=1, then proceed to step 1308, otherwise the processing stage of terminating second of this process of expansion, follow-up continuation detects the utilization factor of CPU, and triggers corresponding flow process according to the utilization factor of the CPU detected.

By above process of expansion second processing stage flow process can find out, if after through first of process of expansion processing stage, the utilization factor of CPU does not also rise to Second Threshold, then according to priority order from high to low, traversal control data bag buffer queue, transmission rate to the suppression packet in the current control data bag buffer queue traversed is reduced gradually according to setting step-length, until the utilization factor of CPU reaches Second Threshold, otherwise, travel through next control data bag buffer queue, and process according to the same manner, until the utilization factor of CPU reaches Second Threshold or has traveled through all control data bag buffer queue positions.

The processing stage of by above-mentioned process of expansion two, first according to priority order from high to low, control data packet rate is promoted, instead of directly by the complete derepression of a kind of control data packet rate, thus ensure that CPU is to the process of all types of affairs, and further when the utilization factor of CPU is still in reduced levels, can according to priority order from high to low, after a kind of complete derepression of transmission rate of control data bag, again to the transmission rate derepression of the control data bag of next priority, thus ensure the process of high priority affairs as far as possible.Like this, when ensureing that the utilization factor of CPU is not too high, CPU can be made full use of again, to ensure the process of CPU to affairs as much as possible.

The suppression stage of above-mentioned control data bag and the expansionary phase of control data bag, all need the transmission rate determining control data bag, the embodiment of the present invention is according to the CIR of a control data bag and send the speed suppressing packet to corresponding buffer queue, calculates the transmission rate of control data bag in a control data bag buffer queue.Specifically, according to aforementioned description, in same control data bag buffer queue, packet paired domination number is suppressed to tie up according to bag, if the guarantee information speed of the i-th buffer queue is CIR _i, then suppress the transmission rate of the transmission rate of packet and control data bag to there is following relation:

Rf _i＝CIR _i-Df _i……………………………………………(1)

Wherein, Rf _ibe the transmission rate of the control data bag in the i-th buffer queue, CIR _ibe the guarantee information speed in the i-th buffer queue, Df _iit is the transmission rate of the suppression packet in the i-th buffer queue.

In another kind of preferred embodiment, in order to more accurately determine the transmission rate of control data bag more easily, measurement data bag can be sent to grouping chip by coprocessor, in same buffer queue, the priority of measurement data bag is lower than the priority of control data bag, and the destination address of measurement data bag is the address of coprocessor, coprocessor draws the speed of control data bag by the transmission rate of measurement data bag and receiving velocity.Like this, the mode refluxed by measurement data bag measures the transmission rate of control data bag, and this mode configures simply, measure simple, without the need to the register by reading grouping chip, by the mode of external chip internal loopback, the measurement of paired domination number according to packet sending speed namely can be completed.

Particularly, limiting measurement data transmission rate is the CIR of buffer queue, and the guarantee information speed in the i-th buffer queue is CIR _i, then there is following relation in the transmission rate of measurement data bag and the transmission rate of control data bag:

Rf _i＝CIR _i-Hf _i……………………………………………(2)

Wherein, Rf _ibe the transmission rate of the control data bag in the i-th buffer queue, CIR _ibe the guarantee information speed in the i-th buffer queue, Hf _ibe the receiving velocity of the measurement data bag in the i-th buffer queue, the quantity of the measurement data bag backflow that namely in the unit interval, coprocessor receives.Special, work as Rf _i>=CIR _itime, the speed that measurement data bag is back to coprocessor is 0, is namely taken by control packet completely in the i-th buffer queue.

After coprocessor sends suppression packet to grouping chip, to control data bag be there is simultaneously, suppress packet and measurement data bag in same buffer queue, owing to suppressing the priority of priority higher than control data bag of packet, the priority of control data bag is again higher than the priority of measurement data bag, then the transmission rate of the control data bag in the i-th buffer queue is:

Rf _i＝CIR _i-Df _i-Hf _i……………………………………………(3)

Wherein, Rf _ibe the transmission rate of the control data bag in the i-th buffer queue, CIR _ibe the guarantee information speed in the i-th buffer queue, Df _ibe the transmission rate of the suppression packet in the i-th buffer queue, Hf _iit is the receiving velocity of the measurement data bag in the i-th buffer queue.

In the above embodiment of the present invention, can have multiple to the mode that the utilization factor of CPU detects, provide a kind of preferred implementation below.

The cpu busy percentage control strategy that the embodiment of the present invention provides, when cpu busy percentage is prescribed a time limit higher than the upper of expection, increase to send in buffer queue and suppress packet, the utilization factor of CPU is declined, when cpu busy percentage is prescribed a time limit lower than the lower of expection, reduce in buffer queue and suppress packet, the utilization factor of CPU is raised, makes the timely process of guarantee affairs.This is achieved in the following ways, grouping chip provides ACL (Access Control List (ACL), AccessControlList), classification can be searched to the control data bag received, put it in corresponding control data bag buffer queue, each buffer queue can limit packet rate wherein.From effect, can regard that grouping chip makes the control data bag of every type flow through a speed limit bucket as, as shown in figure 14.After control data bag enters grouping chip, ACL makes dissimilar control data bag respectively by corresponding speed limit keg, is CIR to the maximum by the speed of the packet of i-th speed limit keg _i, namely each speed limit keg has a maximum flow.In speed limit bucket, the data stream of high priority can tie up the data stream of low priority, and data stream is here the total amount by the packet of speed limit bucket in certain hour.Coprocessor in the embodiment of the present invention, for dissimilar control data bag, sends the suppression packet of different rates, wherein suppresses the priority of packet higher than the priority of control data bag to grouping chip.Grouping chip makes suppression packet flow into the speed limit keg at corresponding control data bag place, owing to suppressing the priority ratio of data stream higher, suppresses data stream can tie up protocol data-flow, thus reaches the object suppressing protocol data-flow.

Further, arranging on the basis of speed limit keg to the control data bag of every type, also a speed limit drum can be set to all control data bags entering CPU, namely when all types of control data bag respectively from respective keg out after, it is made all to flow in speed limit drum, as shown in figure 15.This considers when cpu busy percentage is more than the 3rd threshold value (the 3rd threshold value is greater than first threshold), can preferentially use speed limit drum to be lowered by the control data packet rate entering CPU.Principle and the keg of speed limit drum are similar, all that the data stream of data stream to low priority of high priority ties up, therefore, arrange the priority of priority higher than all control data bags of the suppression packet flowing into speed limit drum, the priority of measurement data bag is lower than the priority of all control data bags.In speed limit drum, measurement data bag is relevant with the utilization factor of the speed sum CPU suppressing packet, be indifferent to the speed of concrete control data bag, speed limit keg calculates respectively, speed limit keg carries out the Exact calculation of the speed of the control data bag of every type, and speed limit drum carries out the control that all control data bags enter the total speed of CPU.Speed limit drum is responsible for the utilization factor of CPU being reduced under the 3rd threshold value, and speed limit keg is responsible for the utilization factor of CPU to be reduced under first threshold.

In order to more clearly understand the present invention, with instantiation, above-mentioned flow process is described in detail below.Flow process described by this instantiation can be divided into initialization A, detection process B1 and B2, process of inhibition C and process of expansion D, as shown in figure 16.

Initialization A: to all parameter initializations.Particularly, process of inhibition and process of expansion are all initialized as 1, and namely representative performs from the first stage of process of inhibition or the first stage of process of expansion.Find_i is the priority lookup variable in suppression stage, if there is the control data bag of N number of type, the control data of each type is surrounded by a priority, as ARP (address resolution protocol, and APS (APS AddressResolutionProtocol), AutomaticProtectionSwitched) between, priority is different, the priority of ARP is 1, the priority of APS is 2, setting find_i is initialized as 1, represent that unwrapping the beginning from the suppression stage from the control data of the minimum type of priority searches measurement, namely the control data that priority is low wraps in the suppression stage and can first be suppressed.Add_i is the priority lookup variable of expansionary phase, is initialized as N, represents that the expansionary phase unwraps the beginning from the control data that priority is the highest.Long-term busy alarm instruction is initialized as 0, represents that CPU is current and be not in long-term busy state.After executing initialization, perform detection process B1.

Step B1: detection cpu busy percentage.Particularly, can learn according to description before, detection data can be utilized to wrap in residence time T and the experimental formula in CPU and draw cpu busy percentage M, therefore only need measure the residence time T of probe data packet.

Step B2: by T and tM ₁, tM ₂compare, if T>tM ₁, then flow process C, i.e. process of inhibition is performed; If T<tM ₂, then flow process D, i.e. process of expansion is performed.

Process of inhibition specifically can be divided into following steps, and as shown in figure 17, wherein, step C3 ~ C9 is the process of inhibition first stage, and step C10 ~ C15 is process of inhibition subordinate phase:

Step C1: first by the initialization of variable one time of process of expansion, in order to transfer to, to perform process of expansion ready.Particularly, expansionary phase=1, add_i=N, represent when transferring process of expansion to from process of inhibition, first perform the first stage of process of expansion, and unwrap from the control data that priority is the highest and begin to perform.

Step C2: judge first stage or the subordinate phase of carrying out process of inhibition, if the first stage, then performs step C3; If subordinate phase, then perform step C10.

Step C3: be 0 by long-term busy alarm cue mark.Because what perform at present is the process of inhibition first stage, also has method the utilization factor of CPU to be lowered, so there is no necessity and carry out long-term busy alarm.

Step C4: the speed measuring the i-th two priority classes packet.Due in initialization procedure, find_i is initialized as 1, therefore in process of inhibition, unwraps begin to measure from the control data that priority is minimum.

Step C5: judge whether the speed of the i-th two priority classes packet is greater than the most low guaranteed bandwidth of this control data bag, if so, then performs step C6; If not, then step C7 is performed.

Step C6: suppress packet to the i-th two priority classes Packet Generation, is suppressed to corresponding most low guaranteed bandwidth by the speed of this control data bag.

Step C7:find_i adds 1, namely forwards the control data bag of next priority to.

Step C8: judge whether find_i is greater than N, if so, then performs step C9; If not, then step B1 is performed.

Step C9: the suppression stage is set to 2, find_i and is set to 1, then performs step B1.Specifically, previous step is judged as "Yes", shows the speed of the control data bag of all priority to be all suppressed to most low guaranteed bandwidth, if now the utilization factor of CPU is still greater than threshold value, then need the subordinate phase forwarding process of inhibition to, again suppress from lowest priority.Conversely, if previous step is judged as "No", shows to still have the speed of control data bag not to be suppressed to most low guaranteed bandwidth, the control data bag suppressing next priority can be continued.

Step C10: suppress packet to the i-th two priority classes Packet Generation, suppresses to be zero by the speed of this control data bag.

Step C11:find_i adds 1, namely forwards the control data bag of next priority to.

Step C12: judge whether find_i is greater than N, if so, then performs step C13; If not, then step B1 is performed.

Step C13: find_i is set to N, and long-term busy alarm instruction is added 1, then perform step C14.Specifically, when the speed of limit priority control data bag is suppressed to be after zero, long-term busy alarm instruction is carried out adding 1 operation, shows, by suppression above, there is no good effect, the utilization factor of CPU is still greater than threshold value M, be now the subordinate phase of process of inhibition, and the speed of all control data bags is suppressed to 0 all, is still in process of inhibition, illustrate that CPU is still very busy, need long-term busy alarm instruction to increase.

Step C14: judge that long-term busy alarm indicates whether to be greater than threshold value L, if so, then perform step C15, if not, then perform step B1, wherein L be greater than 0 integer.

Step C15: send long-term busy alarm, and forward step B1 to.

Thus, process of inhibition has been introduced complete, introduces process of expansion below, as shown in figure 18, can be divided into following steps, and wherein, step D3 ~ D8 is the process of expansion first stage, and step D9 ~ D13 is process of expansion subordinate phase.

Step D1: first by the initialization of variable one time of process of inhibition, in order to transfer to, to perform process of inhibition ready.Particularly, suppress stage=1, find_i=1, represent when transferring process of inhibition to from process of expansion, first perform the first stage of process of inhibition, and unwrap from the control data that priority is minimum and begin to perform.

Step D2: judge first stage or the subordinate phase of carrying out process of expansion, if the first stage, then performs step D3; If subordinate phase, then perform step D9.

Step D3: the speed measuring the i-th two priority classes packet.Due in initialization procedure, add_i is initialized as N, therefore in process of expansion, unwraps begin to measure from the control data that priority is the highest.

Step D4: judge whether the speed of the i-th two priority classes packet is greater than the most low guaranteed bandwidth of this control data bag, if so, then performs step D5; If not, then step D6 is performed.

Step D5: reduce and suppress packet to the i-th two priority classes Packet Generation one, then performs step B1.In effect, the speed of the control data bag of the i-th priority can be made to slowly rise to corresponding most low guaranteed bandwidth, the control data bag then changing a priority performs step below.

Step D6:add_i subtracts one, namely forwards the control data bag that next priority is lower to.

Step D7: judge whether add_i is less than 1, if so, then performs step D8; If not, then step B1 is performed.

Step D8: will be set to 2, add_i the expansionary phase and be set to N, then performs step B1.Specifically, previous step is judged as "Yes", shows to make the speed of the control data bag of all priority be raised to most low guaranteed bandwidth, if now the utilization factor of CPU is still less than threshold value, then need the subordinate phase forwarding process of expansion to, again reduce from limit priority and suppress.Conversely, if previous step is judged as "No", shows to still have the speed of control data bag not to be raised to most low guaranteed bandwidth, can continue to reduce the control data bag suppressing next priority.

Step D9: reduce and suppress packet to the i-th two priority classes Packet Generation one.

Step D10: judge whether the suppression packet to the i-th two priority classes Packet Generation reduces to zero, if so, then performs step D11; If not, then step B1 is performed.

Step D11:add_i subtracts 1, namely forwards the control data bag of next priority to.Specifically, the suppression packet of forward direction i-th two priority classes Packet Generation reduce to zero, namely packet is not suppressed to the i-th two priority classes Packet Generation, if now the utilization factor of CPU is still less than threshold value, show that CPU is still in idle condition, then reduce and send suppression packet to the control data bag that next priority is lower.

Step D12: judge whether add_i is less than 1, if so, then performs step D13; If not, then step B1 is performed.

Step D13: add_i is set to 1, then performs step B1.

The control method of the embodiment of the present invention; provide a kind of two step control strategies, and adopt different controlling extent for process of inhibition and process of expansion, the impact of too much packet to CPU can be reduced fast; the ability of slow increase CPU process load, provides good protection to CPU.Meanwhile, the priority of different agreement can be taken into account, make the control data bag of high priority by the first Recovery processing of rear suppression.

Based on identical technical conceive, the embodiment of the present invention also provides a kind of cpu busy percentage control device, Figure 19 shows the system schematic controlling cpu busy percentage, and cpu busy percentage control device, as shown in I in Figure 19, comprising: detecting module 1, judge module 2 and suppression module 3;

Described detecting module 1, for detecting the utilization factor of central processor CPU;

Described judge module 2, for judging whether the utilization factor of described CPU is more than or equal to first threshold;

Described suppression module 3, for when the utilization factor of described CPU is more than or equal to described first threshold, determine the control data bag buffer queue needing enlargement discharge to suppress according to the priority of control data bag, and improve the speed sending suppression packet to the described control data bag buffer queue needing enlargement discharge to suppress; Wherein, described grouping chip comprises N number of control data bag buffer queue, N be greater than 1 integer, the priority of the suppression packet in a control data bag buffer queue is higher than the priority of the control data bag in this buffer queue, suppression packet in a control data bag buffer queue is dropped after going out team from the control data bag buffer queue at place, and the control data bag in a control data bag buffer queue is forwarded to described CPU.

Preferably, described suppression module 3 for: according to the priority order from low to high of control data bag, determine the control data bag buffer queue needing enlargement discharge to suppress.

Preferably, according to the control data packet priority order from low to high of institute's buffer memory, described N number of control data bag buffer queue comprises the first buffer queue to N buffer queue;

Described suppression module 3 is specifically for performing following steps:

Step 1201: i is set to 1;

Step 1202: judge that the transmission rate of the control data bag in the i-th buffer queue is whether higher than the minimum guaranteed rate of described control data bag, if so, then proceeds to step 1203, otherwise proceeds to step 1205;

Step 1203: send to the i-th buffer queue and suppress packet, the difference that the minimum guaranteed rate that the transmission rate sending the control data bag suppressing the speed of packet to equal in the i-th buffer queue to the i-th buffer queue deducts described control data bag obtains;

Step 1204: the utilization factor detecting described CPU, if the utilization factor of described CPU is more than or equal to described first threshold, then proceeds to step 1205;

Step 1205: i is increased progressively 1;

Step 1206: if i≤N, then proceed to step 1202.

Preferably, described suppression module 3 is also for performing following steps:

In described step 1205, if i>N, then proceed to step 1207;

Step 1207: i is set to 1;

Step 1208: increase and send to the i-th buffer queue the speed suppressing packet, sends to the i-th buffer queue the transmission rate that the speed suppressing packet to increase equals the control data bag in the i-th buffer queue;

Step 1209: the utilization factor detecting described CPU, if the utilization factor of described CPU is more than or equal to described first threshold, then proceeds to step 210;

Step 1210: i is increased progressively 1;

Step 1211: if i≤N, then proceed to step 1208.

Preferably, described suppression module 3 also for:

In described step 1211, if i>N, then send and be used to indicate the high alarm instruction of cpu busy percentage.

Preferably, described suppression module 3 also for:

If the utilization factor of described CPU is less than Second Threshold, then determine the control data bag buffer queue needing to reduce flow suppression according to the priority of control data bag, and reduce to the described speed needing the control data bag buffer queue reducing flow suppression to send suppression packet; Wherein, described Second Threshold is less than or equal to described first threshold.

Preferably, described suppression module 3 also for: according to the priority order from high to low of control data bag, determine to need to reduce the control data bag buffer queue that flow suppresses.

Preferably, the priority of described N number of buffer queue is different each other, and according to priority order from low to high, described N number of buffer queue comprises the first buffer queue to N buffer queue;

Described suppression module 3 is specifically for performing following steps:

Step 1301: i is set to N;

Step 1302: judge that the transmission rate of the control data bag in the i-th buffer queue is whether lower than the minimum guaranteed rate of described control data bag, if so, then proceeds to step 1303, otherwise proceeds to step 1305;

Step 1303: reduce according to setting step-length and send to the i-th buffer queue the speed suppressing packet, proceed to step 1304;

Step 1304: the utilization factor detecting described CPU, if the utilization factor of described CPU is less than or equal to described Second Threshold, then proceeds to step 1302;

Step 1305: i is successively decreased 1;

Step 1306: if i >=1, then proceed to step 1302.

Preferably, described suppression module is also for performing following steps:

In described step 1306, if i<1, then proceed to step 1307;

Step 1307: i is set to N;

Step 1308: judge that the i-th buffer queue sends and suppress the speed of packet whether to be greater than zero, if so, then proceed to step 1309, otherwise proceed to step 1311;

Step 1309: reduce according to setting step-length and send suppression packet to the i-th buffer queue;

Step 1310: the utilization factor detecting described CPU, if the utilization factor of described CPU is less than or equal to described Second Threshold, then proceeds to step 1311;

Step 1311: i is successively decreased 1;

Step 1312: if i >=1, then proceed to step 1308.

Preferably, device also comprises measurement module 4, and as shown in II of Figure 20, measurement module 4 is for measuring the transmission rate of described control data bag, and the transmission rate of the control data bag in described i-th buffer queue is:

Rf _i＝CIR _i-Df _i-Hf _i

Wherein, Rf _ibe the transmission rate of the control data bag in the i-th buffer queue, CIR _ibe the guarantee information speed in the i-th buffer queue, Df _ibe the transmission rate of the suppression packet in the i-th buffer queue, Hf _iit is the receiving velocity of the measurement data bag in the i-th buffer queue; The priority of the measurement data bag in a buffer queue is lower than the priority of the control data bag in this buffer queue.

Preferably, detecting module 1 specifically for:

Send probe data packet to described CPU, and receive the described probe data packet that described CPU returns;

According to the transmitting time of described probe data packet and the difference of time of reception, show that described detection data wraps in the residence time in described CPU;

The residence time wrapped in described CPU according to described detection data inquires about the corresponding relation of residence time and the cpu busy percentage pre-set, and obtains the utilization factor of described CPU.

Embodiment four

In the above-described embodiments, embodiment one or example two use all types of control data bag of single buffer queue buffer memory, when cpu busy percentage is more than or equal to first threshold, coprocessor sends to this buffer queue the transmission rate suppressing packet by improving, thus reduce control data bag in this buffer queue and be sent to the speed of CPU, thus reduce cpu busy percentage; When cpu busy percentage is less than Second Threshold, coprocessor, by reducing the transmission rate of the transmission suppression packet to this buffer queue, thus improves control data bag in this buffer queue and is sent to the speed of CPU, thus improve cpu busy percentage.

Embodiment three uses N number of buffer queue, the control data bag of buffer memory N type respectively, when cpu busy percentage is more than or equal to first threshold, coprocessor improves the transmission rate sending suppression packet to N number of buffer memory team respectively according to the priority orders of control data bag in buffer queue, namely from the buffer queue that the control data bag that priority is minimum is corresponding, improve respectively and send to N number of buffer queue the transmission rate suppressing packet, thus reduce the transmission rate of the control data bag being sent to CPU in N number of buffer queue on the whole, thus reduce cpu busy percentage, when cpu busy percentage is less than Second Threshold, coprocessor sends to N number of buffer queue the transmission rate suppressing packet respectively to reducing according to the priority orders of control data bag in buffer queue, namely from the buffer queue that the control data bag that priority is the highest is corresponding, reduce respectively and send to N number of buffer queue the transmission rate suppressing data Ah Bai, thus improve the transmission rate that N number of buffer queue is sent to the control data bag of CPU on the whole, thus improve cpu busy percentage.

Above-mentioned two kinds of methods, individually implement, effectively can control cpu busy percentage.Wherein, single buffer queue method that embodiment one or embodiment two provide according to priority divides according to bag owing to not having paired domination number, therefore can than reducing more quickly or improving cpu busy percentage; And embodiment three is owing to considering the according to priority order buffer memory extremely N number of queue respectively of control data bag, when needing the transmission rate controlling control data bag, can considers to control successively according to priority orders, thus there is good actual application value.Therefore, the embodiment of the present invention four provides the method that another controls cpu busy percentage, combines, or embodiment two and embodiment four are combined by embodiment one and embodiment three, forms the method that cpu busy percentage as shown in figure 15 controls.

In embodiment four, such as, when cpu busy percentage is being greater than first threshold, when needing to reduce, first utilize the method for single buffer queue of embodiment one or embodiment two that cpu busy percentage is reduced to Second Threshold, and then cpu busy percentage continues to reduce by the method using embodiment three to provide, here, first threshold in the method that embodiment two provides just is equivalent to the Second Threshold in embodiment one or embodiment two, then the Second Threshold in embodiment three can be regarded as the 3rd threshold value in embodiment four.

For ease of understanding, below in conjunction with the relation between each threshold value that instantiation explains in embodiment four.Such as current C PU utilization factor is 90%, cpu busy percentage is reduced to 80% by the method that embodiment one or embodiment two can be used to provide, and then cpu busy percentage controls 70% by the method using embodiment two to provide, therefore 90% first threshold being equivalent to embodiment one or implementing in two here, 80% first threshold being equivalent to the Second Threshold in embodiment one or embodiment two and being equivalent in embodiment three, 70% is equivalent to the Second Threshold in embodiment three.In embodiment four, regard the 3rd threshold value as by 70%.

See Fig. 7, in step 706, obtain cpu busy percentage be more than or equal to Second Threshold M2 if judge, then use the method in embodiment three to reduce cpu busy percentage further, Second Threshold M2 is here equivalent to the first threshold of embodiment three.

By the above-mentioned mode by embodiment one method and embodiment three methods combining, or by the mode of embodiment two method and embodiment three methods combining, can realize first fast cpu busy percentage being reduced within certain threshold value by single buffer queue, and then the transmission rate of control data bag is reduced successively according to the priority orders of control data bag, realize controlling cpu busy percentage further, the method that this embodiment provides takes into account efficient control cpu busy percentage and actual application ability, therefore has good characteristic.

The present invention describes with reference to according to the process flow diagram of the method for the embodiment of the present invention, equipment (system) and computer program and/or block scheme.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block scheme and/or square frame and process flow diagram and/or block scheme and/or square frame.These computer program instructions can being provided to the processor of multi-purpose computer, special purpose computer, Embedded Processor or other programmable data processing device to produce a machine, making the instruction performed by the processor of computing machine or other programmable data processing device produce device for realizing the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.

These computer program instructions also can be stored in can in the computer-readable memory that works in a specific way of vectoring computer or other programmable data processing device, the instruction making to be stored in this computer-readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.

These computer program instructions also can be loaded in computing machine or other programmable data processing device, make on computing machine or other programmable devices, to perform sequence of operations step to produce computer implemented process, thus the instruction performed on computing machine or other programmable devices is provided for the step realizing the function of specifying in process flow diagram flow process or multiple flow process and/or block scheme square frame or multiple square frame.

Although describe the preferred embodiments of the present invention, those skilled in the art once obtain the basic creative concept of cicada, then can make other change and amendment to these embodiments.So claims are intended to be interpreted as comprising preferred embodiment and falling into all changes and the amendment of the scope of the invention.

Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.

Claims

1. a cpu busy percentage control method, is characterized in that, comprising:

The utilization factor of detection central processor CPU;

2. the method for claim 1, is characterized in that, described raising sends to described first buffer queue the transmission rate suppressing packet, comprising:

3. method as claimed in claim 2, is characterized in that, the described transmission rate sending suppression packet according to the raising of setting step-length to described first buffer queue, and sends suppression packet according to the transmission rate after improving to described first buffer queue, comprising:

Steps A: the utilization factor of detection CPU;

4. the method for claim 1, is characterized in that, also comprises:

If the utilization factor of described CPU is less than Second Threshold, then reduces and send to described first buffer queue the transmission rate suppressing packet; Wherein, described Second Threshold is less than or equal to described first threshold.

5. method as claimed in claim 4, is characterized in that, if the utilization factor of described CPU is less than Second Threshold, then reduces and sends to described first buffer queue the transmission rate suppressing packet, comprising:

Steps A: the utilization factor of detection CPU;

Step B: if the utilization factor of described CPU is less than described Second Threshold, then proceed to step C;

Step C: judge to send to described first buffer queue to suppress the transmission rate of packet whether to be greater than zero, if so, then proceed to step D, otherwise proceed to A;

Step D: reduce according to setting step-length and send to described first buffer queue the transmission rate suppressing packet, and proceed to steps A.

6. the method according to any one of claim 1 to 5, is characterized in that, also comprises:

If described cpu busy percentage is less than described first threshold and is more than or equal to Second Threshold, then determine the control data bag buffer queue needing enlargement discharge to suppress according to the priority of control data bag, and improve the speed sending suppression packet to the described control data bag buffer queue needing enlargement discharge to suppress; Wherein, described grouping chip comprises N number of control data bag buffer queue, N be greater than 1 integer, the priority of the suppression packet in a control data bag buffer queue is higher than the priority of the control data bag in this buffer queue, suppression packet in a control data bag buffer queue is dropped after going out team from the control data bag buffer queue at place, enters the first buffer queue after the control data in a control data bag buffer queue contracts out team.

7. method as claimed in claim 6, is characterized in that, the described priority according to the control data bag buffer queue in grouping chip determines the control data bag buffer queue needing enlargement discharge to suppress, and comprising:

According to the priority order from low to high of control data bag, determine the control data bag buffer queue needing enlargement discharge to suppress.

8. method as claimed in claim 6, is characterized in that, also comprise:

If the utilization factor of described CPU is less than described Second Threshold, then determine the control data bag buffer queue needing to reduce flow suppression according to the priority of control data bag, and reduce to the described speed needing the control data bag buffer queue reducing flow suppression to send suppression packet.

9. method as claimed in claim 8, is characterized in that, the described priority according to control data bag determines the control data bag buffer queue needing to reduce flow suppression, comprising:

The buffer queue needing to reduce flow suppression is determined according to the priority order from high to low of the buffer queue in described grouping chip.

10. a cpu busy percentage control device, is characterized in that, comprising:

Probe unit, for detecting the utilization factor of central processor CPU;

11. devices as claimed in claim 10, it is characterized in that, described suppression unit comprises:

Determining subelement, for according to being sent to the quantity of measurement data bag of described first buffer queue and the quantity of measurement data bag that returns from described first buffer queue, determining the quantity of the measurement data bag in described first buffer queue; Wherein, the priority of the measurement data bag in described first buffer queue is lower than the priority of the control data bag in this buffer queue, described measurement data bag is sent to described first buffer queue by coprocessor and after going out team, is forwarded to described coprocessor, and the transmission rate of described measurement data bag is the minimum guaranteed rate of described first buffer queue;

Suppress subelement, when quantity for measurement data bag in described first buffer queue is greater than zero, the difference of the quantity of the measurement data bag that the measurement data bag quantity suppressing the transmission rate of packet to be set to be sent to described first buffer queue in the unit interval is forwarded with described first buffer queue received, and send suppression packet according to the transmission rate of the suppression packet determined to described first buffer queue; Wherein, the measurement data bag quantity being sent to described first buffer queue in the described unit interval is identical with the minimum guaranteed rate of described first buffer queue, in described first buffer queue, the priority of packet is followed successively by suppression packet from high to low, control data bag, measurement data bag; Or

12. devices as claimed in claim 11, it is characterized in that, described suppression subelement is specifically for performing following flow process:

Steps A: the utilization factor of detection CPU;

13. devices as claimed in claim 10, is characterized in that, described suppression unit also for:

14. devices as claimed in claim 13, it is characterized in that, described suppression unit is specifically for performing following flow process:

Steps A: the utilization factor of detection CPU;

15. devices according to any one of claim 10 to 14, is characterized in that, described suppression unit also for:

16. devices as claimed in claim 15, is characterized in that, described suppression unit, specifically for:

17. devices as claimed in claim 15, is characterized in that, described suppression unit, specifically for:

When the utilization factor of described CPU is less than described Second Threshold, determine the control data bag buffer queue needing to reduce flow suppression according to the priority of control data bag, and reduce to the described speed needing the control data bag buffer queue reducing flow suppression to send suppression packet.

18. devices as claimed in claim 17, is characterized in that, described suppression unit, specifically for: