CN105160086B - A kind of 1-Wire bus exempts from pull-up resistor port configuration method - Google Patents
A kind of 1-Wire bus exempts from pull-up resistor port configuration method Download PDFInfo
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- CN105160086B CN105160086B CN201510531051.1A CN201510531051A CN105160086B CN 105160086 B CN105160086 B CN 105160086B CN 201510531051 A CN201510531051 A CN 201510531051A CN 105160086 B CN105160086 B CN 105160086B
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Abstract
The invention discloses a kind of 1-Wire buses to exempt from pull-up resistor port configuration method, eliminates the demand in traditional configuration mode to pull-up resistor, simplifies circuit, has stronger driving capability, while being also convenient for carrying out low-power consumption management.In the connection type of traditional 1-Wire equipment and controller etc., because master-slave equipment is open-drain output, need to connect a pull-up resistor in bus.The present invention to 1-Wire principle and timing analyze on the basis of, for current generally existing configurable port novel embedded controller with from the connection of device, propose it is a kind of by programming the I/O mode of dynamic configuration director port and realizing the scheme exempted from pull-up resistor and carry out interface from device.The program had both reduced a pull-up resistor, also has the characteristics that strong pull-up and convenient for energy-saving design, can be used in the 1-Wire network design of multinode and long distance transmission and in the application of low-power consumption.
Description
Technical field
The invention belongs to 1-Wire electronic design arts more particularly to a kind of 1-Wire bus to exempt from pull-up resistor port
Configuration method.
Background technique
The main equipment that 1-Wire bus network is usually expressed as an open-drain mode in physics realization connects one or more
The slave equipment (1-Wire bus device) of open-drain mode connects a pull-up resistor on data/address bus for pulling up 1-Wire bus
To 3V or 5V.In the gap of data communication, 1-Wire bus device obtains power supply by data/address bus.In 1-Wire bus device
The capacitor that portion is integrated with a 800pF is used to store the energy obtained from data line " surreptitiously ", and in communication period to power itself.
1-Wire bus is bidirectional bus, starts reset and read-write operation from main device to from device.Its basic operation has 4 kinds:Write 1,
0 is write, reads and resets, advanced byte operation can be obtained by preceding 3 operative combinations.Determine the device of the state of 1-Wire bus
There are 3 kinds:Main device, pull-up resistor and from device, 1-Wire bus is defeated in the equal high resistant of default conditions (idle state) master-slave equipment
Out, 1-Wire bus pulls into high level via pull-up resistor by positive supply, " charges " during this period from equipment.It pulls up in the application
The size of resistance R will be limited according to the energy consumption of system, communication speed and network size carry out careful selection.Resistance is bigger, main device
Part or from device discharge 1-Wire bus after 1-Wire bus is pulled into high level by power supply the time spent in it is also more, work as electricity
Resistance is big to a certain extent, it could even be possible to causing the rise time too long without being able to satisfy the timing requirements of 1-Wire bus device;
Resistance is smaller, then the ability drawn high 1-Wire bus is also stronger, main device or from device output it is low level when pass through
The electric current of resistance is also bigger, and energy consumption is also bigger, and too small resistance also results in pull-up ability too by force so that 1-Wire
The master and slave device of bus can not drag down bus level.
Summary of the invention
The present invention is directed to the problems of the prior art, provides a kind of 1-Wire bus and exempts from pull-up resistor port configuration method,
By program dynamic configuration master controller port I/O mode and 1-Wire bus from device realization exempt from pull-up resistor into
The scheme of line interface.The program has the characteristics that strong pull-up and also convenient for energy-saving design, can be used for multinode and passes over long distances
Defeated 1-Wire bus network design neutralizes in the application of low-power consumption.
The technical solution adopted by the present invention to solve the technical problems is:A kind of 1-Wire bus is provided and exempts from pull-up resistor end
Mouth configuration method resets operation and includes the following steps that step 1 sets push-pull output mode for master controller port and exports
1, it is that 1-Wire bus charges from device;Step 2, master controller port push-pull output mode output 0, and the H that is delayed, are being delayed
In time, from device after the low level for detecting 1-Wire bus, internal circuit resets 1-Wire bus;Step 3, it is main
Director port is set as push-pull output mode and exports 1, retention time I1;Step 4, set weak for master controller port on
Input pattern is drawn, be delayed I2, and detects whether 1-Wire bus is pulled low, if 1-Wire bus is pulled low, next step is carried out,
If 1-Wire bus is not pulled low, subsequent operation is abandoned;Step 5 waits J1, and then master controller port is set as recommending defeated
Mode and output 1 out.It resets and completes.Idle state after the reset, master controller port should be at push-pull output high level
State, so as to be subsequent operation charging.
According to the above technical scheme, in the step 1, it is 1-Wire bus from device charging time at least 2.5 μ s (G), walks
In rapid two, delay time H is 480~960 μ s, and in step 3, time I1 is 2~6 μ s, and in step 4, delay time I2 is 30
~200 μ s, in step 5, waiting time J1 is 10~20 μ s.
According to the above technical scheme, it writes 1 operation to include the following steps, sets push-pull output mode simultaneously for master controller port
Export 0,2~15 μ s (A) of duration, by master controller port be set as push-pull output mode and export 1, the duration 20~
45μs(B)。
According to the above technical scheme, it writes 0 operation to include the following steps, sets push-pull output mode simultaneously for master controller port
0,35~60 μ s (C) of duration are exported, sets push-pull output mode and output 1 for master controller port, the duration is big
In 2.5 μ s (D).
According to the above technical scheme, it reads 1-Wire bus operation and includes the following steps that master controller port is arranged step 1
For push-pull output mode and 0 is exported, 2~15 μ s (A) of duration;Master controller port is set push-pull output by step 2
Mode simultaneously exports 1,2~4 μ s (E1) of duration;Step 3, master controller port are configured to weak pull-up input pattern, when continuing
Between 2~5 μ s (E2);Step 4, master controller read 1-Wire bus state, obtain the result that 1-Wire bus is read in this time;Step
Five, the waiting time is greater than 2.5 μ s (F), sets push-pull output mode for master controller port and exports 1.
The beneficial effect comprise that:(1) needs of pull-up resistor are eliminated;(2) in the interface for exempting from pull-up resistor
Be in mode by master controller inside push-pull circuit realize the pull-up of 1-Wire bus level, and pushing away inside master controller
Drawing circuit is usually to be realized by MOSFET, has strong driving capability, realizes the 1-Wire bus network of strong driving capability
Target.Therefore this method is used, can also drive and need the 1-Wire bus of larger current from device or 1-Wire bus network
Network;(3) by using recommend+weak pull-up (open-drain) realize traditional scheme in pull-up resistor function, also have reduction system
The advantages of power consumption.Electric current in traditional scheme, if VCC selects 5V, when master controller exports low level, in pull-up resistor
Reach I=U/R=5V/4.7K Ω ≈ 1.1mA, in hand system, belongs to the biggish component of power consumption, master in the method for the present invention
The low and high level of controller output is push-pull output mode, and the electric current accordingly consumed is with regard to much smaller, mainly level conversion
The leakage current of electric current and metal-oxide-semiconductor, generally microampere rank.(4) not using additional power supply line to 1-Wire bus from
In the system of device power supply, if what 1-Wire bus obtained from device is the tempolabile signals such as temperature, pressure, only need once in a while into
Enter working condition, master controller in 1-Wire bus from 0 recommended is exported during the off working state of device, may be implemented so that
1-Wire bus powers off to achieve the purpose that reduce system power dissipation from device.
Detailed description of the invention
Present invention will be further explained below with reference to the attached drawings and examples, in attached drawing:
Fig. 1 is that 1-Wire bus of the embodiment of the present invention exempts from pull-up resistor port configuration method basic operation waveform diagram;
Fig. 2 is the basic operation waveform diagram of traditional pull-up resistor form 1-Wire bus.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that described herein, specific examples are only used to explain the present invention, not
For limiting the present invention.
In the embodiment of the present invention, a kind of 1-Wire bus is provided and exempts from pull-up resistor port configuration method, resetting operation includes
Following steps, step 1 set push-pull output mode and output 1 for master controller port, fill for 1-Wire bus from device
Electricity;Step 2, master controller port push-pull output mode output 0, and the H that is delayed, in delay time, 1-Wire bus is from device
After the low level for detecting 1-Wire bus, internal circuit resets;Step 3, master controller port are set as push-pull output mould
Formula simultaneously exports 1, retention time I1;Master controller port is set weak pull-up input pattern by step 4, and be delayed I2, and detects
Whether 1-Wire bus is pulled low, if 1-Wire bus is pulled low, carries out next step and puts if 1-Wire bus is not pulled low
Abandon subsequent operation;Step 5 waits J1, and then master controller port is set as push-pull output mode and exports 1.It resets and completes.
Idle state after the reset, master controller port should be at the state of push-pull output high level, to fill for subsequent operation
Electricity.
In current general each quasi-controller, port is usually configurable, and generally can be configured open-drain, (weak) pull-up
With push-pull output mode and other modes.Such as the C8051FXXX series monolithic of Silab company, ST Microelectronics
(STMicroelectronics) the controller STM32F10XXX Series Controller of CotexM3, the pin of these controllers are equal
The dynamic configuration of port mode can be realized by writing program.In each stage of 1-Wire bus, can be wanted according to timing
The mode of the pin of dynamic configuration main device is sought, to substitute the function of pull-up resistor.Chip is measured with common temperature
For DS18B20, in the core databook, the pull-up resistor of recommendation is 4.7K Ω, and in C8051F single-chip microcontroller and STM32F10X
The integrated pull-up resistor size in portion is respectively Ω × 21 about 4.7K and Ω × 8.5 4.7K, is all far longer than recommendation.If only
Using the pull-up resistor inside controller, timing requirements can not be met, it is necessary to dexterously utilize the push-pull output of Embedded
To simulate stronger pull-up ability.By using the method for the present invention, the needs of pull-up resistor are not only eliminated, also there is driving energy
The advantages that power is strong, low in energy consumption and energy-saving design easy to accomplish.
It further, is 1-Wire bus from device charging time at least 2.5 μ s (G), step 2 in the step 1
In, delay time H is 480~960 μ s, and in step 3, time I1 is 2~6 μ s, and in step 4, delay time I2 is 30~200
μ s, in step 5, waiting time J1 is 10~20 μ s.
In the embodiment of the present invention, which exempts from pull-up resistor port configuration method, and writing 1 operation includes following step
Suddenly, push-pull output mode is set by master controller port and export 0,2~15 μ s (A) of duration, by master controller port
It is set as push-pull output mode and exports 1,20~45 μ s (B) of duration.
Further, in the embodiment of the present invention, which exempts to write 0 operation in pull-up resistor port configuration method
Include the following steps, sets push-pull output mode and output 0 for master controller port, 35~60 μ s (C) of duration will be led
Director port is set as push-pull output mode and output 1, and the duration is greater than 2.5 μ s (D).
Further, it reads 1-Wire bus operation and includes the following steps that master controller port is set as recommending by step 1
Output mode simultaneously exports 0,2~15 μ s (A) of duration;Step 2 sets push-pull output mode simultaneously for master controller port
Output 1,2~4 μ s (E1) of duration;Step 3, master controller port are configured to weak pull-up input pattern, duration 2~5
μs(E2);Step 4, master controller read 1-Wire bus state, obtain the result that 1-Wire bus is read in this time;Step 5 waits
Time is greater than 2.5 μ s (F), sets push-pull output mode for master controller port and exports 1.
If not using pull-up resistor from the interface of device in master controller and 1-Wire bus, to using pull-up resistor
In the case of waveform diagram, as shown in Fig. 2, the part that pull-up resistor works needs dynamic configuration just to control corresponding pin and be
Push-pull output mode or weak pull-up (open-drain) mode are to come the function of simulating pull-up resistor.In conjunction with the characteristic of one-chip machine port,
New waveform diagram is obtained, as shown in Figure 1.Compared with using pull-up resistor situation, under the timing of configurable port master device has
The variation in face:
1) in the timing write 1 and write 0, the part (high level) worked originally by pull-up resistor is recommended by master controller
Output 1;
2) master controller, which is write, during reading 1-Wire bus, in Fig. 2 discharges 1-Wire bus after 0 delay A, then by
Pull-up resistor draws high bus;
3) the same master controller in part for drawing high 1-Wire bus by pull-up resistor originally in a reset operation, which is recommended, draws high
Then 1-Wire bus discharges;
4) to the state operated, before t 0 is resetted, designer can configure according to what system designed.It writes multiple
After the position and subsequent gap for writing 0, writing 1 and reading 1-Wire bus, it should which master controller is configured as output to recommend 1
(or 1 of weak pull-up) is to maintain working power of the 1-Wire bus from device;It, can also be with after primary complete operation
Recommend 0 realization power-off of the 1-Wire bus from device is configured by master controller.
In the methods of the invention, master controller and 1-Wire bus should be selected from the pin of device interface on weak
It draws, the pin of open-drain and push-pull output function.Master controller is when exporting 0, either push-pull output mode or open-drain mode,
There is very strong 1-Wire bus pull-down capability, 1-Wire bus will become low level;When exporting 1, push-pull output mode has
Very strong pull-up ability can be pulled to 1-Wire bus high level, and open-drain mode is equivalent to and releases 1-Wire bus.Pass through
The output mode of dynamic configuration respective pins in program operation, so that it may realize the function of 1-Wire main device.In which
Lower 1-Wire bus idle state is drawn high by the weak pull-up function (or push-pull output 1) of main device.
It is ingenious that the main distinction of configurable port interface and open-drain interface is that the former is pulled up the leading part of resistance
Ground is converted to the switching of the pin mode of the port of master controller.In Fig. 2, the present invention program sets pin in the t2-t3 stage
For push-pull output mode, so that 1-Wire bus is pulled up rapidly as high level, so as to cause 1-Wire bus from the defeated of device
Timing out;But again because 1-Wire bus sometime will drag down 1-Wire bus in subsequent from device, master control
Device processed should release immediately bus after 1-Wire bus is raised, in order to avoid competing with 1-Wire bus from device, cause to assist
View is destroyed or device damage.In t4 to t6 stage, also there is similar consideration:At the t5 moment, that is, the selection for the J1 that is delayed, it is ensured that
1-Wire bus has released 1-Wire bus from device, so that bus contention will not be generated, but can not be too late, otherwise
Too slow 1-Wire bus voltage rises the complete realization that may also destroy 1-Wire bus protocol.The selection of design parameter should
It is calculated according to the chip handbook of master and slave device.Such as it is used in the Interface design of C8051F320 and DS18B20 upper
The scheme stated, and it is successfully realized the communication of the two.
It should be understood that for those of ordinary skills, it can be modified or changed according to the above description,
And all these modifications and variations should all belong to the protection domain of appended claims of the present invention.
Claims (5)
1. a kind of 1-Wire bus exempts from pull-up resistor port configuration method, which is characterized in that reset operation and include the following steps, walk
Rapid one, push-pull output mode and output 1 are set by master controller port, is that 1-Wire bus charges from device;Step 2, it is main
Director port push-pull output mode output 0, and the H that is delayed, in delay time, 1-Wire bus is detecting 1- from device
After the low level of Wire bus, internal circuit resets;Step 3, master controller port are set as push-pull output mode and output 1,
Retention time I1;Master controller port is set weak pull-up input pattern by step 4, and be delayed I2, and detects 1-Wire bus
Whether it is pulled low, if 1-Wire bus is pulled low, carries out next step if 1-Wire bus is not pulled low and abandon subsequent operation;
Step 5 waits J1, and then master controller port is set as push-pull output mode and exports 1.
2. 1-Wire bus according to claim 1 exempts from pull-up resistor port configuration method, which is characterized in that the step
It is 1-Wire bus from device charging time at least 2.5 μ s, step 2, delay time H is 480~960 μ s, step in one
In three, time I1 is 2~6 μ s, and in step 4, delay time I2 is 30~200 μ s, in step 5, waiting time J1 is 10~
20μs。
3. 1-Wire bus according to claim 1 or 2 exempts from pull-up resistor port configuration method, which is characterized in that write 1 behaviour
Work includes the following steps, sets push-pull output mode for master controller port and exports 0,2~15 μ s of duration, by master control
Device port processed is set as push-pull output mode and exports 1,20~45 μ s of duration.
4. 1-Wire bus according to claim 1 or 2 exempts from pull-up resistor port configuration method, which is characterized in that write 0 behaviour
Work includes the following steps, sets push-pull output mode and output 0 for master controller port, 35~60 μ s of duration will be led
Director port is set as push-pull output mode and output 1, and the duration is greater than 2.5 μ s.
5. 1-Wire bus according to claim 1 or 2 exempts from pull-up resistor port configuration method, which is characterized in that read 1-
Wire bus operation includes the following steps that step 1 sets push-pull output mode and output 0 for master controller port, continues
2~15 μ s of time;Step 2 sets push-pull output mode for master controller port and exports 1,2~4 μ s of duration;Step
Rapid three, master controller port is configured to weak pull-up input pattern, 2~5 μ s of duration;Step 4, master controller read 1-Wire
Bus state obtains the result that 1-Wire bus is read in this time;Step 5, waiting time are greater than 2.5 μ s, master controller port are set
It is set to push-pull output mode and exports 1.
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CN203151822U (en) * | 2013-02-19 | 2013-08-21 | 中国农业大学 | Bus type lighting controlling device with address identification |
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CN104657303A (en) * | 2014-10-13 | 2015-05-27 | 江苏瑞微电子有限公司 | Unibus data communication method |
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- 2015-08-26 CN CN201510531051.1A patent/CN105160086B/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN203151822U (en) * | 2013-02-19 | 2013-08-21 | 中国农业大学 | Bus type lighting controlling device with address identification |
CN103823776A (en) * | 2014-02-28 | 2014-05-28 | 上海晟矽微电子股份有限公司 | Unibus in communication with master equipment and slave equipment and communication method |
CN104657303A (en) * | 2014-10-13 | 2015-05-27 | 江苏瑞微电子有限公司 | Unibus data communication method |
Non-Patent Citations (1)
Title |
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