CN105140304A - 一种NiO:Na/TiOx异质pn结二极管 - Google Patents

一种NiO:Na/TiOx异质pn结二极管 Download PDF

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CN105140304A
CN105140304A CN201510633292.7A CN201510633292A CN105140304A CN 105140304 A CN105140304 A CN 105140304A CN 201510633292 A CN201510633292 A CN 201510633292A CN 105140304 A CN105140304 A CN 105140304A
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李彤
王铁钢
陈佳楣
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Tianjin University of Technology
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/8611Planar PN junction diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/225Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIBVI compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • H01L29/66136PN junction diodes

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Abstract

本发明公开了一种NiO:Na/TiOx异质pn结二极管,至少包括pn结和欧姆接触电极,所述pn结在Si衬底上生长p型NiO:Na薄膜以及n型TiOx薄膜得到异质pn结。本发明利用磁控溅射工艺在Si衬底上制备NiO:Na/TiOx异质pn结二极管,最后采用磁控溅射或热蒸发法在pn结上制作电极。本发明中异质pn结二极管具有较高的反向击穿电压、较大的正向电流密度,而且其制备方法工艺简单。

Description

一种NiO:Na/TiOx异质pn结二极管
技术领域
本发明涉及一种NiO:Na/TiOx异质pn结二极管。属于功能材料和光电子器件领域。
背景技术
强关联材料NiO中含有的d(f)电子的内部自由度如自旋、电荷、轨道之间的相互作用,使得NiO表现出许多奇异的性质,同时也使得材料的物性随着内部参数如温度、压强、掺杂的变化而发生显著改变。截止到目前,NiO因其良好的催化性能、热敏性能而被应用于催化剂、电池电极、电化学电容器等领域的研究,对其光电特性的研究少见报道。半导体异质结易于实现光生电荷分离被广泛应用于薄膜电池等光电子器件的研制和开发。NiO除了上述性质外,还是p型直接宽带隙半透明半导体材料,与间接带隙半导体材料相比,量子效率相对较高。室温下禁带宽度为3.0-4.0eV,3d电子结构的d-d轨道跃迁,使其在可见光区域存在较弱吸收。我们通过NiO基异质结形式研究新型光电子器件。P.Puspharajha等人采用喷雾热解法通过对NiO掺入Li+使NiO薄膜在可见光波段透光率达到90%,薄膜电阻下降到1Ω?cm(见文献PPUSPHARAJAH,SRADHAKRISHNA,AKAROF.Transparentconductinglithium-dopednickeloxidethinfilmsbyspraypyrolysistechnique.JournalofMaterialsScience,1997,32(11):3001-3006)。但从长远考虑,Na金属更为常见,价格更为便宜。我们将Na元素引入NiO,制备NiO:Na基pn结二极管。于此同时,我们选用价格低廉的n型TiOx作为pn结的另一端,从而实现NiO:Na/TiOx异质pn结二极管。众所周知,TiOx集多种功能于一身,而且在很多领域已被广泛应用。这种选择对于新型器件的开发有着重要意义,而目前对于NiO:Na/TiOx异质结还未见报道。
发明内容
为提高传统的平面pn结二极管的性能,本发明提供了一种NiO:Na/TiOx异质pn结二极管,制备的NiO:Na/TiOx异质pn结二极管具有较高的反向击穿电压和大的正向电流密度。相对于传统的平面pn结二极管,该新型二极管的整流特性得到了提高。本发明的技术方案:NiO:Na/TiOx异质pn结二极管,至少包括pn结和欧姆接触电极,所述pn结是由p型NiO:Na和n型TiOx形成异质pn结。
上述NiO:Na/TiOx异质pn结二极管的制备方法:用磁控溅射工艺在Si衬底上制备NiO:Na薄膜以及TiOx薄膜形成异质pn结;最后采用溅射或热蒸发法在pn结上制作电极;其中,NiO:Na和TiOx表面溅射或蒸发银,镍或铝或金电极。本发明采用直径为50mm的NiO:Na2O陶瓷靶,磁控溅射制备的NiO:Na薄膜。溅射前的腔体本底真空度优于3x10-4Pa,在此采用的相对氧分压O2/(O2+Ar)=0%-100%。溅射气压为0.5-2Pa,溅射功率100-200W。在镀膜之前,预溅射5min以去除靶材表面的杂质。镀膜时间均为20-120min,衬底温度为RT-600oC或者后期退火温度从200oC至700oC时间为0.5至1个小时。本发明采用直径为50mm的TiO2陶瓷靶,磁控溅射制备的TiOx薄膜。溅射前的腔体本底真空度优于3x10-4Pa,在此采用的相对氧分压O2/(O2+Ar)=0%-100%。溅射气压为0.5-2Pa,溅射功率50-200W。在镀膜之前,预溅射5min以去除靶材表面的杂质。镀膜时间均为20-120min,衬底温度为RT-600oC或者后期退火温度从200oC至700oC时间为0.5至1个小时。
本发明利用p型NiO:Na薄膜与n型TiOx薄膜形成了异质pn结二极管。通过对NiO:Na薄膜以及TiOx薄膜制备等条件的控制、pn结结构的优化等,提高了异质pn结性能,充分发挥半导体NiO:Na在异质pn结应用方面的独到优势。
附图说明
图1为本发明NiO:Na/TiOx异质pn结结构图
图2为本发明反映异质结整流特性的I-V曲线(实施例一)
图3为本发明反映异质结整流特性的I-V曲线(实施例二)
图4为本发明反映异质结整流特性的I-V曲线(实施例三)
具体实施方式
本发明NiO:Na/TiOx异质pn结二极管,至少包括pn结和欧姆接触电极,所述pn结是在n型Si衬底上沉积NiO:Na/TiOx形成异质pn结,见图1。其具体制备步骤如下:(1)采用半导体工艺中的清洗方法清洗硅片并用氮气吹干;(2)p-NiO:Na的制备:溅射前的腔体本底真空度优于3x10-4Pa,采用的相对氧分压O2/(O2+Ar)=0%-100%,溅射气压为0.5-2Pa,溅射功率100-200W。在镀膜之前,预溅射5min以去除靶材表面的杂质。镀膜时间均为20-120min,衬底温度为RT-600oC以及温度为200oC至700oC退火0.5至1个小时。(3)n-TiOx的制备:溅射前的腔体本底真空度优于3x10-4Pa,采用的相对氧分压O2/(O2+Ar)=0%-100%,溅射气压为0.5-2Pa,溅射功率50-200W。在镀膜之前,预溅射5min以去除靶材表面的杂质。镀膜时间均为20-120min,衬底温度为RT-600oC以及温度为200oC至700oC退火0.5至1个小时。(4)电极的制备:采用热蒸发方法在NiO:Na和TiOx表面边缘制作Al电极。(5)测试用Keithley2612A检测电极的欧姆接触特性和异质pn结二极管的I-V特性(整流特性)。
实施例一
(1)采用半导体工艺中的清洗方法清洗硅片并用氮气吹干;(2)p-NiO:Na的制备:采用直径为50mm的NiO:Na2O陶瓷靶。磁控溅射制备的NiO:Na薄膜。溅射前的腔体本底真空度优于3x10-4Pa,采用的相对氧分压O2/(O2+Ar)=30%。溅射气压为2Pa,溅射功率150W。在镀膜之前,预溅射5min以去除靶材表面的杂质。镀膜时间均为40min,衬底温度为室温(RTroomtemperature)。(3)n-TiOx的制备:采用直径为50mm的TiO2陶瓷靶。溅射前的腔体本底真空度优于3x10-4Pa,采用的相对氧分压O2/(O2+Ar)=0%,溅射气压为1Pa,溅射功率100W。在镀膜之前,预溅射5min以去除靶材表面的杂质。镀膜时间均为60min,衬底温度为RT。(4)电极的制备:采用热蒸发方法在NiO:Na和TiOx表面边缘制作Al电极。(5)测试用Keithley2612A检测电极的欧姆接触特性和异质pn结二极管的I-V特性(整流特性),见图2。
实施例二
(1)采用半导体工艺中的清洗方法清洗硅片并用氮气吹干;(2)p-NiO:Na的制备:采用直径为50mm的NiO:Na2O陶瓷靶。磁控溅射制备的NiO:Na薄膜。溅射前的腔体本底真空度优于3x10-4Pa,采用的相对氧分压O2/(O2+Ar)=30%。溅射气压为2Pa,溅射功率150W。在镀膜之前,预溅射5min以去除靶材表面的杂质。镀膜时间均为40min,衬底温度为室温,并进行200oC后期退火0.5h。(3)n-TiOx的制备:采用直径为50mm的TiO2陶瓷靶。溅射前的腔体本底真空度优于3x10-4Pa,采用的相对氧分压O2/(O2+Ar)=0%,溅射气压为1Pa,溅射功率100W。在镀膜之前,预溅射5min以去除靶材表面的杂质。镀膜时间均为60min,衬底温度为RT。(4)电极的制备:采用热蒸发方法在NiO:Na和TiOx表面边缘制作Al电极。(5)测试用Keithley2612A检测电极的欧姆接触特性和异质pn结二极管的I-V特性(整流特性),见图3。
实施例三
(1)采用半导体工艺中的清洗方法清洗硅片并用氮气吹干;(2)p-NiO:Na的制备:采用直径为50mm的NiO:Na2O陶瓷靶。磁控溅射制备的NiO:Na薄膜。溅射前的腔体本底真空度优于3x10-4Pa,采用的相对氧分压O2/(O2+Ar)=30%。溅射气压为2Pa,溅射功率150W。在镀膜之前,预溅射5min以去除靶材表面的杂质。镀膜时间均为40min,衬底温度为室温,并进行300oC后期退火0.5h。(3)n-TiOx的制备:采用直径为50mm的TiO2陶瓷靶。溅射前的腔体本底真空度优于3x10-4Pa,采用的相对氧分压O2/(O2+Ar)=0%,溅射气压为1Pa,溅射功率100W。在镀膜之前,预溅射5min以去除靶材表面的杂质。镀膜时间均为60min,衬底温度为RT。(4)电极的制备:采用热蒸发方法在NiO:Na和TiOx表面边缘制作Al电极。(5)测试用Keithley2612A检测电极的欧姆接触特性和异质pn结二极管的I-V特性(整流特性),见图4。

Claims (9)

1.一种NiO:Na/TiOx异质pn结二极管,至少包括pn结和欧姆接触电极,其特征在于:所述pn结是由p型NiO:Na薄膜和n型TiOx薄膜而得到的异质pn结。
2.权利要求1所述NiO:Na/TiOx异质pn结二极管的制备方法,其特征在于:用磁控溅射工艺在Si衬底上制备NiO:Na薄膜和TiOx薄膜形成异质pn结。
3.根据权利要求2所述的制备方法,其特征在于:本发明采用NiO:Na2O陶瓷靶,磁控溅射工艺制备NiO:Na薄膜,在此采用氧分压O2/(O2+Ar)=0%-100%。
4.溅射前的腔体本底真空度优于3x10-4Pa,溅射气压为0.5-2Pa,溅射功率为100-200W。
5.镀膜时间均为20-120min,衬底温度从RT变化至600oC,退火温度从200oC变化至700oC。
6.根据权利要求2所述的制备方法,其特征在于:本发明采用TiO2陶瓷靶,磁控溅射工艺制备TiOx薄膜,在此采用氧分压O2/(O2+Ar)=0%-100%。
7.溅射前的腔体本底真空度优于3x10-4Pa,溅射气压为0.5-2Pa,溅射功率为50-200W。
8.镀膜时间均为20-120min,衬底温度从RT变化至600oC,退火温度从200oC至700oC。
9.权利要求1或2或3或6所述NiO:Na/TiOx异质pn结二极管的制备方法,其特征在于:采用溅射法或热蒸发法在pn结上制作电极;其中,NiO:Na和TiOx表面沉积银,镍,铝或金电极。
CN201510633292.7A 2015-09-30 2015-09-30 一种NiO:Na/TiOx异质pn结二极管 Pending CN105140304A (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110303888A1 (en) * 2010-06-15 2011-12-15 Kabushiki Kaisha Toshiba Nonvolatile memory device
CN103715216A (zh) * 2012-10-03 2014-04-09 力晶科技股份有限公司 电阻式存储器单元及其制作方法
CN104124282A (zh) * 2013-04-25 2014-10-29 天津职业技术师范大学 一种Si/NiO:Na异质pn结二极管

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110303888A1 (en) * 2010-06-15 2011-12-15 Kabushiki Kaisha Toshiba Nonvolatile memory device
CN103715216A (zh) * 2012-10-03 2014-04-09 力晶科技股份有限公司 电阻式存储器单元及其制作方法
CN104124282A (zh) * 2013-04-25 2014-10-29 天津职业技术师范大学 一种Si/NiO:Na异质pn结二极管

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Application publication date: 20151209