CN105140129B - The process of LDMOS device buried layer - Google Patents
The process of LDMOS device buried layer Download PDFInfo
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- CN105140129B CN105140129B CN201510607086.9A CN201510607086A CN105140129B CN 105140129 B CN105140129 B CN 105140129B CN 201510607086 A CN201510607086 A CN 201510607086A CN 105140129 B CN105140129 B CN 105140129B
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- 238000000034 method Methods 0.000 title claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 18
- 238000002347 injection Methods 0.000 claims abstract description 10
- 239000007924 injection Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000001259 photo etching Methods 0.000 claims abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 4
- 239000010703 silicon Substances 0.000 claims abstract description 4
- 238000002513 implantation Methods 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7826—Lateral DMOS transistors, i.e. LDMOS transistors with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a kind of processes of LDMOS device buried layer, include: step 1 defines n type buried layer area using photoresist on a silicon substrate, and in the periphery in n type buried layer area, one or more N-type annular buried layer area for surrounding the n type buried layer area is defined；Step 2 carries out the injection of n type buried layer, and the n type buried layer area window and N-type annular buried layer area window that impurity is opened by photoetching enter in substrate, forms n type buried layer area and N-type annular buried layer area；Step 3 carries out high temperature propulsion；Step 4 carries out the general note of p type impurity ion, forms p type buried layer.The present invention does not increase the photoetching number of plies, still by the way of the general note of p type buried layer, adjusts the concentration of n type buried layer edge, improves the breakdown voltage of device.
Description
Technical field
The present invention relates to field of manufacturing semiconductor devices, particularly relate to a kind of process of LDMOS device buried layer.
Background technique
It is the structure that LDMOS is commonly isolated in the technique of BCD as shown in Figure 1, device is by p-well 3, p type buried layer 2 and N-type
Buried layer 1 is kept apart.The pressure-resistant limit of this device is determined by the breakdown voltage between n type buried layer 1 and p type buried layer 2.
At present n type buried layer and p type buried layer usually by photoetching fill into and boiler tube promote and formed.Concrete technology selection has:
1), n type buried layer is defined with mask plate, and p type buried layer uses the scheme of general note.This scheme can save a mask plate, but N-type is buried
Layer and p type buried layer connect together, and breakdown voltage BV is only adjusted by implantation dosage, and controllability is poor.2), n type buried layer
A mask plate is respectively used with p type buried layer.It can also be by adjusting n type buried layer other than regulating dosage with the scheme of two pieces of mask plates
Breakdown voltage BV is improved with the interval of p type buried layer.But this scheme will use two pieces of photolithography plates, higher cost.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of processes of LDMOS device buried layer, to improve device
Voltage endurance capability.
To solve the above problems, the process of LDMOS device buried layer of the present invention, includes:
Step 1 defines n type buried layer area using photoresist, and in the periphery in n type buried layer area, definition on a silicon substrate
One or more N-type annular buried layer area for surrounding the n type buried layer area out；
Step 2 carries out the injection of n type buried layer, and the n type buried layer area window and N-type annular that impurity is opened by photoetching bury
Floor area window enters in substrate, forms n type buried layer area and N-type annular buried layer area；
Step 3 carries out high temperature propulsion；
Step 4 carries out the injection of p type impurity ion, forms p type buried layer.
Further, in the step 1, the spacing and multiple N-types in the n type buried layer area and N-type annular buried layer area
Spacing between annular buried layer area, for adjusting the impurity concentration of the n type buried layer area edge after high temperature promotes；The N-type is buried
Spacing between floor area and the spacing and multiple N-type annular buried layer areas in N-type annular buried layer area is 0.5~8 μm.
Further, in the step 2, N-type impurity injection uses 40~200keV of Implantation Energy, implantation dosage 1014~
1016atoms/cm2。
Further, in the step 3, high temperature, which promotes, uses 1100~1250 DEG C, 30~300 minutes.
The process of LDMOS device buried layer of the present invention, it is one or more by increasing in n type buried layer area periphery
N-type annular buried layer, furnace tube high temperature propulsion rear impurity to side diffusion so that the impurity concentration in n type buried layer area edge region
It is low compared with intermediate region, improve the voltage endurance capability of PN junction between n type buried layer and the p type buried layer of periphery.
Detailed description of the invention
Fig. 1 is the buried layer schematic diagram of traditional LDMOS device；
Fig. 2 is the buried layer schematic diagram of another traditional LDMOS device.
Fig. 3~5 are buried layer process schematic representations of the present invention；
Fig. 6 is process flow chart of the invention.
Description of symbols
1 is n type buried layer, and 2 be p type buried layer, and 3 be p-well, and 4 be photoresist, and A, B are distances.
Specific embodiment
Technical problem to be solved by the invention is to provide a kind of processes of LDMOS device buried layer, to improve device
Voltage endurance capability.
To solve the above problems, the process of LDMOS device buried layer of the present invention, includes:
Step 1, as shown in figure 3, on a silicon substrate, defining n type buried layer area using photoresist, and in n type buried layer area
Periphery, define one or more N-type annular buried layer area for surrounding the n type buried layer area；The n type buried layer area and N-type
Spacing A between the spacing B in annular buried layer area and multiple N-type annular buried layer areas is buried for adjusting the N-type after high temperature promotes
The impurity concentration of layer area edge.A, B can choose 0.5~8 μm of different values according to actual needs, for example A takes 1 μm, and B takes 5 μ
M etc..
Step 2 carries out the injection of n type buried layer, and the n type buried layer area window and N-type annular that impurity is opened by photoetching bury
Floor area window enters in substrate, forms n type buried layer area and N-type annular buried layer area；N-type impurity injection using Implantation Energy 40~
200keV, implantation dosage 1014~1016atoms/cm2.As shown in Figure 3 and Figure 4, Fig. 4 is from depression angle it can be seen that N-type
Annular buried layer and the n type buried layer area that encirclement is surround by N-type annular buried layer, peripheral N-type annular buried layer the present embodiment, which is only shown, to be adopted
With an annular buried layer.
Step 3 carries out high temperature propulsion；High temperature, which promotes, uses 1100~1250 DEG C, 30~300 minutes.N-type is buried after propulsion
Layer is as shown in Figure 5.
Step 4 carries out the injection of p type impurity ion, forms p type buried layer.LDMOS device buried layer technique of the present invention
It completes.
The process of LDMOS device buried layer of the present invention, it is one or more by increasing in n type buried layer area periphery
N-type annular buried layer, furnace tube high temperature propulsion rear impurity to side diffusion so that the impurity concentration in n type buried layer area edge region
It is low compared with intermediate region, improve the voltage endurance capability of PN junction between n type buried layer and the p type buried layer of periphery.
The above is only a preferred embodiment of the present invention, is not intended to limit the present invention.Come for those skilled in the art
It says, the invention may be variously modified and varied.All within the spirits and principles of the present invention, made any modification, equivalent
Replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (4)
1. a kind of process of LDMOS device buried layer, characterized by comprising:
Step 1 defines n type buried layer area using photoresist, and in the periphery in n type buried layer area, define one on a silicon substrate
A or multiple N-type annular buried layer areas for surrounding the n type buried layer area；Between the n type buried layer area and N-type annular buried layer area
Away from and multiple N-type annular buried layer areas between spacing, be 0.5~8 μm；
Step 2, carries out the injection of n type buried layer, the n type buried layer area window and N-type annular buried layer area that impurity is opened by photoetching
Window enters in substrate, forms n type buried layer area and N-type annular buried layer area；
Step 3 carries out high temperature propulsion；
Step 4 carries out the injection of p type impurity ion, forms p type buried layer.
2. the process of LDMOS device buried layer as described in claim 1, it is characterised in that: in the step 1, the N
Spacing between type buried layer area and the spacing and multiple N-type annular buried layer areas in N-type annular buried layer area, pushes away for adjusting high temperature
The impurity concentration of n type buried layer area edge after.
3. the process of LDMOS device buried layer as described in claim 1, it is characterised in that: in the step 2, N-type impurity
Injection uses 40~200keV of Implantation Energy, implantation dosage 1014~1016atoms/cm2。
4. the process of LDMOS device buried layer as described in claim 1, it is characterised in that: in the step 3, high temperature is pushed away
Into using 1100~1250 DEG C, 30~300 minutes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510607086.9A CN105140129B (en) | 2015-09-22 | 2015-09-22 | The process of LDMOS device buried layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510607086.9A CN105140129B (en) | 2015-09-22 | 2015-09-22 | The process of LDMOS device buried layer |
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| Publication Number | Publication Date |
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| CN105140129A CN105140129A (en) | 2015-12-09 |
| CN105140129B true CN105140129B (en) | 2019-01-04 |
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| CN201510607086.9A Active CN105140129B (en) | 2015-09-22 | 2015-09-22 | The process of LDMOS device buried layer |
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| CN110120417A (en) * | 2019-04-15 | 2019-08-13 | 上海华虹宏力半导体制造有限公司 | High-voltage isolating ring |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020019111A1 (en) * | 2000-01-28 | 2002-02-14 | Joseph Pernyeszi | Semiconductor with high-voltage components and low-voltage components on a shared die |
| US20060223257A1 (en) * | 2002-08-14 | 2006-10-05 | Advanced Analogic Technologies, Inc. | Method Of Fabricating Isolated Semiconductor Devices In Epi-Less Substrate |
| CN104576364A (en) * | 2013-10-24 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of vertical NPN device |
| US20150187934A1 (en) * | 2013-12-29 | 2015-07-02 | Texas Instruments Incorporated | High voltage multiple channel ldmos |
-
2015
- 2015-09-22 CN CN201510607086.9A patent/CN105140129B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020019111A1 (en) * | 2000-01-28 | 2002-02-14 | Joseph Pernyeszi | Semiconductor with high-voltage components and low-voltage components on a shared die |
| US20060223257A1 (en) * | 2002-08-14 | 2006-10-05 | Advanced Analogic Technologies, Inc. | Method Of Fabricating Isolated Semiconductor Devices In Epi-Less Substrate |
| CN104576364A (en) * | 2013-10-24 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of vertical NPN device |
| US20150187934A1 (en) * | 2013-12-29 | 2015-07-02 | Texas Instruments Incorporated | High voltage multiple channel ldmos |
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| CN105140129A (en) | 2015-12-09 |
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