CN105099408A - Receiving device - Google Patents
Receiving device Download PDFInfo
- Publication number
- CN105099408A CN105099408A CN201510245837.7A CN201510245837A CN105099408A CN 105099408 A CN105099408 A CN 105099408A CN 201510245837 A CN201510245837 A CN 201510245837A CN 105099408 A CN105099408 A CN 105099408A
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- CN
- China
- Prior art keywords
- circuit
- error detect
- receiving system
- mistake
- detect circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0292—Arrangements specific to the receiver end
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
Abstract
The invention provides a receiving device including a termination circuit to which a received signal is input, a processing circuit which performs a process at a rear stage of the termination circuit, and an error detection circuit which detects an error contained in the received signal. In a case where the error is detected by the error detection circuit, a termination resistance value of the termination circuit is lowered. Therefore, the receiving device can be rapidly restored when a signal containing an error is received.
Description
Technical field
The present invention relates to receiving system, promptly recover when this receiving system receives the signal comprising mistake.
Background technology
In the past, proposed a kind of receiving circuit, this receiving circuit, when receiving the signal sent from dispensing device, prevents from receiving (such as referenced patent documents 1) such as mistakes.In such signal transmits, such as, send from dispensing device after carrying out considering the modulation of the distance of swimming (runlength) or DC balance, after receiving system receives this signal, demodulation is carried out to data.The noise robustness of known this communication mode is high.
Patent documentation 1: Japanese Unexamined Patent Publication 2008-219813 publication
But, be applied in extraneous noise in transmission lines, when being particularly applied in discharge noise, charge accumulation make a mistake in transmission lines in the circuit of rear class, and then there is the problem returning to normal condition and need the time.
Summary of the invention
The present invention completes in view of this problem, and object is to provide a kind of receiving system, promptly recovers when this receiving system receives the signal comprising mistake.
In order to solve above-mentioned problem, in the 1st receiving system, it is characterized in that having: terminating circuit, it is transfused to the signal received; Treatment circuit, it processes in the rear class of described terminating circuit; And error detect circuit, its mistake comprised to the received signal detects, and when mistake being detected by described error detect circuit, the termination resistance value of described terminating circuit is reduced.
According to this receiving system, by reducing termination resistance value, promptly can discharge the electric charge in the transmission lines of the input side being accumulated in receiving system, therefore receiving system can promptly recover.
In the 2nd receiving system, it is characterized in that, described error detect circuit is positioned at the rear class of described treatment circuit.
In the 3rd receiving system, it is characterized in that, described error detect circuit judges that whether the pattern of the signal received is normal, and be judged as in the abnormal situation of result of determination, described error detect circuit exports the information representing mistake.
In the 4th receiving system, it is characterized in that, described testing circuit, when the identical value that the signal received comprises occurs more than stipulated number continuously, is judged as that the pattern of the signal received is abnormal.
In the 5th receiving system, it is characterized in that, described error detect circuit is sampled with the frequency higher than its repetition rate to the received signal, and when the pattern of the value sampled comprises abnormal pattern, described error detect circuit is judged as that the pattern of the signal received is abnormal.
In the 6th receiving system, it is characterized in that, described error detect circuit is positioned at the prime of described terminating circuit or described treatment circuit.
In the 7th receiving system, it is characterized in that, described error detect circuit detects the voltage to the transmission lines of described terminating circuit transmission signal, and when the voltage detected is not in prescribed limit, described error detect circuit exports the information representing mistake.
In the 8th receiving system, it is characterized in that, the described signal received is the differential wave transmitted by 2 transmission lines, described terminating circuit has resistance circuit network, described resistance circuit network is connected to the node between described transmission lines, when mistake being detected by described error detect circuit, described resistance circuit network makes the resistance value of described resistance circuit network reduce.
In the 9th receiving system, it is characterized in that having: terminating circuit, it is transfused to the signal received; Treatment circuit, it processes in the rear class of described terminating circuit; And error detect circuit, its mistake comprised to the received signal detects, when mistake being detected by described error detect circuit, described receiving system makes described transmission lines be connected with fixed potential, discharges to make the electric charge be accumulated in the transmission lines of the input side be connected with described terminating circuit.If make transmission lines be connected with fixed potential, then the electric charge be accumulated in transmission lines is promptly discharged, and therefore receiving system promptly can return to normal condition.
According to receiving system of the present invention, promptly can recover when receiving the signal comprising mistake.
Accompanying drawing explanation
Figure 1A is the block diagram of the sending/receiving system comprising receiving system.
Figure 1B is the block diagram of the sending/receiving system comprising receiving system.
Fig. 2 A is the circuit diagram of the detailed construction that receiving system is shown.
Fig. 2 B is the circuit diagram of the detailed construction that receiving system is shown.
Fig. 3 A is the circuit diagram of the variation that terminating circuit is shown.
Fig. 3 B is the circuit diagram of the variation that terminating circuit is shown.
Fig. 3 C is the circuit diagram of the variation that terminating circuit is shown.
Fig. 3 D is the circuit diagram of the variation that terminating circuit is shown.
Fig. 3 E is the circuit diagram of the variation that terminating circuit is shown.
Fig. 3 F is the circuit diagram of the variation that terminating circuit is shown.
Fig. 3 G is the circuit diagram of the variation that terminating circuit is shown.
Embodiment
Below, the receiving system that execution mode relates to is described.Identical label is used to identical element, and the repetitive description thereof will be omitted.
Figure 1A and Figure 1B is the block diagram of the sending/receiving system comprising receiving system 10 and dispensing device 20.
Receiving system 10 receives the signal sent from dispensing device 20.Dispensing device 20 has the drive circuit DV utilizing reference clock to carry out Signal coding.Receiving system 10 is input to after the signal of dispensing device 20 transmission is propagated among transmission lines D.
Receiving system 10 has: terminating circuit 1, and it is transfused to the signal received; Treatment circuit 2, it processes in the rear class of terminating circuit 1; And error detect circuit 3, its mistake comprised to the received signal detects.In the apparatus, when mistake being detected by error detect circuit 3, the termination resistance value of terminating circuit 1 is reduced.Figure 1A is the structure of error detect circuit 3 when being positioned at the rear class for the treatment of circuit 2, and Figure 1B is the structure of error detect circuit 3 when being positioned at the prime of terminating circuit 1 or treatment circuit 2.
The terminal configuration of the transmission lines D when transmission signal has the terminating circuit 1 comprising terminal resistance, in multiple circuit, be provided with the resistance value identical with the characteristic impedance of transmission lines.In device in the past, this resistance value depends on specification (such as USB, VbyOneHS, PCIe etc.), and cannot change this resistance value.In addition, if make resistance value diminish in general, power consumption increases, and therefore can not carry out the change reducing resistance value in the past.
In present embodiment, receiving system 10 has the error detect circuit 3 detected the mistake occurred because of noise, and this error detect circuit 3 detects the situation transmitting extraneous noise, particularly discharge noise.When mistake being detected, the resistance value of terminal resistance is reduced.In addition, when utilizing the restriction of coding in dispensing device 20 or transmission data, easily detect mistake, error detection sensitivity can also be improved.
Thus, in satisfied transmission specification and under the state not increasing common power consumption, when transmitting the noise as extraneous noise, burst particularly as discharge noise, carry out the recovery of data transmission in advance, result can improve transmission characteristic.
When discharge noise etc. is superimposed in transmission lines D, charge accumulation in transmission lines D, the current potential change of transmission lines D, thus make a mistake in the circuit of rear class.When error detect circuit 3 detects mistake, need to resend signal from dispensing device 20, but, at transmission lines D by under the state of charging, be difficult to carry out normal signal transmission.Therefore, when mistake being detected by error detect circuit 3, the termination resistance value of terminating circuit 1 is reduced.
In this case, the electric charge be accumulated in transmission lines is quickly released, and transmission lines can promptly return to the state with normal current potential.
In figure ia, error detect circuit 3 is positioned at the rear class for the treatment of circuit 2.By error detect circuit 3 is configured at rear class, compared with the situation being configured at preceding-stage side, in fact more easily detect in signal whether comprise mistake.As the detection method of mistake, there will be a known various method.
Such as, there is following method: in dispensing device 20, carrying out in advance can to the modulation (coding) of the signal that normal mode (pattern) and abnormal patterns differentiate, error detect circuit 3 judges that whether the pattern of the signal received is normal, be judged as in the abnormal situation of result of determination, error detect circuit 3 exports the information representing mistake.
There will be a known several such method.
The error detect circuit 3 of Figure 1A is sampled with the frequency higher than its repetition rate to the received signal, and when the pattern of the value sampled comprises abnormal pattern, error detect circuit 3 is judged as that the pattern of the signal received is abnormal.In addition, error detect circuit 3, when the identical value that the signal received comprises occurs more than stipulated number continuously, also can be judged as that the pattern of the signal received is abnormal.
In addition, when the coding of the run-length-limited codes of the data sampled, detected the mistake of the distance of swimming by the error detect circuit 3 of receiver side.
In addition, as shown in Figure 1B, error detect circuit 3 also can be positioned at the prime for the treatment of circuit 2 or terminating circuit 1.In this case, error detect circuit 3 detects the voltage of the transmission lines D to terminating circuit 1 transmission signal, and when the voltage detected is not in prescribed limit, error detect circuit 3 can export the information representing mistake.
Fig. 2 A and Fig. 2 B is the circuit diagram of the detailed construction that above-mentioned receiving system is shown.In Fig. 2 A and Fig. 2 B, express above-mentioned transmission lines D with 2 transmission lines D1, D2.
As the method for carrying out the change making above-mentioned termination resistance value reduce, resistance circuit network 11 can be used.In this case, the signal received by receiving system 10 is the differential wave transmitted by 2 transmission lines D1, D2.
Terminating circuit 1 is provided with between transmission lines D1 and transmission lines D2.Terminating circuit 1 has resistance R1, R2 of being connected in series between transmission lines D1 and transmission lines D2.Tie point (node) VCOM of resistance R1 and resistance R2, the node VCOM namely between transmission lines is connected with resistance circuit network 11.In resistance circuit network 11, when mistake being detected by error detect circuit 3, carry out making the change that the resistance value of resistance circuit network 11 reduces.
Between transmission lines D1 and node VCOM, resistance R1 is connected in parallel in resistance Ra and switch S 1.In addition, between transmission lines D2 and node VCOM, resistance R2 is connected in parallel in resistance Rb and switch S 2.Node VCOM is connected with the node VCOM1 in resistance circuit network 11.
Between node VCOM1 and power Vcc, be connected with resistance R11, be connected with resistance R12 between node VCOM1 and ground, node VCOM1 is connected with power Vcc with resistance R21 via switch S 3.In addition, the node VCOM1 ground connection via switch S 3, resistance R22 and switch S 4 successively.
When mistake being detected by error detect circuit 3, in fig. 2, by making switch S 1, S2, S3 and S4 connect and the combined resistance value of above-mentioned resistance reduced, thus the terminal resistance body of terminating circuit 1 reduced.When mistake not detected, these switch S 1, S2, S3 and S4 all disconnect.In addition, when normal when cut-off switch S4, electric current can not flow through resistance R21 and resistance R22, so can reduce power consumption.
The magnitude relationship of the resistance value of preferred resistance R1, R2, Ra, Rb, R11, R12, R21 and R22 such as can be set as: R1 and Ra is roughly equal, R2 and Rb is roughly equal, R1=R2, Ra=Rb and R11:R12=R21:R22, but, can various distortion be carried out in the present invention.In addition, about the relation between the above-mentioned parameter represented by roughly equal and equal sign, the relation that a parameter value equals another parameter value ± 30% can be had.
If the change carrying out making the resistance value of resistance circuit network 11 to reduce, then can control the current potential of transmission lines D (D1, D2), thus can change rapidly termination resistance value to discharge the electric charge be accumulated in transmission lines D (D1, D2).
In addition, the treatment circuit 2 of this example has buffer circuit 21 and sample circuit 22, but also can use other treatment circuits such as encoder.The signal of transmission lines D1, D2 is input to sample circuit 22 via buffer circuit 21, and in the case of figure 2 a, Received signal strength exports via error detect circuit 3 as digital value.Error detect circuit 3, when mistake being detected, makes switch S 1 ~ S4 connect.
In addition, in the case of fig. 2b, error detect circuit 3 detects the voltage between transmission lines D1, D2, and when the voltage detected is not in prescribed limit, error detect circuit 3 exports the information representing mistake, and switch S 1 ~ S4 is connected.The current potential of error detect circuit 3 detection node VCOM, when the voltage detected is not in prescribed limit, error detect circuit 3 also can export the information representing mistake, and switch S 1 ~ S4 is connected.
In addition, about the method changing termination resistance value, also additive method can be considered as follows.
Fig. 3 is the circuit diagram of the variation that terminating circuit is shown.
Fig. 3 A be above-mentioned node VCOM via switch S 31 example of ground connection, when mistake being detected, switch S 31 being connected, under other usual states, switch S 31 being disconnected.
Fig. 3 B is the example that above-mentioned node VCOM is connected with power Vcc via switch S 31, when mistake being detected, switch S 31 being connected, under other usual states, switch S 31 being disconnected.
Fig. 3 C be above-mentioned node VCOM via switch S 31 and resistance R the example of ground connection, when mistake being detected, switch S 31 being connected, under other usual states, switch S 31 being disconnected.
Fig. 3 D is the example that above-mentioned node VCOM is connected with power Vcc with resistance R via switch S 31, when mistake being detected, switch S 31 being connected, under other usual states, switch S 31 being disconnected.
Fig. 3 E to be above-mentioned node VCOM via switch S 31 be connected with power Vcc with resistance R11 and via switch S 31 and resistance R12 the example of ground connection, when mistake being detected, switch S 31 being connected, under other usual states, switch S 31 being disconnected.
In addition, as illustrated in Figure 3 F, also the electric charge be accumulated in transmission lines can directly be discharged.
That is, receiving system has: terminating circuit 1, and it is transfused to the signal received; Treatment circuit 2, it processes in the rear class of terminating circuit 1; And error detect circuit 3, its mistake comprised to the received signal detects, when mistake being detected by error detect circuit 3, transmission lines D1, D2 are connected with fixed potential, discharge to make the electric charge be accumulated in transmission lines D1, the D2 of the input side be connected with terminating circuit 1.Transmission lines D1 is connected with power Vcc via switch S 3a, and transmission lines D2 is ground connection via switch S 3b.If make transmission lines D be connected with these fixed potentials, then because the electric charge be accumulated in transmission lines D1, D2 is promptly discharged, so receiving system 10 promptly can return to normal condition.When mistake being detected, switch S 3a and switch S 3b being connected, under other usual states, switch S 3a and switch S 3b being disconnected.
In addition, in such a configuration, differential input is illustrated, but when signal is input to the such structure of buffer circuit 21 via single transmission lines, also can applies the present invention.That is, as shown in Figure 3 G, between transmission lines D and node VCOM, resistance R1 is connected in parallel in resistance Ra and switch S 1, can on node VCOM the circuit structure of connection layout 3A ~ Fig. 3 E.
In addition, the current potential of node VCOM is determined by resistance circuit network 11.Even if when resistance value reduces, the current potential that also can maintain node VCOM is constant, has the effect recovering in advance to transmit.
As described above, according to above-mentioned circuit structure, by only just making termination resistance value reduce when mistake being detected, electric charge can be discharged according to termination resistance value from terminating circuit 1.Normally can not transmit data before electric charge releases, again can transmit data after electric charge releases.Termination resistance value is larger, time then again normally needed for restoring data is longer, but in the present invention, termination resistance value is diminished, therefore, the time of electric charge release can be shortened, and put forward high-tension convergence when meeting specification and do not change power when usually working, thus can transmission characteristic be improved.
Claims (9)
1. a receiving system, is characterized in that, described receiving system has:
Terminating circuit, it is transfused to the signal received;
Treatment circuit, it processes in the rear class of described terminating circuit; And
Error detect circuit, its mistake comprised to the received signal detects,
When mistake being detected by described error detect circuit, the termination resistance value of described terminating circuit is reduced.
2. receiving system according to claim 1, is characterized in that,
Described error detect circuit is positioned at the rear class of described treatment circuit.
3. receiving system according to claim 1, is characterized in that,
Described error detect circuit judges that whether the pattern of the signal received is normal, and be judged as in the abnormal situation of result of determination, described error detect circuit exports the information representing mistake.
4. receiving system according to claim 3, is characterized in that,
Described error detect circuit, when the identical value that the signal received comprises occurs more than stipulated number continuously, is judged as that the pattern of the signal received is abnormal.
5. receiving system according to claim 3, is characterized in that,
Described error detect circuit is sampled with the frequency higher than its repetition rate to the received signal, and when the pattern of the value sampled comprises abnormal pattern, described error detect circuit is judged as that the pattern of the signal received is abnormal.
6. receiving system according to claim 1, is characterized in that,
Described error detect circuit is positioned at the prime of described terminating circuit or described treatment circuit.
7. receiving system according to claim 6, is characterized in that,
Described error detect circuit detects the voltage to the transmission lines of described terminating circuit transmission signal, and when the voltage detected is not in prescribed limit, described error detect circuit exports the information representing mistake.
8. receiving system according to claim 1, is characterized in that,
The described signal received is the differential wave transmitted by 2 transmission lines,
Described terminating circuit has resistance circuit network, and described resistance circuit network is connected to the node between described transmission lines,
When mistake being detected by described error detect circuit, described resistance circuit network makes the resistance value of described resistance circuit network reduce.
9. a receiving system, is characterized in that, described receiving system has:
Terminating circuit, it is transfused to the signal received;
Treatment circuit, it processes in the rear class of described terminating circuit; And
Error detect circuit, its mistake comprised to the received signal detects,
When mistake being detected by described error detect circuit, described transmission lines being connected with fixed potential, discharging to make the electric charge be accumulated in the transmission lines of the input side be connected with described terminating circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2014102335A JP6371111B2 (en) | 2014-05-16 | 2014-05-16 | Receiver |
| JP2014-102335 | 2014-05-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105099408A true CN105099408A (en) | 2015-11-25 |
| CN105099408B CN105099408B (en) | 2019-10-25 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510245837.7A Active CN105099408B (en) | 2014-05-16 | 2015-05-14 | Reception device |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US9712344B2 (en) |
| JP (1) | JP6371111B2 (en) |
| CN (1) | CN105099408B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9541990B2 (en) | 2015-04-21 | 2017-01-10 | Cypress Semiconductor Corporation | Asynchronous transceiver for on-vehicle electronic device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100275084A1 (en) * | 2009-04-27 | 2010-10-28 | Fujitsu Limited | Transmission device, receiving circuit and control method of transmission device |
| WO2014049752A1 (en) * | 2012-09-26 | 2014-04-03 | 富士通株式会社 | Data transmission device and data transmission method |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3783281B2 (en) * | 1996-02-08 | 2006-06-07 | ソニー株式会社 | Data decoding device |
| JP3788928B2 (en) * | 2001-11-01 | 2006-06-21 | 株式会社ルネサステクノロジ | Resistance variable |
| JP4179883B2 (en) * | 2003-01-08 | 2008-11-12 | Ｎｅｃエレクトロニクス株式会社 | Termination resistor device, data transmission device, and termination resistor circuit inspection method |
| US7205789B1 (en) * | 2004-08-26 | 2007-04-17 | Chris Karabatsos | Termination arrangement for high speed data rate multi-drop data bit connections |
| JP4798618B2 (en) * | 2006-05-31 | 2011-10-19 | ルネサスエレクトロニクス株式会社 | Output circuit and semiconductor integrated circuit device |
| JP2008219813A (en) | 2007-03-07 | 2008-09-18 | Sharp Corp | Lvds receiver, lvds receiving method, lvds data transmission system, and semiconductor device |
| JP5465376B2 (en) * | 2007-10-18 | 2014-04-09 | ピーエスフォー ルクスコ エスエイアールエル | Semiconductor device and driver control method |
| JP4482048B2 (en) * | 2008-05-30 | 2010-06-16 | 株式会社日本自動車部品総合研究所 | Receiver |
| US8760188B2 (en) * | 2011-06-30 | 2014-06-24 | Silicon Image, Inc. | Configurable multi-dimensional driver and receiver |
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2014
- 2014-05-16 JP JP2014102335A patent/JP6371111B2/en active Active
-
2015
- 2015-05-14 US US14/712,298 patent/US9712344B2/en active Active
- 2015-05-14 CN CN201510245837.7A patent/CN105099408B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100275084A1 (en) * | 2009-04-27 | 2010-10-28 | Fujitsu Limited | Transmission device, receiving circuit and control method of transmission device |
| WO2014049752A1 (en) * | 2012-09-26 | 2014-04-03 | 富士通株式会社 | Data transmission device and data transmission method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2015220579A (en) | 2015-12-07 |
| US9712344B2 (en) | 2017-07-18 |
| CN105099408B (en) | 2019-10-25 |
| US20150333869A1 (en) | 2015-11-19 |
| JP6371111B2 (en) | 2018-08-08 |
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