CN105099174A - Boosting circuit - Google Patents
Boosting circuit Download PDFInfo
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- CN105099174A CN105099174A CN201510435338.4A CN201510435338A CN105099174A CN 105099174 A CN105099174 A CN 105099174A CN 201510435338 A CN201510435338 A CN 201510435338A CN 105099174 A CN105099174 A CN 105099174A
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Abstract
The embodiment of the invention relates to a boosting circuit. The circuit comprises a battery, an inductor, a first switch, a second switch, a first capacitor, a control circuit and a voltage feedback circuit, wherein one end of the inductor is coupled to an anode of the battery, the other end of the inductor is coupled to a cathode of the battery through the first switch and is further coupled to the first capacitor and the cathode of the battery through the second switch, and the second switch and the first capacitor are coupled in series; one end of the voltage feedback circuit is coupled to the other end of the inductor; the other end of the voltage feedback circuit is coupled to the control circuit; the control circuit is used for controlling on/off of the first switch or the second switch according to the level of an enable signal; when the enable signal is changed to a second level from a first level, the control circuit controls the first switch and the second switch to be alternatively closed, and the first capacitor charges the battery; and when the enable signal is at the second level and an output voltage is equal to an input voltage, the control circuit controls the first switch and the second switch to be open, and the boosting circuit stops working.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a booster circuit.
Background
Conventional dc-dc converters do not have an energy recovery function. In some systems, the dc-dc converter and the load are operated intermittently to save energy. The charge on the output capacitor is wasted each time the operation is turned off.
Disclosure of Invention
The invention aims to solve the defects in the prior art, and improves the structure of the prior direct current-direct current converter, so that energy on a capacitor of an intermittent boosting type direct current-direct current converter can be partially recovered, and the efficiency is improved.
To achieve the above object, the present invention provides a booster circuit, comprising: the circuit comprises a battery, an inductor, a first switch, a second switch, a first capacitor, a control circuit and a voltage feedback circuit;
one end of the inductor is coupled with the positive electrode of the battery; the other end of the inductor is coupled with the negative electrode of the battery through a first switch; the other end of the inductor is also coupled with the negative electrode of the battery through a second switch and a first capacitor, wherein the second switch is coupled with the first capacitor in series; one end of the voltage feedback circuit is coupled with the other end of the inductor; the other end of the voltage feedback circuit is coupled with the control circuit; the voltage feedback circuit is grounded;
the control circuit controls the first switch or the second switch to be switched on or switched off according to the level of the enabling signal;
when the enable signal changes from a first level to a second level, the control circuit controls the first switch and the second switch to be closed alternately, and the first capacitor and the parasitic capacitor of the external load charge the battery;
when the enable signal is at the second level and the output voltage is equal to the input voltage, the control circuit controls the first switch and the second switch to be switched off, and the booster circuit stops working.
Preferably, the control circuit controls the first switch and the second switch to be alternately closed during a period when the enable signal changes from the first level to the second level, and the first capacitor charges the battery, including:
during a period when the enable signal received by the control circuit changes from a first level to a second level, in one period, the control circuit controls the first switch to be opened and controls the second switch to be closed, and the first capacitor and the parasitic capacitor of the load supply energy to the inductor; the control circuit controls the first switch to be closed, and when the second switch is opened, the inductor supplies energy to the battery.
Preferably, the control circuit comprises: an energy recovery control circuit; wherein,
the energy recovery control circuit includes: the circuit comprises a comparator, a first trigger, a second trigger, a first pulse generator, a second pulse generator, a third pulse generator, a delayer, a first logic circuit, a second logic circuit, a third logic circuit and a fourth logic circuit;
the input end of the comparator receives the divided voltage signal and the reference voltage; the output end of the comparator is connected with the second input end of the first logic circuit; enabling signals are respectively input to a first input end of the first logic circuit and a clock signal input end of the first trigger; the input voltage is respectively input to the data end of the first trigger and the data end of the second trigger; the output end of the first logic circuit is connected with the reset end of the first trigger; the output end Q of the first trigger is connected with the second input end of the fourth logic circuit through the second pulse generator; the output end of the fourth logic circuit is connected with the third input end of the third logic circuit; the output end of the third logic circuit is connected with the clock signal input end of the second trigger and the first input end of the fourth logic circuit, and the output end of the third logic circuit outputs a first output signal; the output end Q of the second trigger outputs a second output signal; the output end QB of the first trigger is connected with the second input end of the third logic circuit and the second input end of the second logic circuit; the output end of the third logic circuit is connected with the input end of the first pulse generator through a delayer; the output end of the first pulse generator is connected with the first input end of the third logic circuit; the reverse current detection signal is respectively input into the input end of the third pulse generator and the first input end of the second logic circuit; the output end of the third pulse generator is connected with the third input end of the fourth pulse generator; the output end of the second logic circuit is connected with the reset end of the second trigger.
Preferably, the control circuit further comprises: a first driver and a second driver;
the first output signal controls the on or off of the first switch through the first driver; the second output signal controls the opening or closing of the second switch through the second driver, wherein the first switch and the second switch are alternately closed.
Preferably, when the enable signal is at a first level, the control circuit controls the first switch and the second switch to be closed alternately, and the battery supplies power to the external load;
preferably, when the enable signal is at a first level, the control circuit controls the first switch and the second switch to be closed alternately, and the battery supplies power to the external load, and includes:
when the enable signal received by the control circuit is at a first level, in one period, the control circuit controls the first switch to be closed and controls the second switch to be opened, and the battery supplies energy to the inductor; the control circuit controls the first switch to be opened and controls the second switch to be closed, and the inductor supplies energy to the first capacitor and the external load.
Preferably, the control circuit further comprises: a negative feedback control circuit, a fifth logic circuit and a sixth logic circuit;
the output end of the negative feedback control circuit is connected with the second input end of the fifth logic circuit and the first input end of the sixth logic circuit; the first input end of the fifth logic circuit is connected with the output end of the third logic circuit; the output end of the fifth logic circuit is connected with the input end of the first driver; a second input end of the sixth logic circuit is connected with an output end Q of the second trigger; the output terminal of the sixth logic circuit is connected to the input terminal of the second driver.
Preferably, the voltage feedback circuit includes: a first resistor and a second resistor;
one end of the first resistor is grounded; the other end of the first resistor is coupled with one end of the second resistor and the control circuit; the other end of the second resistor is coupled with one end of the first switch and one end of the first capacitor.
Preferably, the booster circuit further includes: a second capacitor;
the second capacitor is coupled in parallel with the battery.
Preferably, the first level is a high level and the second level is a low level.
According to the boost circuit provided by the invention, through improving the structure of the direct current-direct current converter, the control circuit is utilized to control the first switch and the second switch in the boost circuit to be alternatively closed, and the energy on the first capacitor and the load parasitic capacitor is recovered under the synchronous voltage reduction mode, so that the energy on the output capacitor is recovered, the battery at the input end is charged, the system efficiency is improved, and the energy is saved.
Drawings
Fig. 1 is a circuit diagram of a voltage boosting circuit according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a voltage feedback circuit according to an embodiment of the present invention;
fig. 3 is a schematic circuit diagram of a control circuit according to an embodiment of the present invention;
fig. 4 is a waveform diagram of operations of voltage nodes of a voltage boosting circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
For the convenience of understanding of the embodiments of the present invention, the following description will be further explained with reference to specific embodiments, which are not to be construed as limiting the embodiments of the present invention.
Fig. 1 is a circuit diagram of a voltage boost circuit according to an embodiment of the present invention, as shown in fig. 1, the voltage boost circuit includes: a battery BAT, an inductor L1, a first switch S1, a second switch S2, a first capacitor C1, a control circuit 110, and a voltage feedback circuit 120;
one end of the inductor L1 is coupled to the positive electrode of the battery BAT; the other end of the inductor L1 is coupled to the negative terminal of the battery BAT via a first switch S1; the other end of the inductor L1 is further coupled to the negative electrode of the battery BAT through a second switch S2 and a first capacitor C1, wherein the second switch S2 is coupled in series with the first capacitor C1; one terminal of the voltage feedback circuit 120 is coupled to the other terminal of the inductor L1; the other end of the voltage feedback circuit 120 is coupled to the control circuit 110; voltage feedback circuit 120 is grounded;
the control circuit 110 controls the first switch S1 or the second switch S2 to be closed or opened according to the level of the enable signal EN;
during a period when the enable signal EN changes from the first level to the second level, the control circuit 110 controls the first switch S1 and the second switch S2 to be alternately closed, and the first capacitor C1 and the parasitic capacitor of the external load charge the battery BAT;
specifically, during a period when the enable signal EN changes from the first level to the second level, the control circuit 110 controls the first switch S1 and the second switch S2 to be alternately closed, and the parasitic capacitance of the external load of the first capacitor C1 charges the battery BAT, including:
during a period when the enable signal EN received by the control circuit 110 changes from the first level to the second level, in one period, the control circuit 110 controls the first switch S1 to be opened and controls the second switch S2 to be closed, and the first capacitor C1 and the parasitic capacitor of the load supply energy to the inductor L1; when the control circuit 110 controls the first switch S1 to be closed and the second switch S2 to be open, the inductor L1 supplies energy to the battery BAT.
When the enable signal EN is at the second level and the output voltage is equal to the input voltage, the control circuit 110 controls the first switch S1 and the second switch S2 to be turned off, and the boosting circuit stops operating.
Alternatively, when the enable signal EN is at the first level, the control circuit 110 controls the first switch S1 and the second switch S2 to be alternately closed, and the battery BAT supplies power to the external load.
Specifically, when the enable signal EN is at the first level, the control circuit 110 controls the first switch S1 and the second switch S2 to be alternately closed, and the battery BAT supplies power to an external load, including:
when the enable signal EN received by the control circuit 110 is at the first level, in one period, the control circuit 110 controls the first switch S1 to be closed and controls the second switch S2 to be opened, and the battery BAT supplies energy to the inductor L1; the control circuit 110 controls the first switch S1 to open and the second switch S2 to close, and the inductor L1 supplies energy to the first capacitor C1 and the external load.
Specifically, the first level is a high level, and the second level is a low level.
Optionally, the boost circuit further comprises: a second capacitance C2;
a second capacitor C2 is coupled in parallel with battery BAT.
Note that the control circuit 110 controls the first switch S1 and the second switch S2 to be closed or opened. When the enable signal EN is at a high level, the control circuit 110 controls the first switch S1 and the second switch S2 to be alternately closed, so that the boost circuit works in a synchronous boost mode to boost the voltage of the battery bat to supply power to the output load; when the enable signal EN is just changed into a high level and changed into a low level, the control circuit 110 controls the first switch S1 and the second switch S2 to be alternately closed, so that the voltage boosting circuit works in a synchronous voltage reduction mode, energy on the first capacitor C1 and a load parasitic capacitor is recycled, and the battery bat at the input end is charged; when the enable signal EN becomes low level and the energy on the output capacitor is recovered until the output voltage is equal to the input voltage, the energy recovery function is stopped and the whole booster circuit system stops working. When the enable signal EN is at a high level, the booster circuit works normally; when the enable signal EN is changed from a high level to a low level, the booster circuit starts an energy recovery mode to recover part of energy on the output capacitor and charge the battery BAT at the input end; when the enable signal EN is low, the booster circuit stops operating.
According to the boost circuit provided by the invention, through improving the structure of the DC-DC converter, the control circuit 110 is used for controlling the first switch S1 and the second switch S2 in the boost circuit to be alternatively closed, and the energy on the first capacitor C1 and the load parasitic capacitor is recycled under the synchronous buck mode, so that the energy on the output capacitor is recycled, the battery BAT at the input end is charged, the system efficiency is improved, and the energy is saved.
Fig. 2 is a circuit diagram of a voltage feedback circuit according to an embodiment of the present invention, and as shown in fig. 2, the voltage feedback circuit 220 includes: a first resistor R1 and a second resistor R2;
one end of the first resistor R1 is grounded; the other end of the first resistor R1 is coupled with one end of the second resistor R2 and the control circuit 110; the other end of the second resistor R2 is coupled to one end of the first switch S1 and one end of the first capacitor C1.
It should be noted that the voltage feedback circuit 220 may be implemented by any circuit that performs a voltage division function, and is not limited herein.
Fig. 3 is a schematic circuit diagram of a control circuit according to an embodiment of the present invention, and in this example, a first flip-flop and a second flip-flop are D flip-flops, a first logic circuit, a second logic circuit, a fifth logic circuit, and a sixth logic circuit are or gates, and a third logic circuit, and a fourth logic circuit are nor gates, for example, where the D flip-flop is a D flip-flop that is reset at a high level and triggered by a clock falling edge, that is, when a reset terminal is at a high level, an output terminal Q is reset at a low level, an output terminal QB is reset at a high level, and a falling edge of a clock signal is triggered.
As shown in fig. 3, the control circuit includes: an energy recovery control circuit 311, a first driver DRV1, a second driver DRV2, a negative feedback control circuit 312, a fifth logic circuit or3, and a sixth logic circuit or 4;
the energy recovery control circuit 311 includes: a comparator CM, a first flip-flop ffdf1, a second flip-flop ffdf1, a first pulse generator pulse1, a second pulse generator pulse2, a third pulse generator pulse3, a delay, a first logic circuit or1, a second logic circuit or2, a third logic circuit nor1, and a fourth logic circuit nor 2;
the input end of the comparator CM receives a divided voltage signal FB and a reference voltage REF respectively; the output end of the comparator CM is connected with the second input end of the first logic circuit or 1; the enable signal EN is respectively input to a first input terminal of the first logic circuit or1 and a clock signal input terminal of the first flip-flop ffdf 1; the input voltage VIN is respectively input to the data terminal of the first flip-flop ffdf1 and the data terminal of the second flip-flop ffdf 2; the output end of the first logic circuit or1 is connected to the reset end of the first flip-flop ffdf 1; the output Q of the first flip-flop ffdf1 is connected to the second input of the fourth logic circuit nor2 via a second pulse generator pulse 2; the output terminal of the fourth logic circuit nor2 is connected to the third input terminal of the third logic circuit nor 1; an output end of the third logic circuit nor1 is connected with a clock signal input end of the second flip-flop ffdf2 and a first input end of the fourth logic circuit nor2, and an output end of the third logic circuit nor1 outputs a first output signal QS 1; an output terminal Q of the second flip-flop ffdf2 outputs a second output signal QS 2; the output QB of the first flip-flop ffdf1 is connected to the second input terminal of the third logic circuit nor1 and the second input terminal of the second logic circuit or 2; the output of the third logic circuit nor1 is connected via a delay to the input of the first pulse generator pulse 1; the output end of the first pulse generator pulse1 is connected with the first input end of the third logic circuit nor 1; the reverse current detection signals are respectively input into the input end of the third pulse generator pulse3 and the first input end of the second logic circuit or 2; the output end of the third pulse generator pulse3 is connected with the third input end of the fourth pulse generator; the output of the second logic circuit or2 is connected to the reset terminal of the second flip-flop ffdf 2.
The first output signal QS1 controls the closing or opening of the first switch S1 through the first driver DRV 1; the second output signal QS2 controls the opening or closing of the second switch S2 through the second driver DRV2, wherein the first switch S1 and the second switch S2 are alternately closed.
The output end of the negative feedback control circuit 312 is connected with the second input end of the fifth logic circuit or3 and the first input end of the sixth logic circuit or 4; a first input end of the fifth logic circuit or3 is connected with an output end of the third logic nor1 circuit; the output of the fifth logic circuit or3 is connected to the input of the first driver DRV 1; a second input terminal of the sixth logic circuit or4 is connected to the output terminal Q of the second flip-flop ffdf 2; the output of the sixth logic circuit or4 is connected to the input of the second driver DRV 2.
It should be noted that, in the embodiment of the present invention, the negative feedback control circuit 312 may be implemented by using the prior art, and the negative feedback control circuit may include: the error amplifier EA, the comparator PWM and the logic control circuit are not described again for brevity of description
The specific working process is as follows:
when the enable signal EN is at a high level, the signal rst1 passing through the first logic circuit or1 is at a high level, and the first flip-flop ffdf1 is reset, so that the output signal QONB at the output end QB of the first flip-flop ffdf1 is at a high level, and the first output signal QS1 passing through the third logic circuit nor1 is output at a low level; the signal rst2 of the output signal QONB passing through the second logic circuit or2 is also high, the second flip-flop ffdf1 is reset, and the second output signal QS2 is low. The first output signal QS1 and the second output signal QS2 are connected to or gate or3 and or gate or4, and when EN is high, both the first output signal QS1 and the second output signal QS2 are low, which does not affect the output of or gate or3 and or gate 4, i.e. at this time, the output of or gate or3 and or gate or4 is controlled by HDP and LDP only. When the enable signal EN is high, the DVS1 and DVS2 output by the energy recovery control circuit are completely controlled by the negative feedback control circuit.
The negative feedback control circuit operates in the same manner as the prior art. When the divided voltage FB is lower than the reference voltage REF, the output EAO voltage of the error amplifier EA will rise, the duty ratio of the PWM output signal D will increase, the duty ratio of LDP increases and the duty ratio of HDP decreases, the duty ratio of DVS2 increases and the duty ratio of DVS1 decreases, the output voltage VO increases, and the voltage of the divided signal FB through the first resistor R1 and the second resistor R2 rises;
when the divided voltage FB is higher than the reference voltage REF, the output EAO voltage of the error amplifier EA will decrease, the duty ratio of the PWM output signal D will decrease, the duty ratio of LDP decreases and the duty ratio of HDP increases, the duty ratio of DVS2 decreases and the duty ratio of DVS1 increases, the output voltage VO decreases, and the voltage of the divided signal FB through the first resistor R1 and the second resistor R2 decreases. So that it exhibits a negative feedback effect. When the negative feedback is stable, the voltage value of the divided signal FB is equal to the voltage value of the reference voltage REF, so that the output voltage VO is REF (R1+ R2)/R1, where REF is the voltage value of the reference voltage REF, and R1 and R2 are the resistance values of the resistors R1 and R2, respectively.
When the enable signal EN changes from high level to low level, the booster circuit enters an energy recovery state. When the enable signal EN changes from high level to low level, a falling edge is generated to trigger the first flip-flop ffdf1, so that the signal QON output from the output terminal Q changes from low level to high level, a narrow pulse with short high level time is generated through the second flip-flop pulse2, the output a1 of the fourth logic circuit nor2 is set to low level, at this time, the output QONB of the output terminal QB of the first flip-flop ffdf1 also changes to low level, the initial state of the output signal QS1 is low level, and the initial state of the signal po1 after passing through the delay and the first pulse1 is also low level, therefore, the first output signal QS1 output by the third logic circuit nor1 will first go high, and the first output signal QS1 goes through the delay, then goes through the first pulse generator pulse1 to generate a narrow pulse po1 at its rising edge, so that the first output signal QS1 will be reset to low level by the third logic circuit nor 1. The time for which the first output signal QS1 keeps high is determined by the delay time of the delay. When the first output signal QS1 changes from high to low, the second flip-flop ffdf2 is triggered to set the output second output signal QS2 to high.
When the reverse current detection signal RCP changes from low level to high level, indicating that the inductor current drops to zero, in order to avoid generating reverse current, the reverse current detection signal RCP generates a narrow pulse signal po3 at its rising edge through the third pulse generator pulse3, and after passing through the fourth logic circuit nor2, the a1 signal is reset to low level, at this time, since po1, QONB, a1 are all at low level, the first output signal QS1 changes to high level again, so that the first output signal QS1 and the second output signal QS2 work alternately at high level, the energy on the first capacitor C1 is continuously transferred to the input terminal battery to charge the battery, until the output voltage VO drops below the input voltage VIN, the comparator CM1 changes from low level to high level, and the first logic circuit 11 signal resets the first flip-flop ffdf1, the output signal QON at the output terminal Q changes to low level, the output signal QONB changes to a high level, the output signal QON passes through the third logic circuit nor1 and then outputs the first output signal QS1 to a low level, the output signal QONB passes through the second logic circuit or2 and then the rst2 signal changes to a high level, the second flip-flop ffdf2 is reset, and the output signal QS2 changes to a low level.
After the enable signal EN is at a low level, the outputs HDP and LDP of the control logic control circuit are both at a low level, after a period of energy recovery operation, when the output voltage VO drops to the input voltage VIN, the first output signal QS1 and the second output signal QS2 are also at a low level, after passing through the or gates or3 and or4, the HDA and LDA are both at a low level, after passing through the drivers DRV1 and DRV2, the DVS1 and DVS2 are both at a low level, the first switch S1 and the second switch S2 are both turned off, and the boost circuit completely stops working.
The operating waveforms of the voltage nodes during the operation of the boost circuit are shown in fig. 4.
According to the boost circuit provided by the invention, through improving the structure of the DC-DC converter, the control circuit 110 is used for controlling the first switch S1 and the second switch S2 in the boost circuit to be alternatively closed, and the energy on the first capacitor C1 and the load parasitic capacitor is recycled under the synchronous buck mode, so that the energy on the output capacitor is recycled, the battery BAT at the input end is charged, the system efficiency is improved, and the energy is saved.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A voltage boost circuit, characterized in that the voltage boost circuit comprises: the circuit comprises a battery, an inductor, a first switch, a second switch, a first capacitor, a control circuit and a voltage feedback circuit;
one end of the inductor is coupled with the positive electrode of the battery; the other end of the inductor is coupled with the negative electrode of the battery through the first switch; the other end of the inductor is coupled with the negative electrode of the battery through the second switch and the first capacitor, wherein the second switch is coupled with the first capacitor in series; one end of the voltage feedback circuit is coupled with the other end of the inductor; the other end of the voltage feedback circuit is coupled with the control circuit; the voltage feedback circuit is grounded;
the control circuit controls the first switch or the second switch to be switched on or switched off according to the level of an enable signal;
the control circuit controls the first switch and the second switch to be closed alternately in a period of time when the enable signal changes from a first level to a second level, and the first capacitor and the parasitic capacitor of the external load charge the battery;
when the enable signal is at a second level and the output voltage is equal to the input voltage, the control circuit controls the first switch and the second switch to be switched off, and the boosting circuit stops working.
2. The boost circuit of claim 1, wherein the control circuit controls the first switch and the second switch to be alternately closed during a period of time when the enable signal changes from a first level to a second level, and the first capacitor charges the battery, comprising:
the control circuit controls the first switch to be opened and controls the second switch to be closed in a period when an enable signal received by the control circuit changes from a first level to a second level, and the first capacitor and the parasitic capacitor of the external load supply energy to the inductor; the control circuit controls the first switch to be closed, and when the second switch is opened, the inductor supplies energy to the battery.
3. The booster circuit according to claim 1 or2, wherein the control circuit comprises: an energy recovery control circuit; wherein,
the energy recovery control circuit includes: the circuit comprises a comparator, a first trigger, a second trigger, a first pulse generator, a second pulse generator, a third pulse generator, a delayer, a first logic circuit, a second logic circuit, a third logic circuit and a fourth logic circuit;
the input end of the comparator receives the divided voltage signal and the reference voltage; the output end of the comparator is connected with the second input end of the first logic circuit; enabling signals are respectively input to a first input end of the first logic circuit and a clock signal input end of the first trigger; the input voltage is respectively input to the data end of the first trigger and the data end of the second trigger; the output end of the first logic circuit is connected with the reset end of the first trigger; the output end Q of the first trigger is connected with the second input end of the fourth logic circuit through the second pulse generator; the output end of the fourth logic circuit is connected with the third input end of the third logic circuit; the output end of the third logic circuit is connected with the clock signal input end of the second trigger and the first input end of the fourth logic circuit, and the output end of the third logic circuit outputs a first output signal; the output end Q of the second trigger outputs a second output signal; an output end QB of the first flip-flop is connected with a second input end of the third logic circuit and a second input end of the second logic circuit; the output end of the third logic circuit is connected with the input end of the first pulse generator through the delayer; the output end of the first pulse generator is connected with the first input end of the third logic circuit; the reverse current detection signals are respectively input into the input end of the third pulse generator and the first input end of the second logic circuit; the output end of the third pulse generator is connected with the third input end of the fourth pulse generator; and the output end of the second logic circuit is connected with the reset end of the second trigger.
4. The booster circuit according to claim 3, wherein the control circuit further comprises: a first driver and a second driver;
the first output signal controls the first switch to be closed or opened through the first driver; the second output signal controls the second switch to be opened or closed through the second driver, wherein the first switch and the second switch are alternately closed.
5. The boost circuit of claim 1, wherein when the enable signal is at a first level, the control circuit controls the first switch and the second switch to be alternately closed, and the battery supplies power to an external load.
6. The boost circuit of claim 5, wherein when the enable signal is at a first level, the control circuit controls the first switch and the second switch to be alternately closed, and the battery supplies power to an external load, comprising:
when the enable signal received by the control circuit is at a first level, in one period, the control circuit controls the first switch to be closed and controls the second switch to be opened, and the battery supplies energy to the inductor; the control circuit controls the first switch to be open and controls the second switch to be closed, and the inductor supplies energy to the first capacitor and the external load.
7. A boost circuit in accordance with claim 5 or 6, wherein said control circuit further comprises: a negative feedback control circuit, a fifth logic circuit and a sixth logic circuit;
the output end of the negative feedback control circuit is connected with the second input end of the fifth logic circuit and the first input end of the sixth logic circuit; a first input end of the fifth logic circuit is connected with an output end of the third logic circuit; the output end of the fifth logic circuit is connected with the input end of the first driver; a second input end of the sixth logic circuit is connected with an output end Q of the second trigger; and the output end of the sixth logic circuit is connected with the input end of the second driver.
8. The booster circuit according to claim 1, wherein the voltage feedback circuit comprises: a first resistor and a second resistor;
one end of the first resistor is grounded; the other end of the first resistor is coupled with one end of the second resistor and the control circuit; the other end of the second resistor is coupled with one end of the first switch and one end of the first capacitor.
9. The booster circuit according to claim 1, characterized in that the booster circuit further comprises: a second capacitor;
the second capacitor is coupled in parallel with the battery.
10. The booster circuit according to claim 1, wherein the first level is a high level, and the second level is a low level.
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