CN105099174A - Boosting circuit - Google Patents
Boosting circuit Download PDFInfo
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- CN105099174A CN105099174A CN201510435338.4A CN201510435338A CN105099174A CN 105099174 A CN105099174 A CN 105099174A CN 201510435338 A CN201510435338 A CN 201510435338A CN 105099174 A CN105099174 A CN 105099174A
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Abstract
The embodiment of the invention relates to a boosting circuit. The circuit comprises a battery, an inductor, a first switch, a second switch, a first capacitor, a control circuit and a voltage feedback circuit, wherein one end of the inductor is coupled to an anode of the battery, the other end of the inductor is coupled to a cathode of the battery through the first switch and is further coupled to the first capacitor and the cathode of the battery through the second switch, and the second switch and the first capacitor are coupled in series; one end of the voltage feedback circuit is coupled to the other end of the inductor; the other end of the voltage feedback circuit is coupled to the control circuit; the control circuit is used for controlling on/off of the first switch or the second switch according to the level of an enable signal; when the enable signal is changed to a second level from a first level, the control circuit controls the first switch and the second switch to be alternatively closed, and the first capacitor charges the battery; and when the enable signal is at the second level and an output voltage is equal to an input voltage, the control circuit controls the first switch and the second switch to be open, and the boosting circuit stops working.
Description
Technical field
The present invention relates to electronic technology field, particularly relate to a kind of booster circuit.
Background technology
Traditional DC-to-DC converter does not have energy recovery function.In order to save energy in some system, DC-to-DC converter and load are all service intermittent mode.During each closedown work, the electric charge in output capacitance is wasted.
Summary of the invention
The object of the invention is, in order to solve prior art above shortcomings, to improve existing DC-to-DC converter structure, the energy on the Boost DC of service intermittent-direct current transducer electric capacity can be partly recovered, thus the method for raising the efficiency.
For achieving the above object, the invention provides a kind of booster circuit, this booster circuit comprises: battery, inductance, the first switch, second switch, the first electric capacity, control circuit and voltage feedback circuit;
One end of inductance and the positive pole of battery are coupled; The other end of inductance is coupled by the negative pole of the first switch and battery; The other end of inductance is also coupled by the negative pole of second switch and the first electric capacity and battery, and wherein, second switch is coupled with the first capacitances in series; One end of voltage feedback circuit and the other end of inductance are coupled; The other end and the control circuit of voltage feedback circuit are coupled; Voltage feedback circuit ground connection;
Control circuit, according to the level of enable signal, controls the closed or disconnection of the first switch or second switch;
In a period of time when enable signal becomes second electrical level from the first level, control circuit controls the first switch and second switch is alternately closed, and the parasitic capacitance of the first electric capacity and external loading is charged to battery;
When enable signal is second electrical level, and when output voltage equals input voltage, control circuit controls the first switch and second switch disconnects, and booster circuit quits work.
Preferably, in a period of time when enable signal becomes second electrical level from the first level, control circuit controls the first switch and second switch is alternately closed, and the first electric capacity charges to battery, comprising:
In a period of time when the enable signal that control circuit receives becomes second electrical level from the first level, in one cycle, control circuit controls the first switch and disconnects, and controls second switch and close, and the parasitic capacitance of the first electric capacity and load is by Power supply inductance; Control circuit controls the first switch and closes, and when second switch disconnects, inductance is by Power supply battery.
Preferably, control circuit comprises: energy regenerating control circuit; Wherein,
Energy regenerating control circuit comprises: comparator, the first trigger, the second trigger, the first pulse generator, the second pulse generator, the 3rd pulse generator, delayer, the first logical circuit, the second logical circuit, the 3rd logical circuit and the 4th logical circuit;
The input of comparator receives voltage division signal and reference voltage; The output of comparator is connected with the second input of the first logical circuit; Enable signal is input to the first input end of the first logical circuit and the clock signal input terminal of the first trigger respectively; Input voltage is input to the data terminal of the first trigger and the data terminal of the second trigger respectively; The output of the first logical circuit is connected with the reset terminal of the first trigger; The output Q of the first trigger is connected by second input of the second pulse generator with the 4th logical circuit; The output of the 4th logical circuit is connected with the 3rd input of the 3rd logical circuit; The output of the 3rd logical circuit is connected with the first input end of the clock signal input terminal of the second trigger, the 4th logical circuit, and the output of the 3rd logical circuit exports the first output signal; The output Q of the second trigger exports the second output signal; The output QB of the first trigger is connected with the second input of the 3rd logical circuit, the second input of the second logical circuit; The output of the 3rd logical circuit is connected by the input of delayer with the first pulse generator; The output of the first pulse generator is connected with the first input end of the 3rd logical circuit; Reverse current detection signal inputs the input of the 3rd pulse generator and the first input end of the second logical circuit respectively; The output of the 3rd pulse generator is connected with the 3rd input of the 4th pulse generator; The output of the second logical circuit is connected with the reset terminal of the second trigger.
Preferably, control circuit also comprises: the first driver and the second driver;
First output signal is by the closed of the first driver control first switch or disconnect; Second output signal is by the disconnection or closed of the second driver control second switch, and wherein, the first switch and second switch are alternately closed.
Preferably, when enable signal is the first level, control circuit controls the first switch and second switch is alternately closed, and battery is powered to external loading;
Preferably, when enable signal is the first level, control circuit controls the first switch and second switch is alternately closed, and battery is powered to external loading, comprising:
When the enable signal that control circuit receives is the first level, in one cycle, control circuit controls the first switch and closes, and controls second switch disconnection, and battery is by Power supply inductance; Control circuit controls the first switch and disconnects, and it is closed to control second switch, and inductance is by Power supply first electric capacity and external loading.
Preferably, control circuit also comprises: negative feedback control circuit, the 5th logical circuit and the 6th logical circuit;
The output of negative feedback control circuit is connected with the first input end of the second input of the 5th logical circuit, the 6th logical circuit; The first input end of the 5th logical circuit is connected with the output of the 3rd logical circuit; The output of the 5th logical circuit is connected with the input of the first driver; Second input of the 6th logical circuit is connected with the output Q of the second trigger; The output of the 6th logical circuit is connected with the input of the second driver.
Preferably, voltage feedback circuit comprises: the first resistance and the second resistance;
One end ground connection of the first resistance; The other end of the first resistance and one end of the second resistance, control circuit are coupled; One end of the other end of the second resistance and one end of the first switch, the first electric capacity is coupled.
Preferably, booster circuit also comprises: the second electric capacity;
Second electric capacity is coupled with cell parallel.
Preferably, the first level is high level, and second electrical level is low level.
A kind of booster circuit provided by the invention, by improving DC-to-DC converter structure, the first switch in control circuit control booster circuit and second switch is utilized to be alternately closed, by the energy regenerating in the first electric capacity and load parasitic capacitance under synchronous buck pattern, thus the energy in recovery output capacitance, for the battery of input charges, improve system effectiveness, save the energy.
Accompanying drawing explanation
The circuit diagram of a kind of booster circuit that Fig. 1 provides for the embodiment of the present invention;
The circuit diagram of a kind of voltage feedback circuit that Fig. 2 embodiment of the present invention provides;
The circuit theory diagrams of a kind of control circuit that Fig. 3 provides for the embodiment of the present invention;
The working waveform figure of each voltage node of a kind of booster circuit that Fig. 4 provides for the embodiment of the present invention.
Embodiment
For making the object of the embodiment of the present invention, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the embodiment of the present invention, technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
For ease of the understanding to the embodiment of the present invention, be further explained explanation below in conjunction with accompanying drawing with specific embodiment, embodiment does not form the restriction to the embodiment of the present invention.
The circuit diagram of a kind of booster circuit that Fig. 1 embodiment of the present invention provides, as shown in Figure 1, this booster circuit comprises: battery BAT, inductance L 1, first switch S 1, second switch S2, the first electric capacity C1, control circuit 110 and voltage feedback circuit 120;
One end of inductance L 1 and the positive pole of battery BAT are coupled; The other end of inductance L 1 is coupled with the negative pole of battery BAT by the first switch S 1; The other end of inductance L 1 is also coupled by the negative pole of second switch S2 and the first electric capacity C1 and battery BAT, wherein, and second switch S2 and the first electric capacity C1 series coupled; One end of voltage feedback circuit 120 and the other end of inductance L 1 are coupled; The other end and the control circuit 110 of voltage feedback circuit 120 are coupled; Voltage feedback circuit 120 ground connection;
Control circuit 110, according to the level of enable signal EN, controls the closed or disconnection of the first switch S 1 or second switch S2;
In a period of time when enable signal EN becomes second electrical level from the first level, control circuit 110 controls the first switch S 1 and second switch S2 is alternately closed, and the parasitic capacitance of the first electric capacity C1 and external loading is charged to battery BAT;
Particularly, in a period of time when enable signal EN becomes second electrical level from the first level, control circuit 110 controls the first switch S 1 and second switch S2 is alternately closed, and the parasitic capacitance of the first electric capacity C1 external loading is charged to battery BAT, comprising:
In a period of time when the enable signal EN that control circuit 110 receives becomes second electrical level from the first level, in one cycle, control circuit 110 controls the first switch S 1 and disconnects, and controls second switch S2 and close, and the parasitic capacitance of the first electric capacity C1 and load is by Power supply inductance L 1; Control circuit 110 controls the first switch S 1 and closes, and when second switch S2 disconnects, inductance L 1 is by Power supply battery BAT.
When enable signal EN is second electrical level, and when output voltage equals input voltage, control circuit 110 controls the first switch S 1 and second switch S2 disconnects, and booster circuit quits work.
Alternatively, when enable signal EN is the first level, control circuit 110 controls the first switch S 1 and second switch S2 is alternately closed, and battery BAT powers to external loading.
Particularly, when enable signal EN is the first level, control circuit 110 controls the first switch S 1 and second switch S2 is alternately closed, and battery BAT powers to external loading, comprising:
When the enable signal EN that control circuit 110 receives is the first level, in one cycle, control circuit 110 controls the first switch S 1 and closes, and controls second switch S2 and disconnect, and battery BAT is by Power supply inductance L 1; Control circuit 110 controls the first switch S 1 and disconnects, and it is closed to control second switch S2, and inductance L 1 is by Power supply first electric capacity C1 and external loading.
Particularly, the first level is high level, and second electrical level is low level.
Alternatively, booster circuit also comprises: the second electric capacity C2;
Second electric capacity C2 and battery BAT parallel coupled.
It should be noted that, control circuit 110 controls the closed or disconnection of the first switch S 1 and second switch S2.When enable signal EN is high level, control circuit 110 controls the first switch S 1 and second switch S2 is alternately closed, and makes booster circuit be operated in synchronous boost pattern, is raised by battery BATBAT voltage as output loading is powered; When enable signal EN just become high level become low level time, control circuit 110 controls the first switch S 1 and second switch S2 is alternately closed, booster circuit is made to be operated in synchronous buck pattern, by the energy regenerating in the first electric capacity C1 and load parasitic capacitance, for the battery BATBAT of input charges; When enable signal EN becomes low level, the energy in output capacitance be recovered to output voltage equal with input voltage time, stop energy recovery function, whole booster circuit system stalls.When enable signal EN is high level, booster circuit normally works; When enable signal EN becomes low level from high level, energy recuperation mode opened by booster circuit, reclaims, the energetic portions in output capacitance for the battery BAT of input charges; When enable signal EN is low level, booster circuit quits work.
A kind of booster circuit provided by the invention, by improving DC-to-DC converter structure, control circuit 110 is utilized to control the first switch S 1 in booster circuit and second switch S2 is alternately closed, by the energy regenerating in the first electric capacity C1 and load parasitic capacitance under synchronous buck pattern, thus the energy in recovery output capacitance, for the battery BAT of input charges, improve system effectiveness, save the energy.
The circuit diagram of a kind of voltage feedback circuit that Fig. 2 embodiment of the present invention provides, as shown in Figure 2, voltage feedback circuit 220 comprises: the first resistance R1 and the second resistance R2;
One end ground connection of the first resistance R1; The other end of the first resistance R1 and one end of the second resistance R2, control circuit 110 are coupled; One end of the other end of the second resistance R2 and one end of the first switch S 1, the first electric capacity C1 is coupled.
It should be noted that, voltage feedback circuit 220 can be any circuit realiration playing dividing potential drop effect, does not limit at this.
The circuit theory diagrams of a kind of control circuit that Fig. 3 provides for the embodiment of the present invention, in this example, with the first trigger and the second trigger be d type flip flop, the first logical circuit, the second logical circuit, the 5th logical circuit and the 6th logical circuit is or door, the 3rd logical circuit and the 4th logical circuit for NOR gate, for example is described, wherein, d type flip flop is the d type flip flop that high level resets, clock falling edge triggers, namely when reset terminal is high level, output Q is reset to low level, output QB is reset to high level, and the trailing edge of clock signal triggers.
As shown in Figure 3, control circuit comprises: energy regenerating control circuit 311, first driver DRV1, the second driver DRV2, negative feedback control circuit 312, the 5th logical circuit or3 and the 6th logical circuit or4;
Energy regenerating control circuit 311 comprises: comparator CM, the first trigger ffdf1, the second trigger ffdf1, the first pulse generator pulse1, the second pulse generator pulse2, the 3rd pulse generator pulse3, delayer delay, the first logical circuit or1, the second logical circuit or2, the 3rd logical circuit nor1 and the 4th logical circuit nor2;
The input of comparator CM receives voltage division signal FB and reference voltage REF respectively; The output of comparator CM is connected with second input of the first logical circuit or1; Enable signal EN is input to the first input end of the first logical circuit or1 and the clock signal input terminal of the first trigger ffdf1 respectively; Input voltage VIN is input to the data terminal of the first trigger ffdf1 and the data terminal of the second trigger ffdf2 respectively; The output of the first logical circuit or1 is connected with the reset terminal of the first trigger ffdf1; The output Q of the first trigger ffdf1 is connected with second input of the 4th logical circuit nor2 by the second pulse generator pulse2; The output of the 4th logical circuit nor2 is connected with the 3rd input of the 3rd logical circuit nor1; The output of the 3rd logical circuit nor1 is connected with the first input end of the clock signal input terminal of the second trigger ffdf2, the 4th logical circuit nor2, and the output of the 3rd logical circuit nor1 exports the first output signal QS1; The output Q of the second trigger ffdf2 exports the second output signal QS2; The output QB of the first trigger ffdf1 is connected with second input of second input of the 3rd logical circuit nor1, the second logical circuit or2; The output of the 3rd logical circuit nor1 is connected with the input of the first pulse generator pulse1 by delayer delay; The output of the first pulse generator pulse1 is connected with the first input end of the 3rd logical circuit nor1; Reverse current detection signal inputs the input of the 3rd pulse generator pulse3 and the first input end of the second logical circuit or2 respectively; The output of the 3rd pulse generator pulse3 is connected with the 3rd input of the 4th pulse generator; The output of the second logical circuit or2 is connected with the reset terminal of the second trigger ffdf2.
First output signal QS1 controls the closed of the first switch S 1 by the first driver DRV1 or disconnects; Second output signal QS2 controls the disconnection or closed of second switch S2 by the second driver DRV2, and wherein, the first switch S 1 and second switch S2 are alternately closed.
The output of negative feedback control circuit 312 is connected with the first input end of second input of the 5th logical circuit or3, the 6th logical circuit or4; The first input end of the 5th logical circuit or3 is connected with the output of the 3rd logic nor1 circuit; The output of the 5th logical circuit or3 is connected with the input of the first driver DRV1; Second input of the 6th logical circuit or4 is connected with the output Q of the second trigger ffdf2; The output of the 6th logical circuit or4 is connected with the input of the second driver DRV2.
It should be noted that, in embodiments of the present invention, this negative feedback control circuit 312 can adopt prior art to realize, and negative feedback control circuit can comprise: error amplifier EA, comparator PWM, logic control circuit, succinct in order to what describe, do not repeat them here its annexation
Specific works process is as follows:
When enable signal EN is high level, signal rst1 after the first logical circuit or1 is high level, first trigger ffdf1 is resetted, the output signal QONB causing the first trigger ffdf1 output QB is high level, and after the 3rd logical circuit nor1, export the first output signal QS1 is low level; The signal rst2 of output signal QONB after the second logical circuit or2 is also high level, is resetted by the second trigger ffdf1, and the second output signal QS2 exports as low level.First output signal QS1 and second output signal QS2 be connected to or door or3 and or door or4, when EN is high level, first output signal QS1 and second output signal QS2 is low level, do not affect or door or3 and or the output of door or4, namely now, or door or3 and or the output of door or4 only controlled by HDP and LDP.When showing that enable signal EN is high level, DVS1 and DVS2 that energy regenerating control circuit exports is controlled by negative feedback control circuit completely.
Negative feedback control circuit is the same with the working method of prior art.When branch pressure voltage FB is lower than reference voltage REF, the output EAO voltage of error amplifier EA will rise, the duty ratio of PWM output signal D will increase, the duty ratio of LDP increases and the duty ratio of HDP reduces, the duty ratio of DVS2 increases and the duty ratio of DVS1 reduces, output voltage VO increases, through the voltage division signal FB voltage rise of the first resistance R1 and the second resistance R2;
When branch pressure voltage FB is higher than reference voltage REF, the output EAO voltage of error amplifier EA will decline, the duty ratio of PWM output signal D will reduce, the duty ratio of LDP reduces and the duty ratio of HDP increases, the duty ratio of DVS2 reduces and the duty ratio of DVS1 increases, output voltage VO declines, through the voltage division signal FB voltage drop of the first resistance R1 and the second resistance R2.So show as negative feedback effect.When this negative feedback is stablized, the magnitude of voltage of voltage division signal FB is equal with the magnitude of voltage of reference voltage REF, thus output voltage VO value is REF. (R1+R2)/R1, wherein REF is the magnitude of voltage of reference voltage REF, R1 and R2 is the resistance value of resistance R1 and R2 respectively.
When enable signal EN becomes in low level a period of time from high level, booster circuit enters energy recovery state.When enable signal EN becomes low level from high level, trailing edge will be produced, trigger the first trigger ffdf1, the signal QON that its output Q is exported becomes high level from low level, the very short burst pulse of a high level time is produced through the second trigger pulse2, the output A1 of the 4th logical circuit nor2 is set to low level, now the output QONB of the output QB of the first trigger ffdf1 also becomes low level, the initial condition of output signal QS1 is low level, signal po1 initial condition after delayer delay and the first pulse generator pulse1 is also low level, therefore the 3rd logical circuit nor1 output first output signal QS1 first will become high level, first output signal QS1 is through delayer delay, rise along producing a burst pulse po1 thereon through the first pulse generator pulse1 again, by the 3rd logical circuit nor1, the first output signal QS1 will be reset to low level.So the first output signal QS1 keeps high level time to be determined by the time of delay of delayer delay.When the first output signal QS1 becomes low level from high level, trigger the second trigger ffdf2, exported the second output signal QS2 and be set to high level.
When reverse current detection signal RCP becomes high level from low level, represent that inductive current has dropped to zero, in order to avoid producing reverse current, reverse current detection signal RCP signal rises along producing narrow pulse signal po3 thereon by the 3rd pulse generator pulse3, after the 4th logical circuit nor2, A1 signal is reset to low level, now due to po1, QONB, A1 is low level, so the first output signal QS1 becomes high level again, such first output signal QS1 and second output signal QS2 is alternately high level work, constantly by the energy trasfer on the first capacitance C1 to input battery, battery is charged, until when output voltage VO is reduced to lower than input voltage VIN, comparator CM1 becomes high level from low level, wait rst1 signal through the first logical circuit or1 the first trigger ffdf1 is resetted, the output signal QON of its output Q becomes low level, output signal QONB becomes high level, output signal QON exports the first output signal QS1 and becomes low level after the 3rd logical circuit nor1, output signal QONB rst2 signal after the second logical circuit or2 becomes high level, second trigger ffdf2 is resetted, it exports the second output signal QS2 and becomes low level.
Enable signal EN is after low level, output HDP and LDP of control logic control circuit becomes low level, after energy regenerating operation after a while, when output voltage VO is down to input voltage VIN, first output signal QS1 and second output signal QS2 also becomes low level, through or door or3 and or4 after, HDA and LDA is low level, after driver DRV1 and DRV2, DVS1 and DVS2 is low level, and the first switch S 1 and second switch S2 turn off, and booster circuit quits work completely.
In the booster circuit course of work, the work wave of each voltage node as shown in Figure 4.
A kind of booster circuit provided by the invention, by improving DC-to-DC converter structure, control circuit 110 is utilized to control the first switch S 1 in booster circuit and second switch S2 is alternately closed, by the energy regenerating in the first electric capacity C1 and load parasitic capacitance under synchronous buck pattern, thus the energy in recovery output capacitance, for the battery BAT of input charges, improve system effectiveness, save the energy.
Professional should recognize further, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with electronic hardware, computer software or the combination of the two, in order to the interchangeability of hardware and software is clearly described, generally describe composition and the step of each example in the above description according to function.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present invention.
The software module that the method described in conjunction with embodiment disclosed herein or the step of algorithm can use hardware, processor to perform, or the combination of the two is implemented.Software module can be placed in the storage medium of other form any known in random asccess memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.
Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection range be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a booster circuit, is characterized in that, described booster circuit comprises: battery, inductance, the first switch, second switch, the first electric capacity, control circuit and voltage feedback circuit;
One end of described inductance and the positive pole of described battery are coupled; The other end of described inductance is coupled by the negative pole of described first switch and described battery; The other end of described inductance is also coupled by the negative pole of described second switch and described first electric capacity and described battery, and wherein, described second switch is coupled with described first capacitances in series; One end of described voltage feedback circuit and the other end of described inductance are coupled; The other end and the described control circuit of described voltage feedback circuit are coupled; Described voltage feedback circuit ground connection;
Described control circuit, according to the level of enable signal, controls the closed or disconnection of described first switch or described second switch;
In a period of time when described enable signal becomes second electrical level from the first level, described control circuit controls described first switch and described second switch is alternately closed, and the parasitic capacitance of described first electric capacity and external loading is charged to described battery;
When described enable signal is second electrical level, and when output voltage equals input voltage, described control circuit controls described first switch and described second switch disconnects, and described booster circuit quits work.
2. booster circuit according to claim 1, it is characterized in that, in described a period of time when described enable signal becomes second electrical level from the first level, described control circuit controls described first switch and described second switch is alternately closed, described first electric capacity charges to described battery, comprising:
In a period of time when the enable signal that described control circuit receives becomes second electrical level from the first level, in one cycle, described control circuit controls described first switch and disconnects, and control described second switch to close, the parasitic capacitance of described first electric capacity and described external loading is by inductance described in Power supply; Described control circuit controls described first switch and closes, and when described second switch disconnects, described inductance is by battery described in Power supply.
3. booster circuit according to claim 1 and 2, is characterized in that, described control circuit comprises: energy regenerating control circuit; Wherein,
Described energy regenerating control circuit comprises: comparator, the first trigger, the second trigger, the first pulse generator, the second pulse generator, the 3rd pulse generator, delayer, the first logical circuit, the second logical circuit, the 3rd logical circuit and the 4th logical circuit;
The input of described comparator receives voltage division signal and reference voltage; The output of described comparator is connected with the second input of described first logical circuit; Enable signal is input to the first input end of described first logical circuit and the clock signal input terminal of described first trigger respectively; Input voltage is input to the data terminal of described first trigger and the data terminal of described second trigger respectively; The output of described first logical circuit is connected with the reset terminal of described first trigger; The output Q of described first trigger is connected by second input of described second pulse generator with described 4th logical circuit; The output of described 4th logical circuit is connected with the 3rd input of described 3rd logical circuit; The output of described 3rd logical circuit is connected with the first input end of the clock signal input terminal of described second trigger, described 4th logical circuit, and the output of described 3rd logical circuit exports the first output signal; The output Q of described second trigger exports the second output signal; The output QB of described first trigger is connected with the second input of described 3rd logical circuit, the second input of described second logical circuit; The output of described 3rd logical circuit is connected by the input of described delayer with described first pulse generator; The output of described first pulse generator is connected with the first input end of described 3rd logical circuit; Reverse current detection signal inputs the input of described 3rd pulse generator and the first input end of described second logical circuit respectively; The output of described 3rd pulse generator is connected with the 3rd input of described 4th pulse generator; The output of described second logical circuit is connected with the reset terminal of described second trigger.
4. booster circuit according to claim 3, is characterized in that, described control circuit also comprises: the first driver and the second driver;
Described first output signal is by the closed of the first switch described in described first driver control or disconnect; Described second output signal is by the disconnection or closed of second switch described in described second driver control, and wherein, described first switch and described second switch are alternately closed.
5. booster circuit according to claim 1, is characterized in that, when described enable signal is the first level, described control circuit controls described first switch and described second switch is alternately closed, and described battery is powered to external loading.
6. booster circuit according to claim 5, is characterized in that, described when described enable signal is the first level, and described control circuit controls described first switch and described second switch is alternately closed, and described battery is powered to external loading, comprising:
When the enable signal that described control circuit receives is the first level, in one cycle, described control circuit controls described first switch and closes, and controls the disconnection of described second switch, and described battery is by inductance described in Power supply; Described control circuit controls described first switch and disconnects, and it is closed to control described second switch, and described inductance is by the first electric capacity described in Power supply and described external loading.
7. the booster circuit according to claim 5 or 6, is characterized in that, described control circuit also comprises: negative feedback control circuit, the 5th logical circuit and the 6th logical circuit;
The output of described negative feedback control circuit is connected with the first input end of the second input of described 5th logical circuit, described 6th logical circuit; The first input end of described 5th logical circuit is connected with the output of described 3rd logical circuit; The output of described 5th logical circuit is connected with the input of the first driver; Second input of described 6th logical circuit is connected with the output Q of described second trigger; The output of described 6th logical circuit is connected with the input of the second driver.
8. booster circuit according to claim 1, is characterized in that, described voltage feedback circuit comprises: the first resistance and the second resistance;
One end ground connection of described first resistance; The other end and one end of described second resistance, the described control circuit of described first resistance are coupled; One end of the other end of described second resistance and one end of described first switch, described first electric capacity is coupled.
9. booster circuit according to claim 1, is characterized in that, described booster circuit also comprises: the second electric capacity;
Described second electric capacity is coupled with described cell parallel.
10. booster circuit according to claim 1, is characterized in that, described first level is high level, and described second electrical level is low level.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510435338.4A CN105099174B (en) | 2015-07-22 | 2015-07-22 | Booster circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510435338.4A CN105099174B (en) | 2015-07-22 | 2015-07-22 | Booster circuit |
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| CN105099174A true CN105099174A (en) | 2015-11-25 |
| CN105099174B CN105099174B (en) | 2017-11-10 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113726133A (en) * | 2021-08-23 | 2021-11-30 | 宁波大学 | Zero current switch control circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20130307491A1 (en) * | 2010-07-20 | 2013-11-21 | Tesla Motors, Inc. | Bidirectional polyphase multimode converter including boost and buck-boost modes |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113726133A (en) * | 2021-08-23 | 2021-11-30 | 宁波大学 | Zero current switch control circuit |
| CN113726133B (en) * | 2021-08-23 | 2023-03-28 | 宁波大学 | Zero current switch control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105099174B (en) | 2017-11-10 |
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