CN105097899A - Semiconductor structure and formation method thereof - Google Patents
Semiconductor structure and formation method thereof Download PDFInfo
- Publication number
- CN105097899A CN105097899A CN201410198292.4A CN201410198292A CN105097899A CN 105097899 A CN105097899 A CN 105097899A CN 201410198292 A CN201410198292 A CN 201410198292A CN 105097899 A CN105097899 A CN 105097899A
- Authority
- CN
- China
- Prior art keywords
- layer
- nipt film
- semiconductor structure
- content
- nipt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention discloses a semiconductor structure and a formation method thereof. The semiconductor structure includes a silicon substrate, a first-layer NiPt film and a second-layer NiPt film, which are laminated in sequence. The first-layer NiPt film covers the silicon substrate. The second-layer NiPt film covers the first-layer NiPt film. The content of Pt in the first-layer NiPt film is higher than the content of Pt in the second-layer NiPt film. The content of Pt in the first-layer NiPt film that contacts the silicon substrate is relatively high, so favorable conditions are made for formation of a NiSi. The content of Pt in the second-layer NiPt film is low, and the Pt can be easily removed during chemical etching. Therefore, many defects that are likely to be produced in the prior art are reduced and even avoided, and then the product quality is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of semiconductor structure and forming method thereof.
Background technology
At present, nickle silicide is widely used in advanced semiconductor fabrication process.Nickle silicide Main Function reduces the contact resistance between metal and semiconductor.Nickle silicide has three form: NiSi usually
2, NiSi, Ni
2si.Because simple NiSi thermal stability is poor, usually can mix platinum (Pt) wherein, for improving the stability of NiSi.Pt content must and whole silicide process perfect matching.
General, profit forms NiSi with the following method, and as shown in Figure 1, the nickel dam 2 of deposition containing Pt on silicon layer 1, and protective mulch 3, then Ni and Si reaction forms NiSi.
But, find in actual production, formed in the process of NiSi and very easily occur NiSi defect of pipeline (pipingdefect) and Pt residual defects (residuedefect), affect film quality.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor structure and forming method thereof, improve the problem easily producing NiSi defect of pipeline and Pt residual defects in existing technique.
For solving the problems of the technologies described above, the invention provides a kind of semiconductor structure, comprising:
Silicon base;
Cover the ground floor NiPt film of described silicon base, and cover the second layer NiPt film of described ground floor NiPt film, in described ground floor NiPt film, the content of Pt is higher than the content of Pt in second layer NiPt film.
Further, for described semiconductor structure, in described ground floor NiPt film, the content of Pt is 5mol% ~ 30mol%.
Further, for described semiconductor structure, described semiconductor structure also comprises a protective layer, and described protective layer covers described second layer NiPt film.
Further, for described semiconductor structure, the material of described protective layer is TiN.
Further; for described semiconductor structure; described semiconductor structure also comprises third layer NiPt film, and described third layer NiPt film is between described second layer NiPt film and protective layer, and in described third layer NiPt film, the content of Pt is lower than the content of Pt in second layer NiPt film.
Further, for described semiconductor structure, the thickness of described ground floor NiPt film is
the thickness of described second layer NiPt film is
The invention provides a kind of formation method of semiconductor structure, comprising:
One silicon base is provided;
At described deposited on silicon substrates ground floor NiPt film;
Described ground floor NiPt film deposits second layer NiPt film;
Wherein, in described ground floor NiPt film the content of Pt higher than the content of Pt in second layer NiPt film.
Further, for described semiconductor structure, in described ground floor NiPt film, the content of Pt is 5mol% ~ 30mol%.
Further, for the formation method of described semiconductor structure, before described deposited on silicon substrates ground floor NiPt film, also comprise and pre-cleaning processes is carried out to described silicon base.
Further, for the formation method of described semiconductor structure, adopt CVD technique to form described ground floor NiPt film and second layer NiPt film, the thickness of described ground floor NiPt film is
the thickness of described second layer NiPt film is
Further, for the formation method of described semiconductor structure, after formation second layer NiPt film, comprising: form a protective layer and be covered on described second layer NiPt film, the material of described protective layer is TiN.
Further; for the formation method of described semiconductor structure, after formation second layer NiPt film, before formation one protective layer; also comprise: form third layer NiPt film, in described third layer NiPt film, the content of Pt is lower than the content of Pt in second layer NiPt film.
Compared with prior art, in semiconductor structure provided by the invention and forming method thereof, at least comprise ground floor NiPt film and second layer NiPt film, and in described ground floor NiPt film the content of Pt higher than the content of Pt in second layer NiPt film.Compared to existing technology, utilize the content of Pt in the ground floor NiPt film contacted with silicon base higher, thus favourable to the formation of NiSi; And the content of Pt is lower in second layer NiPt film, be easier to remove at chemical etching ratio, thus effective minimizing even avoids the number of drawbacks as easily formed in the prior art, this provides for improved the quality of product.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the semiconductor structure manufactured in a kind of prior art;
Fig. 2 is the schematic diagram of semiconductor structure in the embodiment of the present invention;
Fig. 3 is the flow chart of the formation method of semiconductor structure in the embodiment of the present invention.
Embodiment
Below in conjunction with schematic diagram, semiconductor structure of the present invention and forming method thereof is described in more detail, which show the preferred embodiments of the present invention, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
In order to clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, a large amount of implementation detail must be made to realize the specific objective of developer, such as, according to regarding system or the restriction about business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, more specifically the present invention is described by way of example with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
Mention in the introduction, in actual production, usually can run into two kinds of problems:
1, NiSi defect of pipeline (pipingdefect).To study for a long period of time discovery through inventor, this is because NiSi over-conversion of being heated becomes NiSi
2, thus form pipingdefect.And NiSi
2resistance is high, and consumption silicon amount is large, and pipingdefect can increase the electric leakage of device., once attempted by optimizing rapid thermal treatment (RTP) and silicon wafer surface cleaning technique, and the content of increase Pt in NiPt alloy solves this problem for this reason.But in these two kinds of modes, the former process window is narrow, and the latter can significantly improve production cost.
2, Pt residual defects (residuedefect).For this point, inventor thinks, usually in standard RTP technique, utilizes selective chemical to etch, and reacts remaining NiPt alloy with removing in RTP.But due to the chemical inertness of Pt, be difficult in technical process remove.In addition, for solve pipingdefect and increase the content of Pt time, too increase the technology difficulty of wet etching simultaneously, finally define Pt remain.Current settling mode is mainly by increasing the process time of wet etching, but this certainly will cause the production capacity of wet process to reduce.
For this reason, the invention provides a kind of semiconductor structure and forming method thereof, comprising: the ground floor NiPt film covering silicon base, and covering the second layer NiPt film of described ground floor NiPt film, in described ground floor NiPt film, the content of Pt is higher than the content of Pt in second layer NiPt film.Utilize the content of Pt in the ground floor NiPt film contacted with silicon base higher, thus favourable to the formation of NiSi; And the content of Pt is lower in second layer NiPt film, be easier to remove at chemical etching ratio, thus effective minimizing even avoids the number of drawbacks as easily formed in the prior art, this provides for improved the quality of product.
Based on above-mentioned thought, provide the preferred embodiment of semiconductor structure and forming method thereof below, please refer to Fig. 2 and Fig. 3, Fig. 2 is the schematic diagram of semiconductor structure in the embodiment of the present invention, and Fig. 3 is the flow chart of the formation method of semiconductor structure in the embodiment of the present invention.
First, carry out step S101, a silicon base 1 is provided.Known device architecture can be formed with in described silicon base.Before formation ground floor NiPt film 21, usually need to carry out prerinse to this silicon base 1, to remove the particle on described silicon base 1 surface, metal ion or other impurity.
Then, carry out step S102, described silicon base 1 deposits ground floor NiPt film 21; Preferably, adopt CVD method, such as PECVD deposition is formed, and the thickness of described ground floor NiPt film 21 is preferably
preferably, in described ground floor NiPt film 21, the content of Pt can be such as 5mol% ~ 30mol%.
Then, carry out step S103, described ground floor NiPt film 21 continues deposition second layer NiPt film 22, same, CVD method can be adopted to deposit and formed, such as PECVD deposition is formed, and the thickness of described second layer NiPt film 22 is preferably
Due to the present invention's object be in order to avoid Pt content higher time the Pt residue problem that causes, therefore, in second layer NiPt film 22, the content of Pt is lower than the content of Pt in ground floor NiPt film 21, thus in the subsequent etching processes carried out, can be easier to remove, even avoid Pt remain to reduce as much as possible, improve the quality of product greatly.
In a further preferred embodiment, after carrying out completing steps S103, can also continue to deposit third layer NiPt film on described second layer NiPt film 22, should be understood that, here in described third layer NiPt film the content of Pt lower than the content of Pt in described second layer NiPt film 22.That is, in the present invention, the NiPt structure being positioned at deposition on silicon base 1 includes the multilayer of order formation, the upper correspondence of each layer self-forming order has the content of Pt less and less, thus the content of the Pt good with silicon contact position can either be ensured, NiSi needed for formation, can avoid again Pt in upper strata more, avoiding problems problem as mentioned in the background.Certainly, the number of plies of NiPt film is not The more the better, is good usually, or selects the suitable number of plies according to special process demand with layer 2-3.
Afterwards, after the NiPt film forming the required number of plies, continue on (such as the second layer) NiPt film of top layer, form a protective layer and be covered on described second layer NiPt film, the material of described protective layer is TiN.
Experiment proves, adopts method of the present invention, after defects detection, can not produce Pt residual defects, and also can not find luminance voltage contrast (BVC) defect.Further, tested by WAT, find to use the contact resistance of multilayer NiPt film when NiSi thickness is consistent in the present invention, structure compared to existing technology have dropped 10%, improves the performance of product significantly.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (12)
1. a semiconductor structure, comprising:
Silicon base;
Cover the ground floor NiPt film of described silicon base; And
Cover the second layer NiPt film of described ground floor NiPt film;
Wherein, in described ground floor NiPt film the content of Pt higher than the content of Pt in second layer NiPt film.
2. semiconductor structure as claimed in claim 1, it is characterized in that, in described ground floor NiPt film, the content of Pt is 5mol% ~ 30mol%.
3. semiconductor structure as claimed in claim 1, it is characterized in that, described semiconductor structure also comprises a protective layer, and described protective layer covers described second layer NiPt film.
4. semiconductor structure as claimed in claim 3, it is characterized in that, the material of described protective layer is TiN.
5. semiconductor structure as claimed in claim 4; it is characterized in that; described semiconductor structure also comprises third layer NiPt film; described third layer NiPt film is between described second layer NiPt film and protective layer, and in described third layer NiPt film, the content of Pt is lower than the content of Pt in described second layer NiPt film.
6. semiconductor structure as claimed in claim 1, it is characterized in that, the thickness of described ground floor NiPt film is
the thickness of described second layer NiPt film is
7. a formation method for semiconductor structure, comprising:
One silicon base is provided;
At described deposited on silicon substrates ground floor NiPt film;
Described ground floor NiPt film deposits second layer NiPt film;
Wherein, in described ground floor NiPt film the content of Pt higher than the content of Pt in second layer NiPt film.
8. the formation method of semiconductor structure as claimed in claim 7, it is characterized in that, in described ground floor NiPt film, the content of Pt is 5mol% ~ 30mol%.
9. the formation method of semiconductor structure as claimed in claim 7, is characterized in that, before described deposited on silicon substrates ground floor NiPt film, also comprise and carry out pre-cleaning processes to described silicon base.
10. the formation method of semiconductor structure as claimed in claim 7, is characterized in that, adopt CVD technique to form described ground floor NiPt film and second layer NiPt film, the thickness of described ground floor NiPt film is
the thickness of described second layer NiPt film is
The formation method of 11. semiconductor structures as claimed in claim 7, is characterized in that, after formation second layer NiPt film, also comprises: form a protective layer and be covered on described second layer NiPt film, the material of described protective layer is TiN.
The formation method of 12. semiconductor structures as claimed in claim 11; it is characterized in that; after formation second layer NiPt film; before formation one protective layer; also comprise: form third layer NiPt film, in described third layer NiPt film, the content of Pt is lower than the content of Pt in second layer NiPt film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410198292.4A CN105097899A (en) | 2014-05-12 | 2014-05-12 | Semiconductor structure and formation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410198292.4A CN105097899A (en) | 2014-05-12 | 2014-05-12 | Semiconductor structure and formation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105097899A true CN105097899A (en) | 2015-11-25 |
Family
ID=54577945
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410198292.4A Pending CN105097899A (en) | 2014-05-12 | 2014-05-12 | Semiconductor structure and formation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105097899A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090127594A1 (en) * | 2007-11-19 | 2009-05-21 | Advanced Micro Devices, Inc. | MOS TRANSISTORS HAVING NiPtSi CONTACT LAYERS AND METHODS FOR FABRICATING THE SAME |
| US20100193876A1 (en) * | 2009-02-05 | 2010-08-05 | Advanced Micro Devices, Inc. | METHOD TO REDUCE MOL DAMAGE ON NiSi |
| CN102723268A (en) * | 2012-06-20 | 2012-10-10 | 上海华力微电子有限公司 | Method for preparing self-aligned nickel-silicide |
-
2014
- 2014-05-12 CN CN201410198292.4A patent/CN105097899A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090127594A1 (en) * | 2007-11-19 | 2009-05-21 | Advanced Micro Devices, Inc. | MOS TRANSISTORS HAVING NiPtSi CONTACT LAYERS AND METHODS FOR FABRICATING THE SAME |
| US20100193876A1 (en) * | 2009-02-05 | 2010-08-05 | Advanced Micro Devices, Inc. | METHOD TO REDUCE MOL DAMAGE ON NiSi |
| CN102723268A (en) * | 2012-06-20 | 2012-10-10 | 上海华力微电子有限公司 | Method for preparing self-aligned nickel-silicide |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106067442B (en) | Cobalt etches deeply | |
| US10354935B2 (en) | Graphene structure and method for manufacturing the same | |
| US9373544B2 (en) | Semiconductor arrangement and formation thereof | |
| CN103972160B (en) | Method for lowering influence on copper interconnection reliability from online WAT testing | |
| CN103311178B (en) | Methods of forming copper-based conductive structures on an integrated circuit device | |
| CN104009130A (en) | Growth substrate, nitride semiconductor device and method of manufacturing the same | |
| TWI605145B (en) | Method for depositing metal layers on germanium-containing films using metal chloride precursors | |
| CN103985668B (en) | The preparation method of copper-connection | |
| TW201610231A (en) | Method for electrochemically depositing metal on a reactive metal film (1) | |
| CN209045566U (en) | Conductive plunger structure and semiconductor devices | |
| CN111106060A (en) | Semiconductor device and method of forming the same | |
| Spies et al. | Correlated and in-situ electrical transmission electron microscopy studies and related membrane-chip fabrication | |
| US20130240484A1 (en) | Electroless copper alloy capping | |
| CN106206294A (en) | Semiconductor device crystallization-amorphous transition material and forming method | |
| TW201602424A (en) | Method for electrochemically depositing metal on a reactive metal film(2) | |
| CN105097899A (en) | Semiconductor structure and formation method thereof | |
| CN105448809B (en) | The forming method of copper interconnection structure | |
| US9719189B2 (en) | Process of surface treatment for wafer | |
| CN105097901B (en) | Composite gate dielectric layer applied to iii-v substrate and preparation method thereof | |
| CN110473775A (en) | Improve the method for film removing | |
| CN110854101B (en) | Semiconductor device and formation thereof | |
| CN105047551A (en) | Preparation method of nickel silicon alloy | |
| CN103515318B (en) | CMOS full-silicide metal gate preparation method | |
| CN105244317B (en) | Formation process after a kind of nickle silicide | |
| CN102623329B (en) | Method for forming front metal dielectric layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20151125 |