CN105097815A - Capacitor structure and manufacturing method thereof, and semiconductor memory including capacitor structure - Google Patents
Capacitor structure and manufacturing method thereof, and semiconductor memory including capacitor structure Download PDFInfo
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- CN105097815A CN105097815A CN201410222759.4A CN201410222759A CN105097815A CN 105097815 A CN105097815 A CN 105097815A CN 201410222759 A CN201410222759 A CN 201410222759A CN 105097815 A CN105097815 A CN 105097815A
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Abstract
The present invention provides a capacitor structure and a manufacturing method thereof, and a semiconductor memory including the capacitor structure. The manufacturing method of the capacitor structure at least comprises the steps of: providing a semiconductor substrate comprising a peripheral area and a center area; forming a gate structure of a peripheral device at the peripheral area, and forming a first capacitor structure on the semiconductor substrate at the same time; forming a gate structure of a semiconductor memory at the center area, and forming a second capacitor structure on the first capacitor structure at the same time, wherein the second capacitor structure partly exposes the surface of the first capacitor structure; and forming a first electrode, a second electrode and a third electrode, wherein the first electrode is connected with the semiconductor substrate, the second electrode is connected with the surface of the first capacitor structure, the third electrode is connected with the surface of the second capacitor structure, the first electrode and the third electrode are conducted with each other to serve as first output ends, and the second electrode serves as a second output end. The capacitor structure of the present invention not only has large capacitance, but also has a good voltage resistant capability.
Description
Technical field
The present invention relates to a kind of technical field of semiconductors, particularly relate to a kind of capacitance structure and preparation method thereof, comprise the semiconductor memory of capacitance structure.
Background technology
In integrated circuits, capacity cell usually in the such as integrated circuit such as RFCO2 laser, monolithic microwave IC as electronic passive device.And in integrated circuit design, capacitive means can occupy sizable area usually, in order to reduce the size of whole integrated circuit, needing accordingly to be optimized the area shared by capacitance structure, making can there be comparatively high capacitance compared with the capacitance structure of small size.
General, the structure with the semiconductor memery circuit of capacitance structure as shown in Figure 1, comprising: form capacitance structure 11,12 on a semiconductor substrate 100, peripheral components 13,14 and semiconductor memory 30.Wherein, peripheral components comprises low pressure peripheral components 13 and high voltage peripheral device 14, and described capacitance structure comprises the high-voltage capacitor structure 12 formed when utilizing the low-voltage capacitance structure 11 formed when forming low pressure peripheral components 21 to form high voltage peripheral device 22 with utilization.
As shown in FIG., the gate oxide in the grid structure of low pressure peripheral components 21 is thinner, so the dielectric layer of low-voltage capacitance structure 11 is also thinner, thinner dielectric layer can make the capacitance of low-voltage capacitance structure 11 larger, but voltage endurance capability is less.And gate oxide in the grid structure of high voltage peripheral device 14 is thicker, so the dielectric layer of high-voltage capacitor structure 12 is also thicker, thicker dielectric layer can make the capacitance of high-voltage capacitor structure 12 smaller, and voltage endurance capability is larger.
In some memories, need the capacitance of capacitance structure comparatively large, also need the withstand voltage larger of capacitance structure.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of manufacture method of capacitance structure, can not meet withstand voltage and that capacitance is larger problem for solving the capacitance structure formed in semiconductor memory in prior art simultaneously.
For achieving the above object and other relevant objects, the invention provides a kind of manufacture method of capacitance structure, the manufacture method of described capacitance structure at least comprises:
There is provided Semiconductor substrate, described Semiconductor substrate comprises outer peripheral areas and central area;
Form the grid structure of peripheral components in described outer peripheral areas, form the first capacitance structure on the semiconductor substrate simultaneously;
Form the grid structure of semiconductor memory in described central area, form the second capacitance structure simultaneously on described first capacitance structure, described second capacitive structure parts exposes the surface of described first capacitance structure;
Form the first electrode, the second electrode and third electrode, wherein, described first electrode is connected with described Semiconductor substrate, and described second electrode is connected with the surface of described first capacitance structure, and described third electrode is connected with the surface of the second capacitance structure; And described first electrode and the mutual conducting of described third electrode, as the first output of described capacitance structure, described second electrode is as the second output of described capacitance structure.
Preferably, form the grid structure of peripheral components in described outer peripheral areas, the step simultaneously forming the first capacitance structure on the semiconductor substrate comprises:
The Semiconductor substrate of described outer peripheral areas forms oxide layer;
Described oxide layer is formed the first polysilicon layer;
Photoetching and etching technics is utilized to etch described first polysilicon layer and described oxide layer, to form grid structure and first capacitance structure of peripheral components respectively on a semiconductor substrate.
Preferably, form the grid structure of semiconductor memory in described central area, the step simultaneously forming the second capacitance structure on described first capacitance structure comprises:
The surface of the Semiconductor substrate in described central area and the first capacitance structure forms ONO layer;
Described ONO layer forms the second polysilicon layer;
Utilize photoetching and etching technics described second polysilicon layer of etching and ONO layer to form grid structure and second capacitance structure of memory.
Preferably, described first capacitance structure is positioned at described outer peripheral areas.
Preferably, the thickness of described oxide layer is
the thickness of described ONO layer is
Preferably, described semiconductor memory is ETOXNORflash.
Separately present invention also offers a kind of capacitance structure, described capacitance structure at least comprises: the first capacitance structure that Semiconductor substrate is formed, the second capacitance structure that described first capacitance structure is formed, first electrode, the second electrode and third electrode, wherein, described first electrode is connected with described Semiconductor substrate, and described second electrode is connected with the surface of described first capacitance structure, and described third electrode is connected with the surface of the second capacitance structure; And described first electrode and the mutual conducting of described third electrode, as the first output of described capacitance structure, described second electrode is as the second output of described capacitance structure.
Preferably, described first capacitance structure comprises the oxide layer being positioned at described semiconductor substrate surface and the first polysilicon layer being positioned at described oxide layer surface; Described second capacitance structure comprises the ONO layer being positioned at described first polysilicon layer surface and the second polysilicon layer being positioned at described ONO layer surface.
Accordingly, present invention also offers a kind of semiconductor memory, described semiconductor memory at least comprises: capacitance structure as above.
Preferably, described semiconductor memory also comprises ETOXNORflash.
As mentioned above, capacitance structure that technical scheme of the present invention provides and preparation method thereof, and comprise the semiconductor memory of this capacitance structure, there is following beneficial effect:
The equivalent capacity of described capacitance structure is the electric capacity of the equivalent capacity of the first capacitance structure and equivalent capacity CONO parallel connection between the first output and the second output of the second capacitance structure.Like this, described capacitance structure, and namely the semiconductor memory comprising described capacitance structure can have larger capacitance, also can have thicker dielectric layer and bear larger voltage, have larger voltage endurance capability.Simultaneously described capacitance structure and the semiconductor memory that comprises described capacitance structure do not take more chip area, and the manufacture method of described capacitance structure meets again the technique of dielectric layer that forms capacitance structure and the technique of existing formation semiconductor memory merges.
Accompanying drawing explanation
Fig. 1 is shown as in conventional art the schematic diagram of the structure of the semiconductor memery circuit with capacitance structure.
Fig. 2 is shown as the flow chart of the manufacture method of the capacitance structure that technical scheme of the present invention provides.
Fig. 3 to Fig. 5 is shown as the schematic diagram of the manufacture method of the capacitance structure that technical scheme of the present invention provides.
Fig. 6 is shown as the equivalent circuit diagram of the capacitance structure that technical scheme of the present invention provides.
Element numbers explanation
100 Semiconductor substrate
11 low-voltage capacitance structures
12 high-voltage capacitor structures
13 low pressure peripheral components
22 high voltage peripheral devices
30 semiconductor memories
70 outer peripheral areas
40 storage areas
110 oxide layers
112 first polysilicon layers
22 grid structures
21 first capacitance structures
42 grid structures
41 second capacitance structures
211 bottom oxide layers
212 nitration cases
213 top layer oxide layers
510 first electrodes
520 second electrodes
530 third electrodes
A1 first output
A2 second output
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to Fig. 2 to Fig. 6.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
Shown in composition graphs 2, technical scheme of the present invention provides a kind of manufacture method of capacitance structure, specifically comprises:
First, step S10 is performed: provide Semiconductor substrate;
Shown in figure 3, provide Semiconductor substrate 100, preferably, described Semiconductor substrate comprises outer peripheral areas 70 and storage area 40.Described outer peripheral areas 70 is suitable for forming peripheral components thereon in subsequent technique, and described storage area 40 is suitable for forming semiconductor memory thereon in subsequent technique.
In the present embodiment, described semiconductor memory is the NORFlash of stacked structure or the NORFlash of splitting bar structure.Those skilled in the art are appreciated that, the NORFlash of described stacked structure and the NORFlash of splitting bar structure includes the floating gate structure that ONO layer is formed.The concrete structure of described semiconductor memory is structure well known to those skilled in the art, does not elaborate at this.Preferably, in the present embodiment, described semiconductor memory is ETOXNORflash.
Next, step S20 is performed: shown in figure 3, form grid structure 22 and first capacitance structure 21 of peripheral components on the semiconductor substrate;
Specifically comprise: in described Semiconductor substrate 100, form oxide layer 110, described oxide layer 110 is formed the first polysilicon layer 112, then photoetching and etching technics is utilized to carry out selective etch to described first polysilicon layer 112 and described oxide layer 110, to form grid structure 22 and first capacitance structure 21 of peripheral components on a semiconductor substrate.Wherein, the dielectric layer of described first capacitance structure 21 is oxide layer 110, and the top crown of described first capacitance structure 21 is described first polysilicon layer 112.
The technique of described formation oxide layer 110 is thermal oxidation or APCVD (aumospheric pressure cvd), and the thickness forming oxide layer 110 is
preferably, in argon gas or nitrogen, by SIH
4being diluted to percent by volume is 2% ~ 10%, passes into oxygen simultaneously, and arranging reaction temperature is 450 DEG C ~ 500 DEG C, and 30min is carried out in reaction.
The technique of described formation first polysilicon layer 112 is LPCVD, and being specially in 575 DEG C ~ 650 DEG C, is the SIH of 20% ~ 30% by thermal decomposition pure silane or silane volume ratio
4form polysilicon with the mist of nitrogen, 40min is carried out in reaction.Wherein, in reaction mixture gas body, AsH is added
3, PH
3, B
2h
6etc. carrying out in-situ doped to described first polysilicon layer, change the characteristics such as the first polysilicon resistance rate.
The technique of described formation grid structure 22 and the first capacitance structure 21 is specifically as follows: on described first polysilicon layer 112, form photoresist layer (not shown), then exposure and developing process is utilized, the figure of described grid structure 22 and the first capacitance structure 21 is formed in described photoresist layer, again there is the photoresist layer of the figure of grid structure 22 and the first capacitance structure 21 for mask, plasma etch process is utilized to carry out selective etch to described first polysilicon layer 112 and oxide layer 110 successively, thus form described grid structure 22 and the first capacitance structure 21.
In the present embodiment, described grid structure 22 and the first capacitance structure 21 are formed simultaneously, namely form described first capacitance structure 21 and do not increase new technique, when just needing to carry out photoetching, in lithography mask version, be designed into the figure of grid structure 22 and the first capacitance structure 21 simultaneously.
In addition, after step S20 has been formed, before carrying out step S30, the both sides that can also be included in described grid structure 22 form the step of side wall.
Concrete, the technique that the described both sides at described grid structure 22 form side wall is: utilize LPCVD (low-pressure chemical vapor deposition) to form silicon dioxide layer on the surface of described Semiconductor substrate 100, grid structure 22 and the first capacitance structure 21, then utilize anisotropic plasma dry etching to be removed by the silicon dioxide layer of described Semiconductor substrate 100 and the first capacitance structure 21 upper surface, retain the silicon dioxide layer of described grid structure 22 both sides.Thus formation side wall.
Next, perform step S30: in described Semiconductor substrate 100, form semiconductor memory grid structure 42 and the second capacitance structure 41, described second capacitance structure 41 is positioned on described first capacitance structure 21, and part exposes the surface of described first capacitance structure 21;
In conjunction with reference to shown in figure 4, the Semiconductor substrate 100 of described central area utilizes chemical vapor deposition method form the grid structure 42 of semiconductor memory, comprise ONO layer (oxide layer-nitride layer-oxide layer) 210 and the second polysilicon layer 230.Wherein, described ONO layer is made up of bottom oxide layer 211, nitration case 212 and top layer oxide layer 213.Preferably, adopt thinner bottom oxide layer 211 and thicker top layer oxide layer 213, higher critical electric field strength can be ensured, thinner equivalent oxide thickness can be obtained again, improve coupling efficiency, reduce program voltage.
In addition, after step S30 has been formed, before carrying out step S40, the both sides that can also be included in the grid structure 42 of described semiconductor memory form the step of side wall.
Concrete, the technique that the described both sides at described grid structure 42 form side wall is: utilize LPCVD (low-pressure chemical vapor deposition) to form silicon dioxide layer on the surface of described Semiconductor substrate 100, grid structure 22, first capacitance structure 21 and the second capacitance structure 41, then utilize anisotropic plasma dry etching to be removed by the silicon dioxide layer of described Semiconductor substrate 100, first capacitance structure 21 and the second capacitance structure 41 upper surface, retain the silicon dioxide layer of described grid structure 22 both sides.Thus formation side wall.
Next, perform step S40: shown in figure 5, form the first electrode 510, second electrode 520 and third electrode 530, described first electrode 510 is connected with described Semiconductor substrate 100, described second electrode 520 is connected with the surface of described first capacitance structure 21, described third electrode 530 is connected with the surface of the second capacitance structure 41, described first electrode 510 and described third electrode 530 conducting mutually, as the first output terminals A 1 of described capacitance structure, described second electrode is as the second output terminals A 2 of described capacitance structure.
The technique of described formation first electrode 510, second electrode 520 and third electrode 530 is: utilize LPCVD (low-pressure chemical vapor deposition) to be formed on the surface of described Semiconductor substrate 100, grid structure 22, first capacitance structure 21 and the second capacitance structure 41
silicon dioxide layer as an ILD (interlayer dielectric layer), then on described ILD, photoresist layer (not shown) is formed, then exposure and developing process is utilized, the first electrode 510 is formed in described photoresist layer, the figure of the second electrode 520 and third electrode 530, again there is the photoresist layer of the figure of grid structure 22 and the first capacitance structure 21 for mask, plasma etch process is utilized to carry out selective etch to described first interlayer dielectric layer, thus form the first electrode 510, the opening of the second electrode 520 and third electrode 530 difference correspondence, and then utilizing sputtering technology, metal level is formed in described first interlayer dielectric layer and opening, until described opening is filled, chemical mechanical milling tech is finally utilized to remove the unnecessary metal level of described first interlayer dielectric layer upper surface.
By described first electrode 510 and described third electrode 530 conducting mutually, using the first output terminals A 1 as described capacitance structure, and using described second electrode 520 as the technique of the second output terminals A 2 of described capacitance structure be: at upper formation second interlayer dielectric layer of described first interlayer dielectric layer (not shown), utilize photoetching and etching technics, metal interconnected groove is formed in described second interlayer dielectric layer, so that described first electrode 510 and described third electrode 530 are interconnected, and described second electrode 520 is come out, and then utilizing sputtering technology, metal level is formed in described metal interconnected groove, until described metal interconnected groove is filled, chemical mechanical milling tech is finally utilized to remove the unnecessary metal level of described second interlayer dielectric layer upper surface.Then, from the metal of the described metal interconnected groove be connected with third electrode 530 by first electrode 510, draw the first output terminals A 1, from the metal in the metal interconnected groove described second electrode 520, draw the second output terminals A 2.
Figure 6 shows that the equivalent circuit diagram of the capacitance structure that above-mentioned technique is formed, described first capacitance structure 21 equivalent capacity C
oxwith the equivalent capacity C of the second capacitance structure 41
oNOin parallel between the first output terminals A 1 and the second output terminals A 2.Like this, namely described capacitance structure can have larger capacitance, also can have thicker dielectric layer and bear larger voltage, have larger voltage endurance capability.
Further, the manufacture method of capacitance structure provided by the invention, in conjunction with existing technique, does not increase new technique.
So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. a manufacture method for capacitance structure, is characterized in that, the manufacture method of described capacitance structure at least comprises:
There is provided Semiconductor substrate, described Semiconductor substrate comprises outer peripheral areas and central area;
Form the grid structure of peripheral components in described outer peripheral areas, form the first capacitance structure on the semiconductor substrate simultaneously;
Form the grid structure of semiconductor memory in described central area, form the second capacitance structure simultaneously on described first capacitance structure, described second capacitive structure parts exposes the surface of described first capacitance structure;
Form the first electrode, the second electrode and third electrode, wherein, described first electrode is connected with described Semiconductor substrate, and described second electrode is connected with the surface of described first capacitance structure, and described third electrode is connected with the surface of described second capacitance structure; And described first electrode and the mutual conducting of described third electrode, as the first output of described capacitance structure, described second electrode is as the second output of described capacitance structure.
2. the manufacture method of capacitance structure according to claim 1, is characterized in that: the grid structure forming peripheral components in described outer peripheral areas, and the step simultaneously forming the first capacitance structure on the semiconductor substrate comprises:
The Semiconductor substrate of described outer peripheral areas forms oxide layer;
Described oxide layer is formed the first polysilicon layer;
Photoetching and etching technics is utilized to etch described first polysilicon layer and described oxide layer, to form grid structure and first capacitance structure of peripheral components respectively on the semiconductor substrate.
3. the manufacture method of capacitance structure according to claim 1, is characterized in that: the grid structure forming semiconductor memory in described central area, and the step simultaneously forming described second capacitance structure on described first capacitance structure comprises:
The surface of the Semiconductor substrate in described central area and described first capacitance structure forms ONO layer;
Described ONO layer forms the second polysilicon layer;
Utilize photoetching and etching technics described second polysilicon layer of etching and ONO layer to form grid structure and second capacitance structure of memory.
4. the manufacture method of capacitance structure according to claim 1, is characterized in that: described first capacitance structure is positioned at described outer peripheral areas.
5. the manufacture method of capacitance structure according to claim 1, is characterized in that: the thickness of described oxide layer is
the thickness of described ONO layer is
6. the manufacture method of capacitance structure according to claim 1, is characterized in that: described semiconductor memory is ETOXNORflash.
7. a capacitance structure, it is characterized in that, described capacitance structure at least comprises: the first capacitance structure that Semiconductor substrate is formed, the second capacitance structure that described first capacitance structure is formed, first electrode, the second electrode and third electrode, wherein, described first electrode is connected with described Semiconductor substrate, described second electrode is connected with the surface of described first capacitance structure, and described third electrode is connected with the surface of the second capacitance structure; And described first electrode and the mutual conducting of described third electrode, as the first output of described capacitance structure, described second electrode is as the second output of described capacitance structure.
8. capacitance structure according to claim 7, is characterized in that: the first capacitance structure comprises the oxide layer being positioned at described semiconductor substrate surface and the first polysilicon layer being positioned at described oxide layer surface; Described second capacitance structure comprises the ONO layer being positioned at described first polysilicon layer surface and the second polysilicon layer being positioned at described ONO layer surface.
9. a semiconductor memory, is characterized in that, described semiconductor memory at least comprises: capacitance structure as claimed in claim 7.
10. the manufacture method of semiconductor memory according to claim 9, is characterized in that: described semiconductor memory also comprises ETOXNORflash.
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| CN108376739A (en) * | 2018-01-25 | 2018-08-07 | 厦门市三安集成电路有限公司 | A kind of compound semiconductor device capacitance structure and preparation method thereof |
| CN113257739A (en) * | 2021-04-29 | 2021-08-13 | 长江存储科技有限责任公司 | Preparation method of semiconductor device, semiconductor device and storage device |
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