CN105097771A - Antifuse element, manufacturing method of antifuse element, and semiconductor device - Google Patents
Antifuse element, manufacturing method of antifuse element, and semiconductor device Download PDFInfo
- Publication number
- CN105097771A CN105097771A CN201410199530.3A CN201410199530A CN105097771A CN 105097771 A CN105097771 A CN 105097771A CN 201410199530 A CN201410199530 A CN 201410199530A CN 105097771 A CN105097771 A CN 105097771A
- Authority
- CN
- China
- Prior art keywords
- conductive layer
- conductive
- antifuse element
- conductive bumps
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The application discloses an antifuse element, a manufacturing method of an antifuse element, and a semiconductor device. The antifuse element comprises a first conductive layer, a second conductive layer, and a dielectric layer arranged between the first conductive layer and the second conductive layer. The antifuse element further comprises a first conductive protrusion, which is disposed at one side, close to the dielectric layer, of the first conductive layer. The width of one end, far from the first conductive layer, of the first conductive protrusion, is smaller than the width of the first conductive layer. The power consumption of the antifuse element is reduced, and the reliability of the antifuse element is improved.
Description
Technical field
The application relates to technical field of semiconductors, in particular to manufacture method and the semiconductor device of a kind of antifuse element, antifuse element.
Background technology
Antifuse element is one of element commonly used in semiconductor device, the initial condition of antifuse element is non-conduction and has very large impedance, when the voltage put on antifuse element exceedes certain level, the current path of a permanent conduction can be created.Antifuse element is widely used in programmable integrated circuit (IC).In specific programmable logic device (PLD), such as structured application-specific integrated circuits (ASIC), antifuse element for forming logical circuit wherein, and creates the customizable method for designing from standard IC design.In programmable read only memory, every bit lines comprises fuse and antifuse, carries out programming operation by of triggering in fuse and antifuse, and described programming is permanent and irreversible.
In the semiconductor device, a kind of typical structure of antifuse is configuration one piece of thin barrier layer between the electrode of two metallic conductors formations, and the material on described barrier layer is generally non-conduction amorphous silicon.When enough large voltage puts on antifuse, above-mentioned amorphous silicon changes polysilicon into, and forms together with described metallic conductor and have Low ESR and can the alloy body of conducting; The another kind of typical structure of antifuse is the alloy body that tungsten, titanium and silicon are formed.
But, along with the change of time, when applying higher voltage on antifuse element, very easily produce electron transfer phenomenon, make antifuse element can not generation effect under predetermined operating mode, reduce the reliability of antifuse element, and existing antifuse element needs the voltage of applying high, power consumption is large.
Therefore, need to propose a kind of antifuse element, the manufacture method of antifuse element and semiconductor device, to solve the problem.
Summary of the invention
The application aims to provide a kind of antifuse element, the manufacture method of antifuse element and semiconductor device, to solve the problem that antifuse element power consumption of the prior art is high, reliability is low.
To achieve these goals, according to an aspect of the application, provide a kind of antifuse element, the dielectric layer that this antifuse element comprises the first conductive layer, the second conductive layer and is arranged between the first conductive layer and the second conductive layer, this antifuse element also comprises: the first conductive bumps, be arranged on the side of the close dielectric layer of the first conductive layer, and the width of one end away from the first conductive layer of the first conductive bumps is less than the width of the first conductive layer.
Further, antifuse element also comprises the second conductive bumps, second conductive bumps is arranged on the side of the close dielectric layer of the second conductive layer, the width of one end away from the second conductive layer of the second conductive bumps is less than the width of the second conductive layer, and the first conductive bumps is relative with the protrusion direction of the second conductive bumps.
Further, the width of the end away from the first conductive layer of the first conductive bumps is decremented to zero gradually along the direction away from the first conductive layer.
Further, the width of the end away from the second conductive layer of the second conductive bumps is decremented to zero gradually along the direction away from the second conductive layer.
Further, the end face away from the first conductive layer of the first conductive bumps is arcwall face or inclined-plane.
Further, the end face away from the second conductive layer of the second conductive bumps is arcwall face or inclined-plane.
Further, the end away from the first conductive layer of the first conductive bumps is taper, and the end away from the second conductive layer of the second conductive bumps is also in taper.
Further, the first conductive layer is provided with the contact hole for being connected with wire with the second conductive layer, is provided with conducting medium layer in contact hole.
According to the another aspect of the application, provide a kind of semiconductor device, this semiconductor device comprises antifuse element, and antifuse element is above-mentioned antifuse element.
According to the one side again of the application, provide a kind of manufacture method of antifuse element, the manufacture method of this antifuse element comprises: etch the middle part of conducting block, make the intercell connector of conducting block only between the square block at remaining two ends and the square block being connected to two ends, now, one of the square block at conducting block two ends forms the first conductive layer, and another forms the second conductive layer; Etch intercell connector is disconnected to intercell connector, now, in intercell connector remainder, the part be connected on the first conductive layer forms the first conductive bumps; Between the first conductive layer and the second conductive layer, deposition forms dielectric layer.
Further, in intercell connector remainder, the part be connected on the second conductive layer forms the second conductive bumps.
Further, in the process of etching intercell connector, the width of the end away from the first conductive layer of the first conductive bumps is made to be reduced to zero gradually along the direction away from the first conductive layer.
Further, in the process of the intercell connector of etching, the width of the end away from the second conductive layer of the second conductive bumps is made to be reduced to zero gradually along the direction away from the second conductive layer.
Further, utilize photo-etching processes, be arcwall face or inclined-plane by the end face away from the first conductive layer of the first conductive bumps etching, be reduced to zero to make the width of the end away from the first conductive layer of the first conductive bumps gradually along the direction away from the first conductive layer.
Further, utilize photo-etching processes, be arcwall face or inclined-plane by the end face away from the second conductive layer of the second conductive bumps etching, be reduced to zero to make the width of the end away from the second conductive layer of the second conductive bumps gradually along the direction away from the second conductive layer.
Further, the manufacture method of antifuse element also comprises: after etching the middle part of conducting block, and on the first conductive layer and the second conductive layer, etching forms contact hole, and deposition forms conducting medium layer in the contact hole.
The technical scheme of application the application, antifuse element comprises the first conductive layer, the second conductive layer, dielectric layer and the first conductive bumps.Wherein, dielectric layer is arranged between the first conductive layer and the second conductive layer; First conductive bumps is arranged on the side of the close dielectric layer of the first conductive layer, and the width of one end away from the first conductive layer of the first conductive bumps is less than the width of the first conductive layer.In this application, owing to being provided with the first conductive bumps on the first conductive layer, and the width of one end away from the first conductive layer of the first conductive bumps is less than the width of the first conductive layer, when applying certain voltage at the two ends of antifuse element, electric charge on first conductive layer can be assembled to the direction of the first conductive bumps, and now, the electric field strength between the first conductive bumps to the second conductive layer is the strongest, be convenient to dielectric layer to puncture, realize the conducting function of antifuse element.It can thus be appreciated that, after first conductive layer arranges the first conductive bumps, only need to apply less voltage on two electrodes of antifuse element, just can realize the conducting function of antifuse element, power consumption is low, in addition, because the voltage applied on antifuse element is little, reduce the generation of electron transfer phenomenon, thus improve the reliability of antifuse element.
Accompanying drawing explanation
The Figure of description forming a application's part is used to provide further understanding of the present application, and the schematic description and description of the application, for explaining the application, does not form the improper restriction to the application.In the accompanying drawings:
Fig. 1 diagrammatically illustrates in the first execution mode of the application, the middle part of conducting block is etched to the vertical view of the structure of rear formation;
Fig. 2 diagrammatically illustrates in the first execution mode of the application, vertical view when etching intercell connector;
Fig. 3 diagrammatically illustrates in the first execution mode of the application, the vertical view after being etched away at the middle part of intercell connector;
Fig. 4 diagrammatically illustrates in the first execution mode of the application, the vertical view form dielectric layer between the first conductive layer and the second conductive layer after;
Fig. 5 diagrammatically illustrates in first execution mode of the application, the vertical view after the first conductive layer and the second conductive layer form contact hole;
Fig. 6 diagrammatically illustrates the vertical view of the first execution mode of the antifuse element of the application;
Fig. 7 diagrammatically illustrates in the second execution mode of the application, the middle part of conducting block is etched to the vertical view of the structure of rear formation;
Fig. 8 diagrammatically illustrates in the second execution mode of the application, vertical view when etching intercell connector;
Fig. 9 diagrammatically illustrates in the second execution mode of the application, the vertical view after being etched away at the middle part of intercell connector;
Figure 10 diagrammatically illustrates in the second execution mode of the application, the vertical view form dielectric layer between the first conductive layer and the second conductive layer after;
Figure 11 diagrammatically illustrates in second execution mode of the application, the vertical view after the first conductive layer and the second conductive layer form contact hole;
Figure 12 diagrammatically illustrates the vertical view of the second execution mode of the antifuse element of the application;
Figure 13 diagrammatically illustrates in the third execution mode of the application, the middle part of conducting block is etched to the vertical view of the structure of rear formation;
Figure 14 diagrammatically illustrates in the third execution mode of the application, vertical view when etching intercell connector;
Figure 15 diagrammatically illustrates in the third execution mode of the application, the vertical view after being etched away at the middle part of intercell connector;
Figure 16 diagrammatically illustrates in the third execution mode of the application, the vertical view form dielectric layer between the first conductive layer and the second conductive layer after;
Figure 17 diagrammatically illustrates in the 3rd execution mode of the application, the vertical view after the first conductive layer and the second conductive layer form contact hole;
Figure 18 diagrammatically illustrates the vertical view of the third execution mode of the antifuse element of the application;
Figure 19 diagrammatically illustrates the vertical view of the 4th execution mode of the antifuse element of the application; And
Figure 20 diagrammatically illustrates the flow chart of the manufacture method of the antifuse element of the application.
Description of reference numerals:
10, the first conductive layer; 11, the first conductive bumps; 20, the second conductive layer; 21, the second conductive bumps; 30, dielectric layer; 40, contact hole; 50, conducting medium layer; 60, conducting block; 61, intercell connector.
Embodiment
It should be noted that, when not conflicting, the embodiment in the application and the feature in embodiment can combine mutually.Below with reference to the accompanying drawings and describe the application in detail in conjunction with the embodiments.
It should be noted that used term is only to describe embodiment here, and be not intended to the illustrative embodiments of restricted root according to the application.As used herein, unless the context clearly indicates otherwise, otherwise singulative is also intended to comprise plural form, in addition, it is to be further understood that, when use belongs to " comprising " and/or " comprising " in this manual, it indicates existing characteristics, step, operation, device, assembly and/or their combination.
For convenience of description, here can usage space relative terms, as " ... on ", " in ... top ", " at ... upper surface ", " above " etc., be used for the spatial relation described as a device shown in the figure or feature and other devices or feature.Should be understood that, space relative terms is intended to comprise the different azimuth in use or operation except the described in the drawings orientation of device.Such as, " in other devices or structure below " or " under other devices or structure " will be positioned as after if the device in accompanying drawing is squeezed, being then described as the device of " above other devices or structure " or " on other devices or structure ".Thus, exemplary term " in ... top " can comprise " in ... top " and " in ... below " two kinds of orientation.This device also can other different modes location (90-degree rotation or be in other orientation), and relatively describe space used here and make respective explanations.
Illustrative embodiments according to the application will be described in more detail below.But these illustrative embodiments can be implemented by multiple different form, and should not be interpreted as being only limited to execution mode set forth herein.Should be understood that, there is provided these execution modes be in order to make the application open thorough and complete, and the design of these illustrative embodiments is fully conveyed to those of ordinary skill in the art, in the accompanying drawings, for the sake of clarity, expand the thickness in layer and region, and use the device that identical Reference numeral represents identical, thus will omit description of them.
As what introduce in background technology, existing antifuse element is configuration one piece of thin barrier layer between the electrode of two metallic conductors formations.The metal electrode normally layer of metal layer of this antifuse element, in tabular, this antifuse element is in the process of conducting, need to apply very high voltage, could, by barrier-layer puncture, make antifuse element realize its conducting function, in addition, in the high-tension process of applying, easily there is transport phenomena in the electronics on the electrode that metallic conductor is formed, and makes antifuse element can not produce corresponding effect under predetermined operating mode.Visible, existing antifuse element not only power consumption and also reliability low.For the above-mentioned defect of prior art, this application provides a kind of antifuse element, the manufacture method of antifuse element and semiconductor device.The antifuse element of the application, the manufacture method of antifuse element and semiconductor device is introduced below in conjunction with accompanying drawing.
Fig. 6 diagrammatically illustrates the vertical view of the first execution mode of the antifuse element of the application.According to the present embodiment, antifuse element comprises the first conductive layer 10, second conductive layer 20, dielectric layer 30 and the first conductive bumps 11.Wherein, dielectric layer 30 is arranged between the first conductive layer 10 and the second conductive layer 20; First conductive bumps 11 is arranged on the side of the close dielectric layer 30 of the first conductive layer 10, and the width of one end away from the first conductive layer 10 of the first conductive bumps 11 is less than the width of the first conductive layer 10.In the present embodiment, owing to being provided with the first conductive bumps 11 on the first conductive layer 10, and the width of one end away from the first conductive layer 10 of the first conductive bumps 11 is less than the width of the first conductive layer 10, when applying certain voltage at the two ends of antifuse element, electric charge on first conductive layer 10 can be assembled to the direction of the first conductive bumps 11, now, electric field strength between first conductive bumps 11 to the second conductive layer 20 is the strongest, be convenient to dielectric layer 30 to puncture, realize the conducting function of antifuse element.It can thus be appreciated that, after first conductive layer 10 arranges the first conductive bumps 11, only need to apply less voltage on two electrodes of antifuse element, just can realize the conducting function of antifuse element, power consumption is low, in addition, because the voltage applied on antifuse element is little, reduce the generation of electron transfer phenomenon, thus improve the reliability of antifuse element.It should be noted that, in the application, said width all refers to the width watched in the vertical view of antifuse element.
Preferably, antifuse element also comprises the second conductive bumps 21, this second conductive bumps 21 is arranged on the side of the close dielectric layer 30 of the second conductive layer 20, the width of one end away from the second conductive layer 20 of the second conductive bumps 21 is less than the width of the second conductive layer 20, and the first conductive bumps 11 is relative with the protrusion direction of the second conductive bumps 21.Second conductive layer 20 arranges the first conductive bumps 11 and makes the second conductive bumps 21 relative with the first conductive bumps 11, after voltage is applied to antifuse element, between first conductive bumps 11 and the second conductive bumps 21, electric field can sharply strengthen, easier being punctured by dielectric layer 30 and realize the conducting function of antifuse element.
Preferably, the width of the end away from the first conductive layer 10 of the first conductive bumps 11 is decremented to zero gradually along the direction away from the first conductive layer 10, when the first conductive bumps 11 be zero away from the first conductive layer 10 wide time, one end away from the first conductive layer 10 of the first conductive bumps 11 is a tip.Apply after voltage antifuse element, the first conductive bumps 11 is the most concentrated at the electric charge at tip location place, and the electric field of the first conductive bumps 11 to the second conductive layer 20 is the strongest, is easilier punctured and conducting by dielectric layer 30.According to the present embodiment, only need apply the conducting function that less voltage just can realize antifuse element, reduce further the power consumption of antifuse element and the probability of electron transfer phenomenon occurs.In the present embodiment, the first conductive bumps 11 and the second conductive bumps 21 are two, in other execution modes of the application, the first conductive bumps 11 and the second conductive bumps 21 all can also be arranged one.
Preferably, the width of the end away from the second conductive layer 20 of the second conductive bumps 21 is decremented to zero gradually along the direction away from the second conductive layer 20, makes one end away from the second conductive layer 20 of the second conductive bumps 21 form a tip.The same with the first conductive bumps 11, after voltage is applied to antifuse element, electric charge can be concentrated at the tip of the second conductive bumps 21, further increase the electric field strength between the first conductive layer 10 and the second conductive layer 20, easier dielectric layer 30 between first conductive layer 10 and the second conductive layer 20 to be punctured, and then reduce the power consumption of antifuse element and the probability of phenomenon of electron transfer occurs.
Refer again to shown in Fig. 6, in the present embodiment, the end face away from the first conductive layer 10 of the first conductive bumps 11 is arcwall face, the width of one end away from the first conductive layer 10 of the first conductive bumps 11 is diminished gradually along the direction away from the first conductive layer 10, and then make one end of the first conductive bumps 11 in most advanced and sophisticated, structure is simple, is easy to realize.In other embodiments of the invention; the end face away from the first conductive layer 10 of the first conductive bumps 11 can also be other shapes such as inclined-planes; as long as one end away from the first conductive layer 10 of the first conductive bumps 11 can be made in most advanced and sophisticated mode, all in the scope of the application's protection.
Preferably, the end face away from the second conductive layer 20 of the second conductive bumps 21 is also arcwall face or inclined-plane, is convenient to one end away from the second conductive layer 20 of the second conductive bumps 21 to be set to cutting-edge structure.
In this application, the first conductive layer 10 and the second conductive layer 20 are provided with contact hole 40, and conducting medium layer 50 is set in contact hole 40, be convenient to antifuse element to be connected with wire.
Shown in Fig. 1 to Fig. 6 and Figure 20, specifically introduce the manufacture method of the antifuse element of the first execution mode.The manufacture method of this antifuse element comprises: first etch the middle part of conducting block 60, make the intercell connector 61 of conducting block 60 only between the square block at remaining two ends and the square block being connected to two ends, now, one of the square block at conducting block 60 two ends forms the first conductive layer 10, and another forms the second conductive layer 20; Then etch intercell connector 61 is disconnected to intercell connector 61, now, in intercell connector 61 remainder, the part be connected on the first conductive layer 10 forms the first conductive bumps 11; Last deposition between the first conductive layer 10 and the second conductive layer 20 forms dielectric layer 30.In this manufacture method, conducting block 60 can be one or more in polysilicon layer, metal level, conductive metal nitride layer, conductive metal oxide layer and metal silicide layer, and wherein, the constituent material of metal level can be tungsten, nickel or titanium; Conductive metal nitride layer can comprise titanium nitride layer; Conductive metal oxide layer can comprise iridium oxide layer; Metal silicide layer can comprise titanium silicide layer.Dielectric layer 30 can be amorphous silicon layer.According to this method, the antifuse element obtaining there is the first conductive bumps 11 can be manufactured, electric charge when applying certain voltage at the two ends of antifuse element on the first conductive layer 10 can be assembled to the direction of the first conductive bumps 11, now, electric field strength between first conductive bumps 11 to the second conductive layer 20 is the strongest, be convenient to dielectric layer 30 to puncture, realize the conducting function of antifuse element.It can thus be appreciated that, after first conductive layer 10 arranges the first conductive bumps 11, only need to apply less voltage on two electrodes of antifuse element, just can realize the conducting function of antifuse element, power consumption is low, in addition, because the voltage applied on antifuse element is little, reduce the generation of electron transfer phenomenon, thus improve the reliability of antifuse element.
Specifically, first, the middle part of conducting block 60 is etched, make the intercell connector 61 of conducting block 60 only between the square block at remaining two ends and the square block being connected to two ends, as shown in Figure 1.What adopt in present embodiment is the technique of photoengraving, in other embodiments of the application, other techniques can also be adopted to etch conducting block 60.
Then the intercell connector 61 of the square block connecting conducting block 60 two ends is etched, intercell connector 61 disconnected thus forms the first conductive bumps 11 and the second conductive bumps 21, and making the first conductive bumps 11 relative with the second conductive bumps 21.In intercell connector 61 remainder, the part be connected on the second conductive layer 20 forms the second conductive bumps 21.It should be noted that, in order to form the first conductive bumps 11 and the second conductive bumps 21, etching process is preferably carried out at the middle part of intercell connector 61.
Preferably, in the process of etching intercell connector 61, the width of the end away from the first conductive layer 10 of the first conductive bumps 11 is made to be reduced to zero gradually along the direction away from the first conductive layer 10; Make the width of the end away from the second conductive layer 20 of the second conductive bumps 21 be reduced to zero gradually along the direction away from the second conductive layer 20 simultaneously.And then one end away from the second conductive layer 20 of one end away from the first conductive layer 10 of the first conductive bumps 11 and the second conductive bumps 21 is tapered off to a point structure, as shown in Figure 3.
In order to the end making the first conductive bumps 11 relative with the second conductive bumps 21 is cutting-edge structure.Present embodiment utilizes the photoresist with pattern (circle in Fig. 2) to carry out photoengraving to intercell connector 61, such as circular or oval, as shown in Figure 2, the end face away from the first conductive layer 10 of the first conductive bumps 11 is etched for arcwall face, maybe the end face away from the second conductive layer 20 stating the second conductive bumps 21 is etched as arcwall face, make the width of the end away from the first conductive layer 10 of the first conductive bumps 11 along being reduced to zero or make the width of the end away from the second conductive layer 20 of the second conductive bumps 21 be reduced to zero gradually along the direction away from the second conductive layer 20 gradually away from the direction of the first conductive layer 10, thus the structure that tapers off to a point.
Then between the first conductive layer 10 and the second conductive layer 20, deposition forms dielectric layer 30.Form dielectric layer 30 and can adopt atomic deposition or pecvd process etc.
Finally the first conductive layer 10 and the second conductive layer 20 are etched, form contact hole 40, and deposition forms conducting medium layer 50 in contact hole 40, is convenient to antifuse element to be connected with wire.
Shown in Figure 12, embodiment there is provided a kind of antifuse element according to the second of the application.The structure of this antifuse element and the substantially identical of the first execution mode, difference is, in the present embodiment, first conductive bumps 11 and the second conductive bumps 21 all only have one, and be only provided with a cutting-edge structure, even if the width away from the first conductive layer 10 end of the first conductive bumps 11 is reduced to zero gradually along the direction away from the first conductive layer 10.
See shown in Fig. 7 to Figure 12, due to the structure of the antifuse element of present embodiment and the substantially the same of the first execution mode, so the method manufactured in the method for antifuse element of present embodiment and the first execution mode is basically identical, difference is, when the middle part of etching conductive block 60, the middle part of conducting block 60 is made only to leave an intercell connector 61, as shown in Figure 7.Then the photoresist with triangle pattern is utilized to carry out photoengraving to intercell connector 61, intercell connector 61 is made to form the first conductive bumps 11 and the second conductive bumps 21, now, the end face away from the first conductive layer 10 of the first conductive bumps 11 is inclined-plane, and then the end away from the first conductive layer 10 making the first conductive bumps 11 is cutting-edge structure.
Shown in Figure 18, embodiment there is provided a kind of antifuse element according to the third of the application.The structure of this antifuse element and the first execution mode basically identical, difference is, in present embodiment, the width of the first conductive bumps 11 and the second conductive bumps 21 can not change, but two the first conductive bumps 11 and two the second conductive bumps 21 are set, now, a pair relative tip is had between the first tiltedly right conductive bumps 11 and the second conductive bumps 21, when voltage is applied to antifuse element, this sharply strengthens the electric field between tip, thus is punctured by dielectric layer and realize the conducting function of antifuse element.
In conjunction with shown in Figure 13 to 18, specifically introduce the manufacture method of the antifuse element of present embodiment.The manufacture method of the antifuse element of present embodiment and the basically identical of the first execution mode, difference is, in process in the middle part of etching conductive block 60, be a bending intercell connector (as shown in figure 13) by intercell connector 61 etching, then with the photoresist with rectangle pattern, intercell connector 61 is etched (as shown in figure 14), it should be noted that, in etching process, the photoresist with rectangle pattern need be made to favour intercell connector 61, guarantee to form one or more pairs of relative cutting-edge structure.
Shown in Figure 19, according to the 4th embodiment of the application, provide a kind of antifuse element, the structure of this antifuse element and the basically identical of the second execution mode, difference is, in present embodiment, the end away from the first conductive layer 10 of the first conductive bumps 11 and the end away from the second conductive layer 20 of the second conductive bumps 21 are all in taper.
Basically identical in the manufacture method of the antifuse element in present embodiment and the second embodiment, difference is, the figure of the photoresist adopted when etching intercell connector 61 is different, as long as make the end away from the second conductive layer 20 away from the first conductive layer 10 and the second conductive bumps 21 of the first conductive bumps 11 all in taper, repeat no more herein.Preferably, the first conductive bumps 11 shown in Figure 19 and the second conductive bumps 21 are opposite to each other.
According to the application the 5th embodiment there is provided a kind of semiconductor device, and this semiconductor device comprises antifuse element, and this antifuse element is the antifuse element in above-mentioned arbitrary execution mode.
From above description, can find out, the application's the above embodiments achieve following technique effect: owing to being provided with the first conductive bumps on the first conductive layer, and the width of one end away from the first conductive layer of the first conductive bumps is less than the width of the first conductive layer, the electric charge kept off when the two ends of antifuse element apply certain voltage on the first conductive layer can be assembled to the direction of the first conductive bumps, now, electric field strength between first conductive bumps to the second conductive layer is the strongest, be convenient to dielectric layer to puncture, realize the conducting function of antifuse element.It can thus be appreciated that, after first conductive layer arranges the first conductive bumps, only need to apply less voltage on two electrodes of antifuse element, just can realize the conducting function of antifuse element, power consumption is low, in addition, because the voltage applied on antifuse element is little, reduce the generation of electron transfer phenomenon, thus improve the reliability of antifuse element.
The foregoing is only the preferred embodiment of the application, be not limited to the application, for a person skilled in the art, the application can have various modifications and variations.Within all spirit in the application and principle, any amendment done, equivalent replacement, improvement etc., within the protection range that all should be included in the application.
Claims (16)
1. an antifuse element, the dielectric layer comprising the first conductive layer, the second conductive layer and be arranged between the first conductive layer and the second conductive layer, is characterized in that, also comprise:
First conductive bumps, is arranged on the side of the close described dielectric layer of described first conductive layer, and the width of one end away from described first conductive layer of described first conductive bumps is less than the width of described first conductive layer.
2. antifuse element according to claim 1, it is characterized in that, described antifuse element also comprises the second conductive bumps, described second conductive bumps is arranged on the side of the close described dielectric layer of described second conductive layer, the width of one end away from described second conductive layer of described second conductive bumps is less than the width of described second conductive layer, and described first conductive bumps is relative with the protrusion direction of described second conductive bumps.
3. antifuse element according to claim 1, is characterized in that, the width of the end away from described first conductive layer of described first conductive bumps is decremented to zero gradually along the direction away from described first conductive layer.
4. antifuse element according to claim 2, is characterized in that, the width of the end away from described second conductive layer of described second conductive bumps is decremented to zero gradually along the direction away from described second conductive layer.
5. antifuse element according to claim 1, is characterized in that, the end face away from described first conductive layer of described first conductive bumps is arcwall face or inclined-plane.
6. antifuse element according to claim 2, is characterized in that, the end face away from described second conductive layer of described second conductive bumps is arcwall face or inclined-plane.
7. antifuse element according to claim 2, is characterized in that, the end away from the first conductive layer of described first conductive bumps is taper, and the end away from described second conductive layer of described second conductive bumps is also in taper.
8. antifuse element according to any one of claim 1 to 7, is characterized in that, described first conductive layer is provided with the contact hole for being connected with wire with described second conductive layer, is provided with conducting medium layer in described contact hole.
9. a semiconductor device, comprises antifuse element, it is characterized in that, the antifuse element of described antifuse element according to any one of claim 1 to 8.
10. a manufacture method for antifuse element, is characterized in that, comprising:
Etch the middle part of conducting block, make the intercell connector of described conducting block only between the square block at remaining two ends and the described square block being connected to two ends, now, one of the square block at described conducting block two ends forms the first conductive layer, and another forms the second conductive layer;
Etch described intercell connector is disconnected to described intercell connector, now, in described intercell connector remainder, the part be connected on described first conductive layer forms the first conductive bumps;
Between described first conductive layer and described second conductive layer, deposition forms dielectric layer.
The manufacture method of 11. antifuse elements according to claim 10, is characterized in that, in described intercell connector remainder, the part be connected on described second conductive layer forms described second conductive bumps.
The manufacture method of 12. antifuse elements according to claim 10, it is characterized in that, in the process of the described intercell connector of etching, the width of the end away from described first conductive layer of described first conductive bumps is made to be reduced to zero gradually along the direction away from described first conductive layer.
The manufacture method of 13. antifuse elements according to claim 11, it is characterized in that, in the process of the intercell connector described in etching, the width of the end away from described second conductive layer of described second conductive bumps is made to be reduced to zero gradually along the direction away from described second conductive layer.
The manufacture method of 14. antifuse elements according to claim 12, it is characterized in that, utilize photo-etching processes, the end face away from described first conductive layer of described first conductive bumps is etched for arcwall face or inclined-plane, be reduced to zero to make the width of the end away from described first conductive layer of described first conductive bumps gradually along the direction away from described first conductive layer.
The manufacture method of 15. antifuse elements according to claim 13, it is characterized in that, utilize photo-etching processes, the end face away from described second conductive layer of described second conductive bumps is etched for arcwall face or inclined-plane, be reduced to zero to make the width of the end away from described second conductive layer of described second conductive bumps gradually along the direction away from described second conductive layer.
16. according to claim 10 to the manufacture method of the antifuse element according to any one of 15, it is characterized in that, the manufacture method of described antifuse element also comprises: after etching the middle part of described conducting block, on described first conductive layer and described second conductive layer, etching forms contact hole, and deposition forms conducting medium layer in described contact hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410199530.3A CN105097771B (en) | 2014-05-12 | 2014-05-12 | Antifuse element, the manufacture method of antifuse element and semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410199530.3A CN105097771B (en) | 2014-05-12 | 2014-05-12 | Antifuse element, the manufacture method of antifuse element and semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105097771A true CN105097771A (en) | 2015-11-25 |
| CN105097771B CN105097771B (en) | 2017-12-19 |
Family
ID=54577863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410199530.3A Active CN105097771B (en) | 2014-05-12 | 2014-05-12 | Antifuse element, the manufacture method of antifuse element and semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105097771B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5646438A (en) * | 1994-11-12 | 1997-07-08 | Deutsche Itt Industries Gmbh | Programmable semiconductor memory |
| US6396120B1 (en) * | 2000-03-17 | 2002-05-28 | International Business Machines Corporation | Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application |
| CN102237395A (en) * | 2010-05-07 | 2011-11-09 | 电力集成公司 | Integrated transistor and anti-fuse as programming element for a high-voltage integrated circuit |
| CN102341904A (en) * | 2009-03-02 | 2012-02-01 | 株式会社村田制作所 | Antifuse device |
| CN102473521A (en) * | 2009-07-22 | 2012-05-23 | 株式会社村田制作所 | Dielectric thin film element and method for producing the same |
-
2014
- 2014-05-12 CN CN201410199530.3A patent/CN105097771B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5646438A (en) * | 1994-11-12 | 1997-07-08 | Deutsche Itt Industries Gmbh | Programmable semiconductor memory |
| US6396120B1 (en) * | 2000-03-17 | 2002-05-28 | International Business Machines Corporation | Silicon anti-fuse structures, bulk and silicon on insulator fabrication methods and application |
| CN102341904A (en) * | 2009-03-02 | 2012-02-01 | 株式会社村田制作所 | Antifuse device |
| CN102473521A (en) * | 2009-07-22 | 2012-05-23 | 株式会社村田制作所 | Dielectric thin film element and method for producing the same |
| CN102237395A (en) * | 2010-05-07 | 2011-11-09 | 电力集成公司 | Integrated transistor and anti-fuse as programming element for a high-voltage integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105097771B (en) | 2017-12-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9583700B2 (en) | RRAM process with roughness tuning technology | |
| CN101174607B (en) | Fuse structures and integrated circuit devices | |
| US7282679B2 (en) | Electrical contact connection and method for forming such a contact connection | |
| US9245925B1 (en) | RRAM process with metal protection layer | |
| CN105514112A (en) | One time programmable non-volatile memory | |
| CN109524413A (en) | Semiconductor storage | |
| CN107785420A (en) | Semiconductor devices and its manufacture method | |
| CN104347589B (en) | A kind of anti-fuse structures | |
| CN105097771A (en) | Antifuse element, manufacturing method of antifuse element, and semiconductor device | |
| CN102130092A (en) | Fuse device and preparation method thereof | |
| TWI756882B (en) | Anti-fuse one-time programmable memory cell and related array structure | |
| US8390326B2 (en) | Method for fabrication of a semiconductor element and structure thereof | |
| KR101699165B1 (en) | Integrated circuit having slot via and method of forming the same | |
| CN102760720B (en) | Electronic programmable fuse wire vacant active area adding method and electronic programmable fuse wire | |
| CN104576600B (en) | A kind of anti-fuse structures | |
| US9852983B1 (en) | Fabricating method of anti-fuse structure | |
| CN114005802B (en) | Power device and manufacturing method thereof | |
| CN210110756U (en) | Memory cell and anti-fuse structure | |
| CN103296004A (en) | Anti-fuse element and manufacturing method thereof | |
| CN203553153U (en) | Anti-fuse structure | |
| US8143695B1 (en) | Contact fuse one time programmable memory | |
| US20080093702A1 (en) | Semiconductor device having a passive device | |
| CN109166841B (en) | Electrically programmable polysilicon fuse device structure | |
| US7973559B2 (en) | Method for fabrication of a semiconductor element and structure thereof | |
| US8860177B2 (en) | Semiconductor device and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |