CN105097711B

CN105097711B - Semiconductor devices and forming method thereof

Info

Publication number: CN105097711B
Application number: CN201410184886.XA
Authority: CN
Inventors: 刘金华
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2014-05-04
Filing date: 2014-05-04
Publication date: 2018-03-30
Anticipated expiration: 2034-05-04
Also published as: CN105097711A

Abstract

The forming method of a kind of semiconductor devices and forming method thereof, wherein semiconductor devices includes：Substrate is provided, substrate includes the first semiconductor layer, the insulating barrier positioned at the first semiconductor layer surface and the second semiconductor layer positioned at surface of insulating layer, substrate has first area, second area and the 3rd region, second area and first area and the 3rd region are adjacent, wherein, the thickness of insulating layer in first area and the 3rd region is more than the thickness of insulating layer of second area, and the insulating barrier lower surface of first area, second area and the 3rd region flushes；Grid structure is formed in the second semiconductor layer surface of second area；Doped region is formed in the first area of grid structure both sides and the 3rd the second semiconductor layer of region.Thickness of insulating layer below grid structure of the present invention is less than the thickness of insulating layer below doped region, because the insulating barrier effective resistance below grid structure is smaller, therefore can be effectively improved the threshold voltage of semiconductor devices.

Description

Semiconductor devices and forming method thereof

Technical field

The present invention relates to field of semiconductor manufacture technology, more particularly to semiconductor devices and forming method thereof.

Background technology

With the progress of semiconductor technology, integrated circuit is towards high integration, high speed and the trend development of low-power consumption, body The technique of silicon (Bulk Silicon) substrate and body silicon device (device based on the manufacture of body silicon substrate) just close to physics limit, Severe challenge is run into terms of integrated circuit feature size is further reduced.Industry thinks silicon-on-insulator (SOI at present： Silicon on Insulator) substrate and SOI device be one of preferred plan of substitution body silicon and body silicon device.

SOI substrate is a kind of substrate for IC manufacturing, compared with the body silicon substrate widely applied at present, SOI Substrate has many advantages：Using the parasitic capacitance of integrated circuit made of SOI substrate is small, integrated level is high, short-channel effect is small, Speed is fast, and can also realize the medium isolation of component in integrated circuit, eliminates the parasitic door bolt in body silicon integrated circuit Lock effect.

Fig. 1 is refer to, Fig. 1 is the cross-sectional view of the semiconductor devices formed using SOI substrate, including：Bottom silicon Layer 100, the insulating barrier 101 positioned at the surface of bottom silicon layer 100, the top silicon layer 102 positioned at the surface of insulating barrier 101, the three-decker Form SOI substrate；Grid structure positioned at the top surface of silicon layer 102, including gate oxide 103 and grid conductive layer 104, adjacent grid The side wall 105 of pole structure side wall；Doped region 106 in the top silicon layer 102 of grid structure both sides.

However, the threshold voltage of the semiconductor devices of above-mentioned offer is difficult to adjust, the application of semiconductor devices is restricted.

The content of the invention

The present invention solves the problems, such as to be to provide a kind of semiconductor devices and forming method thereof solve to be difficult to adjust semiconductor device The problem of part threshold voltage, while ensure that the probability of semiconductor devices generation soft error is low.

To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, including：Substrate is provided, it is described Substrate includes the first semiconductor layer, the insulating barrier positioned at the first semiconductor layer surface and the second half positioned at surface of insulating layer Conductor layer, the substrate have first area, second area and the 3rd region, the second area and first area and the 3rd area Domain is adjacent, wherein, the thickness of insulating layer in first area and the 3rd region is more than the thickness of insulating layer of second area, the firstth area The insulating barrier lower surface in domain, second area and the 3rd region flushes, and first area, the second of second area and the 3rd region Semiconductor layer surface flushes；Grid structure is formed in the second semiconductor layer surface of the second area；In the grid Doped region is formed in the first area of structure both sides and the 3rd the second semiconductor layer of region.

Optionally, the forming step of the substrate includes：Base with first area, second area and the 3rd region is provided Bottom, the substrate include the 3rd semiconductor layer, the dielectric film positioned at the 3rd semiconductor layer surface and positioned at insulating film surfaces 4th semiconductor layer；Patterned mask layer is formed in the substrate surface；Using the patterned mask layer as mask, etching The 4th semiconductor layer of second area and the dielectric film of segment thickness are removed, groove is formed in the second area, it is remaining Insulating barrier of the dielectric film as substrate；Form the 5th semiconductor layer of the full groove of filling, the 3rd semiconductor layer, insulating barrier with And the 5th semiconductor layer collectively constitute substrate.

Optionally, the forming step of the 5th semiconductor layer includes：Form the semiconductor film of the full groove of filling, institute State semiconductor film top surface and be higher than patterned mask layer top surface；The semiconductor film is planarized, until semiconductor film Top surface flushes with patterned mask layer top surface；The semiconductor film of segment thickness is removed, remaining semiconductor film is 5th semiconductor layer, and the 5th semiconductor layer surface flushes with the 4th semiconductor layer surface, wherein, the 4th half Second semiconductor layer of the conductor layer as first area and the 3rd region, the 5th semiconductor layer are led as the second the half of second area Body layer.

Optionally, the forming step of the 5th semiconductor layer includes：Form the semiconductor film of the full groove of filling, institute State semiconductor film and be also covered in the 4th semiconductor layer surface；Planarize semiconductor film and form the 5th semiconductor layer；4th half Conductor layer and the 5th semiconductor layer collectively as first area and the 3rd region the second semiconductor layer, the 5th half of second area the Second semiconductor layer of the conductor layer as second area.

Optionally, the forming step of the substrate includes：There is provided with the first of first area, second area and the 3rd region Primordium bottom, the initial substrate include the 3rd semiconductor layer and the dielectric film positioned at the 3rd semiconductor layer surface；Etching removes The dielectric film of second area segment thickness forms groove, insulating barrier of the dielectric film after etching as substrate；The 4th half is provided to lead Body layer；Etching removes the 4th semiconductor layer of segment thickness, is formed with the 5th raised semiconductor layer；There is groove by described in Initial substrate be bonded with the 5th semiconductor layer, projection is placed exactly in groove, surface of insulating layer and the 5th half Conductor layer surface is in contact, second semiconductor layer of the 5th semiconductor layer as substrate after bonding.

Accordingly, the present invention also provides a kind of semiconductor devices, including：Substrate, the substrate include the first semiconductor layer, Insulating barrier positioned at the first semiconductor layer surface and the second semiconductor layer positioned at surface of insulating layer, the substrate have the One region, second area and the 3rd region, the second area and first area and the 3rd region are adjacent, wherein, the firstth area The thickness of insulating layer in domain and the 3rd region is more than the thickness of insulating layer of second area, first area, second area and the 3rd region Insulating barrier lower surface flush, and the second semiconductor layer surface of first area, second area and the 3rd region flushes； Positioned at the grid structure of the second semiconductor layer surface of second area；Positioned at the first area of grid structure both sides and the 3rd region The doped region of second semiconductor layer.

Optionally, second semiconductor layer in the first area and the 3rd region is made up of the 4th semiconductor layer, and described Second semiconductor layer in two regions is made up of the 5th semiconductor layer, the 4th semiconductor layer surface and the 5th semiconductor layer Top surface flushes.

Optionally, second semiconductor layer in the first area and the 3rd region is by the 4th semiconductor layer and positioned at the 4th half 5th semiconductor layer of conductor layer surface is formed, and the second semiconductor layer of second area is made up of the 5th semiconductor layer, and first The 5th semiconductor layer surface in region, second area and the 3rd region flushes.

Optionally, the second semiconductor layer of the first area, second area and the 3rd region is by the 5th semiconductor layer structure Into, and the 5th semiconductor layer of first area, second area and the 3rd region flushes.

Compared with prior art, technical scheme has advantages below：

The embodiment of the present invention provides a kind of forming method of semiconductor devices, wherein, there is provided there is first area, the secondth area Domain and the substrate in the 3rd region, the second area and first area and the 3rd region are adjacent, and the substrate includes the first half Conductor layer, insulating barrier and the second semiconductor layer, and the thickness of insulating layer in first area and the 3rd region is exhausted more than second area Second layer semiconductor thickness in edge layer thickness, first area and the 3rd region is less than the second layer semiconductor thickness of second area； Grid structure is formed in the second semiconductor layer surface of second area, in the first area of grid structure both sides and the 3rd region the Doped region is formed in two semiconductor layers.In the embodiment of the present invention, because the thickness of insulating layer below grid structure is less than doped region The thickness of insulating layer of lower section, therefore, the effective resistance value of the insulating barrier below grid structure are smaller, are applied when to the first semiconductor layer When adding bias voltage, because the effective resistance value below grid structure is small, the bias voltage passes through the electricity consumed during insulating barrier Pressure is smaller, so as to get the voltage up to the second semiconductor layer (i.e. channel region) below grid structure is larger, is applied to by improving The voltage of channel region, the threshold voltage of semiconductor devices can be effectively adjusted, improve the electric property of semiconductor devices；And And because the thickness of insulating layer below doped region is thicker, the insulating barrier can effectively stop the Doped ions in doped region Diffuse in the first semiconductor layer, reduce the error rate of semiconductor devices.

Further, in the embodiment of the present invention, the semiconductor layer of second area the 4th and segment thickness dielectric film are etched exhausted After forming groove in velum, the semiconductor film of the full groove of filling is formed using epitaxy technique, is formed due to epitaxy technique Semiconductor film has the trend grown along the 4th semiconductor layer material lattice bearing of trend so that the semiconductor film of formation and the 4th Semiconductor layer contact is close；The 5th semiconductor layer, the 4th semiconductor layer and the are formed after subsequently being planarized to semiconductor film Five semiconductor layers are collectively as the second semiconductor layer of substrate, and therefore, the second semiconductor layer of formation is functional, so as to favourable In the excellent semiconductor devices of formation electric property.

Further, in the embodiment of the present invention, patterned mask layer, the figure of the reservation are retained after the formation of the recess The mask layer of change both can also play alignment effect, specifically, due to figure as the stop-layer of planarization semiconductor film The opening of the mask layer of change is located at second area, and after forming gate oxidation films in patterned mask layer, advantageously reduce Second area forms the technology difficulty of grid structure.

Further, in the embodiment of the present invention, the gate structure sidewall is located at second area border, in second area or In first area and the 3rd region, the distance of the gate structure sidewall to second area border is 0 angstrom to 100 angstroms, so as to enter One step reduces the graphical technology difficulty for forming grid structure.

The embodiment of the present invention also provides a kind of structural behaviour superior semiconductor devices, including with first area, second Region and the substrate in the 3rd region, the second area and first area and the 3rd region are adjacent, and the substrate includes first Semiconductor layer, the insulating barrier positioned at the first semiconductor layer surface and the second semiconductor layer positioned at surface of insulating layer, and first The thickness of insulating layer in region and the 3rd region is more than the thickness of insulating layer of second area, first area, second area and the 3rd area The insulating barrier lower surface in domain flushes；Positioned at the grid structure of the second semiconductor layer surface of second area；Positioned at grid structure The first area of both sides and the doped region of the 3rd the second semiconductor layer of region.Thickness of insulating layer below grid structure is less than doping The thickness of insulating barrier below area so that the insulating barrier effective resistance below grid structure is smaller, is applied when to the first semiconductor layer When adding bias voltage, before the second semiconductor layer (i.e. channel region) that bias voltage is reached below grid structure, grid structure The bias voltage amount of underlying insulating layer consumption is less, therefore the bias voltage amount for being actually reached channel region is larger, so as to effective Adjust threshold voltage of semiconductor device；Simultaneously as the thickness of insulating layer below doped region is thicker, it can effectively stop doping Ion is diffused into the first semiconductor layer in area, reduces the probability that soft error occurs for semiconductor devices, improves semiconductor devices Reliability.

Brief description of the drawings

Fig. 1 is an embodiment semiconductor devices cross-sectional view；

Fig. 2 to Fig. 9 is one embodiment of the invention semiconductor devices forming process cross-sectional view；

Figure 10 to Figure 14 is another embodiment of the present invention semiconductor devices forming process cross-sectional view；

Figure 15 to Figure 19 is further embodiment of this invention semiconductor devices forming process cross-sectional view.

Embodiment

From background technology, the threshold voltage of prior art semiconductor devices is difficult to adjust, the application of semiconductor devices It is restricted.

Found for semiconductor devices research, the semiconductor devices manufactured on soi substrates, adjust the threshold of semiconductor devices Threshold voltage, achieved the goal essentially by the bias voltage on bottom silicon layer is changed.Apply typically by bottom silicon layer Bias voltage (body bias voltage), to change the magnitude of voltage on the top silicon layer (i.e. channel region) below grid structure, To adjust the threshold voltage of semiconductor devices；However, although it is applied with larger bias voltage, semiconductor devices threshold to bottom silicon layer The limitation that threshold voltage improves.

For semiconductor devices carry out further study show that, to bottom silicon layer apply bias voltage after, the bias voltage Insulating barrier can be first passed through before the top silicon layer below grid structure is reached, because insulating barrier has certain resistance value, insulation Layer can consume a certain amount of bias voltage, and therefore, the magnitude of voltage for reaching top silicon layer is typically smaller than bias voltage；Also, due to exhausted Edge layer also has the function that to stop that Doped ions diffuse to bottom silicon layer in doped region, therefore the thickness of the generally insulating barrier will have There is thicker thickness, to reduce the probability that soft error (soft error) occurs for semiconductor devices；And the thickness of insulating barrier is thicker, The amount of the bias voltage of insulating barrier consumption is bigger, and the bias voltage amount being actually reached on the silicon layer of top is smaller, is more difficult to regulation and partly leads The threshold voltage of body device.

The above analysis is found, if the insulating barrier below doped region keeps thicker thickness, and below grid structure Thickness of insulating layer is relatively thin, then just can solve the problem that the problem of being difficult to adjust threshold voltage of semiconductor device, and ensures insulating barrier Stop the ability of Doped ions diffusion in doped region, reduce the probability that soft error occurs for semiconductor devices.

Therefore, the present invention provides a kind of semiconductor devices and forming method thereof, there is provided have first area, second area and The substrate in the 3rd region, the second area and first area and the 3rd region are adjacent, and the substrate includes the first semiconductor Layer, the insulating barrier positioned at the first semiconductor layer surface and the second semiconductor layer positioned at surface of insulating layer, and first area and The thickness of insulating layer in the 3rd region is more than the second semiconductor layer of the thickness of insulating layer of second area, first area and the 3rd region Thickness is less than the second layer semiconductor thickness of second area；Grid knot is formed in the second semiconductor layer surface of the second area Structure；Doped region is formed in the first area of the grid structure both sides and the 3rd the second semiconductor layer of region.The present invention is dropping The probability of soft error occurs for low semiconductor device meanwhile, it is capable to effectively improve the threshold voltage of semiconductor devices.

It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.

Fig. 2 to Fig. 9 is the cross-sectional view for the semiconductor devices forming process that one embodiment of the invention provides.

It refer to Fig. 2, there is provided there is first area I, second area II and the 3rd region III substrate, the substrate bag Include the 3rd semiconductor layer 200, the dielectric film 201 positioned at the surface of the 3rd semiconductor layer 200 and positioned at the surface of dielectric film 201 4th semiconductor layer 202.

In the present embodiment, the second area II and first area I and the 3rd region III are adjacent, wherein first area I, the thickness of second area II and the 3rd region III dielectric film 201 is identical.3rd semiconductor layer 200 is used to subsequently make For the first semiconductor layer of substrate, insulating barrier of the insulating barrier subsequently formed after the dielectric film 201 is etched as substrate, institute State the 4th semiconductor layer 202 and be used for the follow-up semiconductor layer of part second as substrate.

The material of 3rd semiconductor layer 200 is silicon, germanium, SiGe, carborundum or GaAs；The material of the dielectric film 201 Expect that for silica or silicon oxynitride, thickness be 100 angstroms to 2000 angstroms；The material of 4th semiconductor layer 202 is silicon, germanium, germanium SiClx, carborundum or GaAs.

Please continue to refer to Fig. 2, patterned mask layer is formed in the substrate surface, the patterned mask layer has Expose the opening 205 on the surface of the 4th semiconductor layers of second area II 202.

Mask of the patterned mask layer as subsequent etching dielectric film 201, and the width and the of the opening 205 Two region II width is consistent.The patterned mask layer is single layer structure or laminated construction, in the present embodiment, in order to improve The etching selection ratio of subsequent etching dielectric film 201, the patterned mask layer are laminated construction, specifically, institute is patterned Mask layer includes the first mask layer 203 positioned at the surface of the 4th semiconductor layer 202 and the positioned at the surface of the first mask layer 203 Two mask layers 204.

As a specific embodiment, the material of first mask layer 203 is silica, the thickness of the first mask layer 203 Spend for 50 angstroms to 200 angstroms, the material of the second mask layer 204 is silicon nitride, and the thickness of the second mask layer 204 is 200 angstroms to 1000 Angstrom.

Fig. 3 is refer to, using the patterned mask layer as mask, along 205 (refer to Fig. 2) of opening etching second Region II the 4th semiconductor layer 202 and the dielectric film 201 (refer to Fig. 2) of segment thickness, in the second area II shapes Into groove 206, the dielectric film 201 after etching is insulating barrier 207.

In the present embodiment, the side wall of the groove 206 is located at second area II border.As a specific embodiment, The depth of the groove 206 is 50 angstroms to 1500 angstroms, in other embodiments of the present invention, can determine to etch according to actual process Remove the thickness of dielectric film.The groove 206 is formed using dry etch process；In the present embodiment, the groove 206 is being formed Afterwards, patterned mask layer is retained.

Fig. 4 is refer to, forms the semiconductor film 208 of the full groove of filling, the top surface of semiconductor film 208 is higher than Patterned mask layer top surface；The semiconductor film 208 is planarized, up to the top surface of semiconductor film 208 and graphically Mask layer top surface flush.

In the present embodiment, the semiconductor film 208 is formed using epitaxy technique, and the material of the semiconductor film 208 with The material of 4th semiconductor layer 202 is identical, and epitaxy technique has what the lattice bearing of trend along the 4th semiconductor layer 202 grew Characteristic, therefore, after forming semiconductor film 208 using epitaxy technique, semiconductor film 208 is in close contact with the 4th semiconductor layer 202.

As a specific embodiment, the technological parameter of the epitaxy technique is：The technological parameter of the epitaxy technique is： Reacting gas includes silicon source gas, H₂And HCl, wherein, silicon source gas flow is 1sccm to 1000sccm, and HCl flows are 1sccm to 1000sccm, H₂Flow is 100sccm to 50000sccm, and reaction chamber pressure is 1 support to 50 supports, reaction chamber room temperature Spend for 600 degree to 800 degree, wherein, silicon source gas SiH₄Or SiH₂Cl₂。

Because epitaxy technique has the characteristic grown along the lattice bearing of trend of the 4th semiconductor layer 202, therefore, the half of formation The top surface of electrically conductive film 208 is typically difficult to and plane-parallel, if follow-up directly carry out oxidation processes to the semiconductor film 208 The top surface of remaining semiconductor film 208 is also difficult to and plane-parallel afterwards, is unfavorable for carrying out being subsequently formed grid structure Technique；Therefore, in the present embodiment, the top of semiconductor film 208 is higher than patterned mask layer top, subsequently to semiconductor film After 208 carry out planarization process, you can make the top surface of semiconductor film 208 and plane-parallel, in favor of being subsequently formed top Surface and the 5th semiconductor layer of plane-parallel.

As a specific embodiment, the semiconductor film 208 is planarized using CMP process.The figure The mask layer of change can be as the stop-layer of CMP process, when the top surface of semiconductor film 208 is covered with patterned When film layer top surface flushes, stop planarization process.

Fig. 5 is refer to, oxidation processes are carried out to the semiconductor film 208, the semiconductor film 208 of segment thickness is converted into Oxide-film 209.

The purpose of the oxidation processes is：Removed after the semiconductor film 208 of segment thickness is aoxidized, and it is not oxidized Semiconductor film 208 is not by going the technique of oxide film dissolving 209 to be influenceed so that and remaining semiconductor film 208 is the 5th semiconductor layer, 5th semiconductor layer surface flushes with the top surface of the 4th semiconductor layer 202, and the 5th semiconductor layer is as successive substrates Two region II the second semiconductor layer, in favor of carrying out being subsequently formed the processing step of grid structure.As a specific implementation Example, the oxidation processes are thermal oxidation technology, and the technological parameter of the thermal oxidation technology is：O₂Flow be 20sccm extremely 200sccm, reaction chamber temperature are 350 degree to 550 degree.

The thickness of the oxide-film 209 is identical with the thickness of patterned mask layer, in oxidation processes, the figure The mask layer of shape plays a part of protecting the 4th semiconductor layer 202, prevents the material of the 4th semiconductor layer 202 to be oxidized.And And before oxidation processes, the top surface of semiconductor film 208 flushes with the top surface of the 4th semiconductor layer 202, therefore oxygen After change processing, the thickness of oxide-film 209 has uniformity so that the remaining top surface of semiconductor film 208 and plane-parallel.

Fig. 6 is refer to, removes the oxide-film 209 (refer to Fig. 5), remaining semiconductor film 208 (refer to Fig. 5) is 5th semiconductor layer 210, the top surface of the 5th semiconductor layer 210 flush with the top surface of the 4th semiconductor layer 202.

As one embodiment, the oxide-film 209, the quarter of the wet-etching technology are removed using wet-etching technology Erosion liquid is hydrofluoric acid solution, and the volume ratio of hydrofluoric acid and water is 1:100 to 1:700.

210 common groups of 3rd semiconductor layer 201, insulating barrier 207, the 4th semiconductor layer 202 and the 5th semiconductor layer Into the substrate with first area I, second area II and the 3rd region III, second area II and first area I and the 3rd region III is adjacent, and the substrate includes the first semiconductor layer, the insulating barrier 207 positioned at the first semiconductor layer surface and positioned at exhausted Second semiconductor layer on the surface of edge layer 207, wherein, the 3rd semiconductor layer 201 is used as the first semiconductor layer, the 5th semiconductor layer 210 and the 4th semiconductor layer 202 be used as the second semiconductor layer, wherein, the 4th semiconductor layer 202 is first area I and the 3rd area Domain III the second semiconductor layer, the 5th semiconductor layer 210 are second area II the second semiconductor layer, and first area I and the The three region III thickness of insulating barrier 207 be more than second area II the thickness of insulating barrier 207, first area I, second area II and The 3rd region III lower surface of insulating barrier 207 flushes, first area I and the 3rd region III the second semiconductor layer the (the 4th Semiconductor layer 202) the second semiconductor layer (the 5th semiconductor layer 210) thickness of thickness less than second area II, first area I, Second area II and the 3rd region III the second semiconductor layer surface flushes.

Fig. 7 is refer to, the second semiconductor layer (the 5th semiconductor layer 210) surface between the patterned mask layer Form gate oxidation films 211；Gate-conductive film 212 is formed on the surface of gate oxidation films 211 and patterned mask layer surface.

The material of the gate oxidation films 211 is silica or high K medium material, and the material of the gate-conductive film 212 is more Crystal silicon, the polysilicon or conducting metal of doping.In the present embodiment, during gate oxidation films 211 are formed, due to patterned The presence of mask layer, the gate oxidation films 211 of formation are placed exactly in the surface of the 5th semiconductor layer 210 so that the grid being subsequently formed Structure is also placed exactly in the surface of the 5th semiconductor layer 210, and therefore, the patterned mask layer has the function that to play alignment, Make the gate oxidation films 211 to be formed can be as the gate oxide of subsequent gate structure.

Fig. 8 is refer to, the graphical gate-conductive film 212 (refer to Fig. 7) forms grid structure, the grid structure position In second area II the second semiconductor layer (the 5th semiconductor layer 210) surface, the grid structure include gate oxide 221 with And the grid conductive layer 222 positioned at the surface of gate oxide 221.

Specifically, patterned photoresist layer is formed on the surface of gate-conductive film 212, with the patterned photoresist Layer is mask, etches the gate-conductive film 212.In the present embodiment, while gate-conductive film 212 are etched, also etching is gone Except patterned mask layer, the surface of the 4th semiconductor layer 202 is exposed.

As one embodiment, the width of the grid structure of the formation just width with gate oxidation films 211 (refer to Fig. 7) Unanimously；As another embodiment, the width of the grid structure of formation is more than the width of gate oxidation films 211, that is to say, that part is wide The patterned mask layer of degree is located in grid structure；As another embodiment, the width of the grid structure of formation is less than grid oxygen Change the width of film 211, that is to say, that the gate oxidation films 211 of partial width are carried out while the graphical gate-conductive film Etching.

It should be noted that in other embodiments of the present invention, removed after the 5th semiconductor layer is formed patterned Mask layer, then the forming step of grid structure include：In the 4th semiconductor layer and the 5th semiconductor layer surface successively shape Into gate oxidation films and gate-conductive film；The graphical gate oxidation films and gate-conductive film form grid structure, the grid knot Structure is located at the semiconductor layer surface of second area the 5th.

Fig. 9 is refer to, lightly doped district (not shown) is formed in the second semiconductor layer of the grid structure both sides；Institute State the side wall 213 that the surface of the 4th semiconductor layer 202 forms adjacent grid structure both sides；It is mask with the side wall 213, described Heavily doped region 214 is formed in second semiconductor layer of grid structure both sides.

The material of the side wall 213 is silicon nitride, silica or silicon oxynitride.Semiconductor devices of the present embodiment to be formed It is exemplary illustrated to be done exemplified by nmos pass transistor.The Doped ions of lightly doped district are N-type ion, the N-type ion be P, As or Sb；The lightly doped district can alleviate hot carrier's effect.

In the present embodiment, the heavily doped region 214 is formed using ion implantation technology, as one embodiment, ion note The technological parameter for entering technique is：Injection ion is P, and Implantation Energy is 1kev to 50kev, implantation dosage 5E18atom/cm³Extremely 5E21atom/cm³.It after the completion of ion implantation technology, can also be made annealing treatment, activate the injection in heavily doped region 214 Ion, repair ion implantation technology and damaged to caused by the second semiconductor layer.

In the present embodiment, the insulating barrier 207 of the lower section of heavily doped region 214 is located in first area I and the 3rd region III, grid Insulating barrier 207 below the structure of pole is located in second area II, and the thickness of insulating barrier 207 in second area II is less than the firstth area Domain I and the 3rd region III thickness of insulating barrier 207；Therefore, the insulating barrier 207 of the lower section of heavily doped region 214 has thicker thickness Degree, it can effectively stop ion scattering and permeating in heavily doped region 214 to the first semiconductor layer (the 3rd semiconductor layer 200) It is interior, so as to reduce the soft error of semiconductor devices, improve the reliability of the semiconductor devices of formation.

Also, generally in the practical application of semiconductor devices, it is desirable to by the way that to the first semiconductor layer, (that is, the 3rd half leads Body layer 200) it is biased, change the current potential of the second semiconductor layer (that is, the 5th semiconductor layer 210) below grid structure to adjust The threshold voltage of whole semiconductor devices, semiconductor devices is set to meet application demand, the insulation in the present embodiment below grid structure Layer 207 has relatively thin thickness, and the effective resistance of the insulating barrier 207 below grid structure is smaller, when by the 3rd semiconductor When layer 200 applies bias voltage to adjust the current potential amount of the 5th semiconductor layer 210, the bias voltage is after insulating barrier 207 It is applied on the 5th semiconductor layer 210, because the second area II effective resistance of insulating barrier 207 is smaller, therefore can keeps real The gap that border is added between the magnitude of voltage and bias voltage on the 5th semiconductor layer 210 is smaller, so as to which effectively adjustment the 5th half is led The current potential amount of body layer 210, change the threshold voltage of semiconductor devices, the electric property of semiconductor devices is in optimum state.

Accordingly, the present embodiment provides a kind of semiconductor devices, refer to Fig. 9, the semiconductor devices includes：

Substrate, the substrate include the first semiconductor layer (the 3rd semiconductor layer 200), positioned at the first semiconductor layer surface Insulating barrier 207 and the second semiconductor layer positioned at the surface of insulating barrier 207, the substrate have first area I, second area II and the 3rd region III, the second area II and first area I and the 3rd region III are adjacent, wherein, first area I and The 3rd region III thickness of insulating barrier 207 is more than the second area II thickness of insulating barrier 207, first area I, second area II Flushed with the 3rd region III lower surface of insulating barrier 207, and the of first area I, second area II and the 3rd region III Two semiconductor layer surfaces flush；Positioned at the grid structure of second area II the second semiconductor layer surface；Positioned at grid knot The first area I of structure both sides and the 3rd the second semiconductor layers of region II doped region.

Specifically, the material of first semiconductor layer (that is, the 3rd semiconductor layer 200) is silicon, germanium, SiGe or arsenic Gallium.The material of the insulating barrier 207 is silica.First area I, second area II and the 3rd region the III bottom of insulating barrier 207 Portion surface flushes, and the thickness of second area II insulating barrier 207 is less than first area I and the 3rd region III insulating barrier 207 Thickness, the top of insulating barrier 207 of the first area I and the 3rd region III is high to the second area II top of insulating barrier 207 Spend for 50 angstroms to 1500 angstroms, the height at the top to top refers to the height on horizontal plane direction, that is to say, that Big 50 angstroms of the thickness of the thickness ratio second area II of first area I and the 3rd region III insulating barrier 207 insulating barrier 207 is extremely 1500 angstroms.

In the present embodiment, the second semiconductor layer of the first area I and the 3rd region III are by the 4th semiconductor layer 202 Form, the second semiconductor layer of the second area II is made up of the 5th semiconductor layer 210, and the 4th semiconductor layer 202 pushes up Portion surface flushes with the top surface of the 5th semiconductor layer 210, and the thickness of the 4th semiconductor layer 202 is less than the 5th semiconductor layer 210 thickness.

The grid structure includes being located at the gate oxide 221 of the semiconductor layer surfaces of second area II second and is located at The grid conductive layer 222 on the surface of gate oxide 211, the material of the gate oxide 221 are silica or high K medium material, described The material of grid conductive layer 222 is polysilicon or conducting metal.The gate structure sidewall is located at second area II borders, the secondth area In the II of domain or in first area I and the 3rd region III, the distance of the gate structure sidewall to second area II borders is 0 angstrom To 100 angstroms.This implementation is done exemplary illustrated so that the grid structure is located at second area II borders as an example.

Also include：Positioned at the side wall 213 of gate structure sidewall, the material of the side wall 213 is silica, silicon nitride or nitrogen Silica.The doped region includes：Lightly doped district in the semiconductor layer of grid structure both sides second and positioned at grid knot Heavily doped region 214 in the semiconductor layer of structure both sides second.

Small 50 angstroms of the thickness of insulating barrier 207 of the lower section of thickness ratio heavily doped region 214 of insulating barrier 207 below grid structure is extremely 1500 angstroms, the effective resistance of the insulating barrier 207 below grid structure is smaller, when to the first semiconductor layer (that is, the 3rd semiconductor layer 200) when applying bias voltage, the bias voltage that grid structure underlying insulating layer 207 consumes is smaller, is actually reached under grid structure Bias voltage amount on the second semiconductor layer (that is, the 5th semiconductor layer 210) of side is larger, so as to effectively improve semiconductor device The threshold voltage of part, the threshold voltage of semiconductor devices is set to meet actual process demand；Also, due to the lower section of heavily doped region 214 The thickness of insulating barrier 207 it is thicker, therefore, the insulating barrier 207 of the lower section of heavily doped region 214 can effectively stop that ion diffuses to the In semi-conductor layer, reduce semiconductor devices and soft error probability occurs.

Another embodiment of the present invention also provides a kind of forming method of semiconductor devices, unlike previous embodiment, After the formation of the recess, patterned mask layer is removed, exposes the 4th semiconductor layer surface.

Figure 10 to Figure 14 is the cross-sectional view for the semiconductor devices forming process that another embodiment of the present invention provides, It should be noted that in the present embodiment with the restriction such as mutually isostructural parameter in previous embodiment and effect in the present embodiment not Repeat again, specifically refer to above-described embodiment.

It refer to Figure 10, there is provided there is first area I, second area II and the 3rd region III substrate, the substrate bag Include the 3rd semiconductor layer 200, the dielectric film positioned at the surface of the 3rd semiconductor layer 200 and the positioned at insulating film surface the 4th half Conductor layer 202；Patterned mask layer is formed in the substrate surface；Using the patterned mask layer as mask, etching the Two region II the 4th semiconductor layer 202 and the dielectric film of segment thickness, groove 206 is formed in the second area II, is carved Dielectric film after erosion is insulating barrier 207；The patterned mask layer is removed, exposes the surface of the 4th semiconductor layer 202.

The mask layer is removed using wet-etching technology, as a specific embodiment, the wet-etching technology Etch liquids are hot phosphoric acid solution, wherein, phosphoric acid quality percentage is 65% to 85%, and solution temperature is 80 degree to 200 degree.

Figure 11 is refer to, forms the semiconductor film 208 of the full groove 206 (refer to Figure 10) of filling, the semiconductor Film 208 is also covered in the surface of the 4th semiconductor layer 202 exposed.

It should be noted that after due to subsequently being planarized to semiconductor film 208, first area I, second area II Need to flush with the top surface of the 3rd region III semiconductor film 208, therefore, in the present embodiment, the epitaxy technique stops Stop bit is set to：At least second area II top surface of semiconductor film 208 flushes with the top surface of the 4th semiconductor layer 202； Or the second area II top surface of semiconductor film 208 is higher than the top surface of the 4th semiconductor layer 202.

The present embodiment is higher than the top surface of the 4th semiconductor layer 202 with the second area II top surface of semiconductor film 208 Exemplified by do it is exemplary illustrated.The material of the semiconductor film 208 is silicon, germanium, SiGe or GaAs, is formed using epitaxy technique The semiconductor film 208.

Figure 12 is refer to, the semiconductor film 208 (refer to Figure 11) is planarized and forms the 5th semiconductor layer 210.

In the present embodiment, the 5th semiconductor layer 210 is also located at first area I and in addition to positioned at second area II The three region III surface of the 4th semiconductor layer 202.In other embodiments, the 5th semiconductor layer is only located at second area, and Five semiconductor layer surfaces flush with the 4th semiconductor layer surface.

3rd semiconductor layer 200, insulating barrier 207, the 4th semiconductor layer 202 and the 5th semiconductor layer 210 have by being formed There are first area I, second area II and the 3rd region III a substrate, the 4th semiconductor layer 202 and positioned at the 4th semiconductor layer 5th semiconductor layer 210 on 202 surfaces is as substrate first area I and the 3rd region III the second semiconductor layer, second area 5th semiconductor layer 210 is substrate second area II the second semiconductor layer；3rd semiconductor layer 200 as substrate the first half Conductor layer；Insulating barrier of the insulating barrier 207 as substrate.

In the present embodiment, the depth of groove 206 is 50 angstroms to 1500 angstroms, therefore, first area I and the 3rd region III's The thickness of the thickness ratio second area II of insulating barrier 207 insulating barrier 207 is big 50 angstroms to 1500 angstroms, first area I and the 3rd area The thickness of second semiconductor layer of domain III the second semiconductor layer than second area II is small 50 angstroms to 1500 angstroms.

Figure 13 is refer to, grid structure is formed on the surface of the 5th semiconductor layer 210 of the second area II.

The grid structure includes：Positioned at the surface of the 5th semiconductor layers of second area II 210 gate oxide 221 and Grid conductive layer 222 positioned at the surface of gate oxide 221.As one embodiment, forming the processing step of grid structure includes： The surface of 5th semiconductor layer 210 sequentially forms gate oxidation films and the gate-conductive film positioned at gate oxidation films surface；Graphically The gate oxidation films and gate-conductive film, grid structure is formed on the surface of the 5th semiconductor layers of the second area II 210.

Location expression on the grid structure refers to previous embodiment, will not be repeated here.

Figure 14 is refer to, in the first area I and the 3rd region III of the grid structure both sides the 5th semiconductor layer Lightly doped district (not shown) is formed in 210；The side wall of adjacent gate structure sidewall is formed on the surface of the 5th semiconductor layer 210 213；Heavily doped region 214 is formed in the 5th semiconductor layer 210 of the grid structure both sides.

The formation process of the lightly doped district, side wall 213 and heavily doped region 214 refers to the light of embodiment offer and mixed The formation process in miscellaneous area, side wall and heavily doped region, will not be repeated here.

The thickness of insulating barrier 207 of the lower section of heavily doped region 214 is more than the thickness of insulating barrier 207 below grid structure.By It is thicker in first area I and the 3rd region the III thickness of insulating barrier 207, therefore can effectively stop mixing in heavily doped region 214 Heteroion spreads to the first semiconductor layer (the 3rd semiconductor layer 200), reduces the error rate of semiconductor devices；And second area II The thinner thickness of insulating barrier 207, therefore the effective resistance of second area II insulating barrier 207 is relatively small, by the 3rd half Conductor layer 200 applies bias voltage to change the electricity of the second semiconductor layer (that is, the 5th semiconductor layer 210) below grid structure During position, the bias voltage amount that second area II insulating barrier 207 consumes is less so that final actually applied in the 5th semiconductor layer Bias voltage on 210 is larger, therefore can effectively change the magnitude of voltage of grid structure underlying channel region, is partly led so as to adjust The threshold voltage of body device, improve the electric property of semiconductor devices.

Accordingly, the present embodiment provides a kind of semiconductor devices, and as shown in figure 14, the semiconductor devices includes：

Substrate, the substrate include the first semiconductor layer, insulating barrier 307, Yi Jiwei positioned at the first semiconductor layer surface The second semiconductor layer in the surface of insulating barrier 307, the substrate have first area I, second area II and the 3rd region III, The second area II and first area I and the 3rd region III are adjacent, wherein, first area I and the 3rd region III's is exhausted Insulating barrier 307 thickness of the thickness of edge layer 307 more than second area II, first area I, second area II and the 3rd region III's The lower surface of insulating barrier 307 flushes, first area I, second area II and the 3rd region III the second semiconductor layer surface Flush；Positioned at the grid structure of second area II the second semiconductor layer surface；Positioned at grid structure both sides first area I and The doped region of 3rd the second semiconductor layers of region III.

Specifically, in the present embodiment, the 3rd semiconductor layer 200 is the first semiconductor layer, first semiconductor layer Material be silicon, germanium, SiGe or GaAs.The material of the insulating barrier 307 is silica；The first area I and the 3rd The region III top of insulating barrier 307 to the second area II overhead height of insulating barrier 307 is 50 angstroms to 1500 angstroms, that is to say, that Small 50 angstroms of the thickness of the thickness ratio second area II of first area I and the 3rd region III insulating barrier 307 insulating barrier 307 is extremely 1500 angstroms.

The second semiconductor layer of the first area I and the 3rd region III are by the 4th semiconductor layer 202 and positioned at the 4th half 5th semiconductor layer 210 on the surface of conductor layer 202 is formed, and second area II the second semiconductor layer is by the 5th semiconductor layer 210 Form, and first area I, second area II and the 3rd region the III top surface of the 5th semiconductor layer 210 flush.

The grid structure includes gate oxide 221 and grid conductive layer 222；The gate structure sidewall is located at second area In II borders, second area II or in first area I and the 3rd region III, the gate structure sidewall to second area II sides The distance on boundary is 0 angstrom to 100 angstroms.The present embodiment does exemplary theory by the gate structure sidewall exemplified by second area II borders It is bright.

Also include：Positioned at the side wall 213 of gate structure sidewall.The doped region includes：Positioned at grid structure both sides Lightly doped district in two semiconductor layers (the 4th semiconductor layer 202 and the 5th semiconductor layer 210)；Positioned at grid structure both sides Heavily doped region 214 in two semiconductor layers.

In the present embodiment, the insulating barrier 307 of the lower section of thickness ratio heavily doped region 214 of the insulating barrier 307 below grid structure Thickness of thin, therefore the effective resistance of insulating barrier 307 below grid structure is smaller, when to the first semiconductor layer, (the i.e. the 3rd half leads Body layer 200) when applying bias voltage, the biasing that is actually reached on grid structure underlying channel region (i.e. the 5th semiconductor layer 210) Voltage is larger, so as to effectively improve the threshold voltage of semiconductor devices.

Further embodiment of this invention also provides a kind of forming method of semiconductor devices, and Figure 15 to Figure 19 is another for the present invention The cross-sectional view for the semiconductor devices forming process that embodiment provides.

It refer to Figure 15, there is provided there is first area I ', second area II ' and the 3rd region III ' initial substrate, institute Stating initial substrate includes the 3rd semiconductor layer 300 and the dielectric film 301 positioned at the surface of the 3rd semiconductor layer 300.

The material of 3rd semiconductor layer 300 is silicon, germanium, SiGe or GaAs；The material of the dielectric film 301 is Silica.Subsequently the first semiconductor layer as substrate, subsequent etching remove second area II ' to 3rd semiconductor layer 300 After the dielectric film 301 of segment thickness, insulating barrier of the remaining dielectric film 301 as substrate.It is described first as one embodiment The forming step at primordium bottom includes：3rd semiconductor layer 300 is provided；In the surface depositing insulating films of the 3rd semiconductor layer 300 301, the semiconductor layer 300 of dielectric film 301 and the 3rd collectively constitutes dielectric base.

Figure 16 is refer to, patterned mask layer (not shown) is formed in the dielectric film 301 (refer to Figure 15), The patterned mask layer has the opening for exposing the surface of second area II ' dielectric films 301；With the patterned mask Layer is mask, and etching removes the dielectric film 301 (refer to Figure 15) of second area II ' segment thicknesses, and remaining dielectric film 301 is Insulating barrier 307, second area II ' insulating barrier 307 is interior to have groove 306.

As one embodiment, the depth of the groove 306 is 50 angstroms to 1500 angstroms.After the groove 306 is formed, Cleaning treatment can also be carried out to the bottom of groove 306 and side wall, the interfacial state of groove 306 be improved, in favor of being subsequently bonded Technique.

It refer to Figure 17, there is provided the 4th semiconductor layer；Patterned mask layer is formed in the 4th semiconductor layer surface (not shown)；Using the patterned mask layer as mask, etching removes the 4th semiconductor layer of segment thickness, forms tool There is the 5th semiconductor layer 310 of projection 309.

The material of 4th semiconductor layer is silicon, germanium, SiGe or GaAs；Described raised 309 thickness and groove 306 deep equality, and raised 309 topside area is equal with the bottom area of the groove 306.

Figure 18 is refer to, the 5th semiconductor layer 310 is bonded with the initial substrate with groove 306.

After the completion of bonding technology, the projection 309 of the 5th semiconductor layer 310 is placed exactly in groove 306, and the projection 309 top surfaces are in contact with the lower surface of groove 306, and raised 309 sidewall surfaces are in contact with the sidewall surfaces of groove 306, and The surface of 5th semiconductor layer 310 is in contact with the surface of insulating barrier 307.

After bonding, the 3rd semiconductor layer 300, the semiconductor layer 310 of insulating barrier 307 and the 5th composition have first area I ', second area II ' and the 3rd region III ' substrate, first semiconductor layer of the 3rd semiconductor layer 300 as substrate, the 5th Second semiconductor layer of the semiconductor layer 310 as substrate, and first area I ' and the 3rd region III ' thickness of insulating barrier 307 is big In the thickness of second area II ' insulating barriers 307, first area I ' and the 3rd region III ' the second layer semiconductor thickness is less than the Two region II ' the second layer semiconductor thickness.

Figure 19 is refer to, grid structure, the grid structure bag are formed in second area II ' the second semiconductor layer surface Include gate oxide 321 and grid conductive layer 322；Lightly doped district is formed in the second semiconductor layer of grid structure both sides；Institute State the side wall 313 that the second semiconductor layer surface forms adjacent gate structure sidewall；The second half in the grid structure both sides lead Heavily doped region 314 is formed in body layer.

Due to the thinner thickness of insulating barrier 307 below grid structure, the effective resistance of the insulating barrier 307 of the position compared with It is small, therefore when applying bias voltage on the first semiconductor layer (i.e. the 3rd semiconductor layer 300), be actually reached below grid structure (i.e. the voltage of the 5th semiconductor layer 310 is higher, so as to effectively adjust the threshold voltage of semiconductor devices, changes for channel region The electric property of kind semiconductor devices.

Accordingly, the present embodiment also provides a kind of semiconductor devices, refer to Figure 19, and the semiconductor devices includes：

Substrate with first area I ', second area II ' and the 3rd region III ', the second area II ' and first Region I ' and the 3rd region III ' are adjacent, and the substrate includes the first semiconductor layer, positioned at the exhausted of the first semiconductor layer surface Edge layer 307 and the second semiconductor layer positioned at the surface of insulating barrier 307, and first area I and the 3rd region III ' insulating barrier Insulating barrier 307 thickness of 307 thickness more than second area II ', first area II ', second area II ' and the 3rd region III's ' The lower surface of insulating barrier 307 flushes, first area I ', second area II ' and the 3rd region III ' the second semiconductor layer Surface flushes；Positioned at the grid structure of second area II ' the second semiconductor layer surface；Positioned at the firstth area of grid structure both sides Domain I ' and the 3rd the second semiconductor layers of region III ' doped region.

Specifically, in the present embodiment the 3rd semiconductor layer 300 be substrate the first semiconductor layer, first semiconductor layer Material be silicon, germanium, SiGe or GaAs.The material of the insulating barrier 307 is silica, first area I ' and the 3rd region III ' the top of insulating barrier 307 to the second area II ' overhead height of insulating barrier 307 is 50 angstroms to 1500 angstroms.

The first area I ', second area II ' and the 3rd region III ' the second semiconductor layer are by the 5th semiconductor layer 310 are formed, and first area I ', second area II ' and the 3rd region III ' top of the 5th semiconductor layer 310 flush, also It is to say, first area I ' and the 3rd region III ' bottom of the 5th semiconductor layer 310 are higher than second area II ' the 5th semiconductor 310 bottom of layer, first area I ' and the 3rd region III ' bottom of the 5th semiconductor layer 310 to the 5th half of second area II ' The bottom level of conductor layer 310 is 50 angstroms to 1500 angstroms.

The grid structure includes gate oxide 321 and grid conductive layer 322, and the gate structure sidewall is located at the secondth area In domain II ' borders, second area II ' or in first area I ' and the 3rd region III ', the gate structure sidewall to the secondth area The distance on domain II ' borders is 0 angstrom to 100 angstroms；The present embodiment is so that the gate structure sidewall is located at second area II ' borders as an example Do exemplary illustrated.

Also include：Positioned at the second semiconductor layer surface and the side wall 313 of adjacent gate structure sidewall, the side wall 313 Material is silica, silicon nitride or silicon oxynitride.The doped region includes：In the semiconductor layer of grid structure both sides second Lightly doped district；Heavily doped region 314 in the semiconductor layer of grid structure both sides second.

In the present embodiment, the insulating barrier 307 below grid structure is thinner than the insulating barrier 307 of the lower section of heavily doped region 314, therefore The effective resistance of insulating barrier 307 below grid structure is smaller, is applied when to the first semiconductor layer (that is, the 3rd semiconductor layer 300) When adding bias voltage, the amount that the bias voltage consumes via insulating barrier 307 is less, is actually reached grid structure underlying channel region The bias voltage amount of (i.e. the 5th semiconductor layer 310) is larger, therefore can effectively improve the threshold voltage of semiconductor devices；And And the thickness of insulating barrier 307 of the lower section of heavily doped region 314 is thicker, can effectively stop that the ion in heavily doped region 314 diffuses into Enter in the first semiconductor layer, reduce the probability that soft error occurs for semiconductor devices, optimize the electric property of semiconductor devices.

Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute The scope of restriction is defined.

Claims

A kind of 1. forming method of semiconductor devices, it is characterised in that including：

Substrate is provided, the substrate includes the first semiconductor layer, the insulating barrier positioned at the first semiconductor layer surface and positioned at exhausted Second semiconductor layer on edge layer surface, the substrate have first area, second area and the 3rd region, the second area with First area and the 3rd region are adjacent, wherein, the thickness of insulating layer in first area and the 3rd region is more than the exhausted of second area Edge layer thickness, the insulating barrier lower surface of first area, second area and the 3rd region flush, and first area, second area Flushed with the second semiconductor layer surface in the 3rd region；

Grid structure is formed in the second semiconductor layer surface of the second area；

Doped region is formed in the first area of the grid structure both sides and the 3rd the second semiconductor layer of region；

Wherein, the forming step of the substrate includes：Substrate with first area, second area and the 3rd region, institute are provided Stating substrate includes the 3rd semiconductor layer, the dielectric film positioned at the 3rd semiconductor layer surface and the positioned at insulating film surface the 4th Semiconductor layer；Patterned mask layer is formed in the substrate surface；Using the patterned mask layer as mask, etching removes 4th semiconductor layer of second area and the dielectric film of segment thickness, groove, remaining insulation are formed in the second area Insulating barrier of the film as substrate；Form the 5th semiconductor layer of the full groove of filling, the 3rd semiconductor layer, insulating barrier and the Five semiconductor layers collectively constitute substrate.
2. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that first semiconductor layer and the second half The material of conductor layer is silicon, germanium, SiGe or GaAs；The material of the insulating barrier is silica.
3. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the first area and the 3rd region Thickness of insulating layer is bigger than the thickness of insulating layer of second area 50 angstroms to 1500 angstroms.
4. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that after the groove is formed, retain Patterned mask layer.
5. the forming method of semiconductor devices as claimed in claim 4, it is characterised in that the formation step of the 5th semiconductor layer Suddenly include：The semiconductor film of the full groove of filling is formed, the semiconductor film top surface is higher than patterned mask layer top Portion surface；The semiconductor film is planarized, until semiconductor film top surface flushes with patterned mask layer top surface；Go Except the semiconductor film of segment thickness, remaining semiconductor film is the 5th semiconductor layer, and the 5th semiconductor layer surface Flushed with the 4th semiconductor layer surface, wherein, the 4th semiconductor layer is led as the second the half of first area and the 3rd region Body layer, second semiconductor layer of the 5th semiconductor layer as second area.
6. the forming method of semiconductor devices as claimed in claim 5, it is characterised in that remove the semiconductor film of segment thickness Method is：Oxidation processes are carried out to the semiconductor film, the semiconductor film of segment thickness is converted into oxide-film；Remove the oxygen Change film.
7. the forming method of semiconductor devices as claimed in claim 6, it is characterised in that the oxygen is carried out using thermal oxidation technology Change is handled, and the technological parameter of thermal oxidation technology is：O₂Flow is 20sccm to 200sccm, reaction chamber temperature be 300 degree extremely 550 degree.
8. the forming method of semiconductor devices as claimed in claim 5, it is characterised in that the step of forming grid structure includes： The 5th semiconductor layer surface between the patterned mask layer forms gate oxide；In the gate oxide and graphically Mask layer surface formed gate-conductive film；The graphical gate-conductive film forms grid structure, and the grid structure is located at second Second semiconductor layer surface in region.
9. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that after the groove is formed, remove The patterned mask layer, exposes the 4th semiconductor layer surface.
10. the forming method of semiconductor devices as claimed in claim 9, it is characterised in that the formation of the 5th semiconductor layer Step includes：The semiconductor film of the full groove of filling is formed, the semiconductor film is also covered in the 4th semiconductor layer table Face；Planarize semiconductor film and form the 5th semiconductor layer；4th semiconductor layer and the 5th semiconductor layer are collectively as first area With second semiconductor layer in the 3rd region, the second semiconductor layer of the 5th semiconductor layer of second area as second area.
11. the forming method of semiconductor devices as described in claim 5 or 10, it is characterised in that institute is formed using epitaxy technique Semiconductor film is stated, the technological parameter of epitaxy technique is：Reacting gas includes silicon source gas, H₂And HCl, wherein, flow of Si It is 1sccm to 1000sccm, H to measure as 1sccm to 1000sccm, HCl flows₂Flow is 100sccm to 50000sccm, reaction Chamber pressure is 1 support to 50 supports, and reaction chamber temperature is 600 degree to 800 degree.
12. the forming method of semiconductor devices as claimed in claim 1, it is characterised in that the gate structure sidewall is positioned at the In two zone boundaries, second area or in first area and the 3rd region, the gate structure sidewall to second area border Distance is 0 angstrom to 100 angstroms.
A kind of 13. semiconductor devices, it is characterised in that including：

Substrate, the substrate include the first semiconductor layer, the insulating barrier positioned at the first semiconductor layer surface and positioned at insulating barriers Second semiconductor layer on surface, the substrate have first area, second area and the 3rd region, the second area and first Region and the 3rd region are adjacent, wherein, the thickness of insulating layer in first area and the 3rd region is more than the insulating barrier of second area Thickness, the insulating barrier lower surface of first area, second area and the 3rd region flush, and first area, second area and The second semiconductor layer surface in three regions flushes；

Positioned at the grid structure of the second semiconductor layer surface of second area；

Positioned at the first area of grid structure both sides and the doped region of the 3rd the second semiconductor layer of region；

Wherein, the forming step of the substrate includes：Substrate with first area, second area and the 3rd region, institute are provided Stating substrate includes the 3rd semiconductor layer, the dielectric film positioned at the 3rd semiconductor layer surface and the positioned at insulating film surface the 4th Semiconductor layer；Patterned mask layer is formed in the substrate surface；Using the patterned mask layer as mask, etching removes 4th semiconductor layer of second area and the dielectric film of segment thickness, groove, remaining insulation are formed in the second area Insulating barrier of the film as substrate；Form the 5th semiconductor layer of the full groove of filling, the 3rd semiconductor layer, insulating barrier and the Five semiconductor layers collectively constitute substrate.
14. semiconductor devices as claimed in claim 13, it is characterised in that the insulating barrier top in the first area and the 3rd region Portion to the insulating barrier overhead height of second area is 50 angstroms to 1500 angstroms.
15. semiconductor devices as claimed in claim 13, it is characterised in that the second the half of the first area and the 3rd region lead Body layer is made up of the 4th semiconductor layer, and the second semiconductor layer of the second area is made up of the 5th semiconductor layer, and the described 4th Semiconductor layer surface flushes with the 5th semiconductor layer surface.
16. semiconductor devices as claimed in claim 13, it is characterised in that the second the half of the first area and the 3rd region lead Body layer is made up of the 4th semiconductor layer and the 5th semiconductor layer positioned at the 4th semiconductor layer surface, and the second the half of second area leads Body layer is made up of the 5th semiconductor layer, and the 5th semiconductor layer surface of first area, second area and the 3rd region is neat It is flat.
17. semiconductor devices as claimed in claim 13, it is characterised in that the first area, second area and the 3rd region The second semiconductor layer be made up of the 5th semiconductor layer, and the 5th semiconductor layer of first area, second area and the 3rd region Top flushes.
18. semiconductor devices as claimed in claim 13, it is characterised in that the gate structure sidewall is located at second area side In boundary, second area or in first area and the 3rd region, the distance of the gate structure sidewall to second area border is 0 angstrom To 100 angstroms.