CN105095532A - Operation method for half-node CMP model in master-node layout - Google Patents
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Abstract
The invention relates to an operation method for a half-node CMP model in a master-node layout and a fabrication method of a semiconductor device.The operation method comprises following steps: step (a): providing the master-node layout; step (b): dividing the master-node layout into multiple net regions and geometrically extracting each net region in order to acquire numerical information; step (c): reducing geometrical information of numerical information in order to acquire the half-node geometrical information and carrying out half-node CMP simulation based on half-node geometrical information; step (d): outputting data of simulated results and determining defect points in a simulation process; step (e): analyzing the above defect points in the master-node layout; step (f): generating the layout, modifying guidelines and performing modification.The operation method for the half-node CMP model in the master-node layout has following beneficial effects: by adjusting the grid size in a VCMP method, two processing steps consuming a lot of time are avoided by adjusting analogue resolution of VCMP and reduction factors of processes in order to increase simulation efficiency.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to operation method and the semiconductor devices preparation method of half node CMP model in a kind of host node domain.
Background technology
Ic manufacturing technology is a complicated technique, and technology innovation is very fast, and the key parameter characterizing ic manufacturing technology is minimum feature size, i.e. critical size (criticaldimension, CD).Along with the development of semiconductor technology, the critical size of device is more and more less, and the reduction just because of critical size just makes each chip to be arranged 1,000,000 devices becomes possibility.
Along with constantly reducing of semiconductor technology device size, when described dimensions of semiconductor devices is contracted to nanometer nodes, manufacturability design (DesignforManufacturing, DFM) has become more and more important in semi-conductor industry nano-engineer flow and method.Described DFM refers to by the production efficiency of fast lifting chip yield and reduces for the purpose of production cost, rule in Unify legislation chip design, tool and method, thus control integration circuit copying to physics wafer better, being the design of process variability in a kind of measurable manufacture process, making the whole process from being designed into wafer manufacture reach optimization.
Current crystal grain (Die) size reduce or technological process reduces to refer to reducing of a simple dimensions of semiconductor devices in semiconductor device, mainly refer to transistor.Reducing of crystal grain can ensure integrated more crystal grain in a wafer, and keeps identical circuit design, thus reduces the cost of product.
Reducing of usual crystal grain advances International Technology Roadmap for Semiconductors (InternationalTechnologyRoadmapforSemiconductors, the lithography node of definition ITRS), but the lithography node of crystal grain is not defined by ITRS sometimes, be called as half node (Half-Node), wherein, described half node is a kind of alternative techniques (stopgap) in ITRS between two process nodes, to help the cost reducing device.
In addition, along with constantly reducing of dimensions of semiconductor devices, contact between IC deviser and manufacturer is more tight, and the design of device or manufacturability design (DesignforManufacturing, DFM) can strengthen the contact between deviser and manufacturer.By DFM, the data of Integrated manufacture can make the cooperation between designer and manufacturer, thus improve production output and shop characteristic, decrease design cycle and design cost simultaneously.
Fig. 1 is the process chart that in prior art prepared by domain, wherein in described DFM flow process, relate to virtual chemically mechanical polishing (VirtualChemicalMechanicalPolishing, VCMP), process chart prepared by the host node domain wherein comprising CMP as shown in Figure 2 a.Usual half node domain is that the domain following host node design rule that manufacturer provides carries out a certain proportion of reducing and obtains, the checking of DFMVCMP is comprised at half node domain, wherein typical flow process as shown in Figure 2 b, described half node domain need obtain before carrying out VCMP simulation, this step is usually by domain instrument integrated on simulation tool or reduced according to a certain percentage by the domain instrument that third party provides and realize, the shortcoming of described method is that the step that described domain reduces must be carried out before simulation, and described simulation tool does not have integrated domain instrument sometimes, described reduction process needs by manually selecting third party's instrument to carry out, this step needs the time of at substantial, especially in batch process.
Further, because simulation process is directly applied on the host node domain i.e. half node domain that reduces, so the identifying information exported and geological information also reduce, thus in the analysis carrying out defect point, need to perform on the domain reduced, but normal domain amendment is carried out, after therefore obtaining domain alteration ruler in original layout, need first alteration ruler to be converted into the alteration ruler meeting host node design rule, this is a process very consuming time equally.In addition, owing to needing to store the domain that reduces in this process and taking a large amount of disk spaces.
Therefore, in prior art, there is above-mentioned multiple drawback in the analogy method of VCMP in DFM, needs to make further improvements described method, to eliminate above-mentioned drawback.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection domain attempting to determine technical scheme required for protection.
The present invention, in order to solve problems of the prior art, provides the operation method of half node CMP model in a kind of host node domain, comprising:
Step (a): host node domain is provided;
Step (b): described host node domain is divided into some net regions, and directly geometry extraction is carried out to each described net region, acquisition number value information;
Step (c): reduced to obtain half-section point geometry information by the described geological information in described numerical information, carries out half node CMP according to described half-section point geometry information and simulates;
Step (d): export analog result data, and determine the defect point in described simulation process;
Step (e): on described host node domain, described defect point is analyzed;
Step (f): produce domain amendment and instruct rule, and modify.
As preferably, described step (b) comprises following sub-step:
Step (b-1): described host node domain is divided into some described net regions according to grid resolution;
Step (b-2): described net region does not reduce, directly carries out geometry extraction, and acquisition number value information is to represent described host node domain.
As preferably, described numerical information comprises identifying information and geological information.
As preferably, described identifying information comprises grid numbering and mesh coordinate;
Described geological information comprises mesh-density, grid live width and grid girth.
As preferably, described step (c) comprises following sub-step:
Step (c-1): reduced by the described geological information representing host node domain by the process shrink factor, to obtain the described half-section point geometry information representing described half node domain;
Step (c-2): carry out half node CMP according to described half-section point geometry information and simulate, to obtain described analog result.
As preferably, described step (d) comprises following sub-step:
Step (d-1): the simulation value information obtained in being simulated by described half node CMP exports, to obtain described analog result;
Step (d-2) checks described simulation value information, the simulation value information of abnormality is leached;
The identifying information of step (d-3) corresponding to the simulation value of described abnormality finds grid corresponding on described host node domain, to determine defect point.
As preferably, described defect point refers to the net region that analog result surpasss the expectation, and described net region is run counter to the pattern of design rule or irrational territory pattern.
As preferably, after carrying out described amendment, repeated execution of steps (a)-step (f) is till passing through checking.
Present invention also offers a kind of semiconductor layout preparation method, described method comprises the step selecting above-mentioned method to carry out half node CMP simulation in host node domain.
The present invention is in order to solve problems of the prior art, provide a kind of half node VCMP simulated technological process method be applied in host node domain, described method is by the size of mesh opening (Gridsize) in adjustment VCMP method, namely by simulation resolution (VCMPsimulationResolution) and the process shrink factor of adjustment VCMP, avoid the processing step of two at substantial times in prior art, to improve simulation precision.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
The process chart that in Fig. 1 prior art prepared by domain;
Process chart prepared by the host node domain comprising CMP in Fig. 2 a prior art;
Process chart prepared by the half node domain comprising CMP in Fig. 2 b prior art;
Fig. 3 is the schematic flow sheet of the host node domain Picking up geometry information comprising CMP in the embodiment of the invention;
Fig. 4 a is the structural representation that the host node domain size of mesh opening comprising CMP in prior art reduces;
Fig. 4 b is the structural representation that the host node domain size of mesh opening comprising CMP in the embodiment of the invention reduces;
Fig. 5 is process chart prepared by the host node domain comprising CMP in the embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, use the element that identical Reference numeral represents identical, thus will omit description of them.
Below in conjunction with accompanying drawing, the operation method of half node CMP model in a kind of host node domain of the present invention is described further.
Embodiment 1
The present invention is in order to solve problems of the prior art, provide a kind of half node VCMP simulated technological process method be applied in host node domain, described method is by the size of mesh opening (Gridsize) in adjustment VCMP method, namely by the simulation resolution (VCMPsimulationResolution) of adjustment VCMP and drag into and reduce the factor, the processing step of two at substantial times in prior art is avoided.
Fig. 5 is process chart prepared by the host node domain comprising CMP in invention one embodiment, and composition graphs 5 pairs of the method for the invention are further described.
Particularly, comprise the following steps:
Step (a): host node domain is provided;
Step (b): described host node domain is divided into some net regions, and directly geometry extraction is carried out to each described net region, obtain numerical information;
Step (c): the geological information in described numerical information is reduced obtain half-section point geometry information, carry out half node CMP according to described half-section point geometry information and simulate;
Step (d): export analog result data, and determine the defect point in described simulation process;
Step (e): on described host node domain, the described defect point obtained is analyzed;
Step (f): produce domain amendment and instruct rule, and modify.
Particularly, wherein, in described step (a), described host node domain refers to that it has the domain structure of large-size, the domain structure of the nodes such as such as 65nm, 45nm, but is not limited to described numerical range.Along with the size of development need domain structure described in half node (half-node) technique of technology is less than the size of host node domain structure.
Described step (b) comprises following sub-step:
Described host node domain is divided into some net regions according to grid resolution by step (b-1);
Step (b-2) described net region does not reduce, and directly carries out geometry extraction, obtains carrying numerical information to represent described host node domain.
Particularly, in this step, before VCMP simulation, must by required resolution (i.e. size of mesh opening, Gridsize) layout information is extracted, in the process extracting layout information, first described host node domain divides multiple grid (Grid) into, then the identifying information (IdentificationInformation) in described each grid and geological information (Geometryinformation) is extracted, as shown in Figure 3, for the schematic flow sheet that the half node territory pattern and size of mesh opening that comprise CMP in the embodiment of the invention reduce.
Wherein said identifying information (IdentificationInformation) comprises mesh coordinate (coordinate), grid numbering (GridID); Described geological information (Geometryinformation) comprises density (Density), live width (LineWidth) and girth (Perimeter) etc.
Next after extraction obtains described numerical information, described domain is represented by a series of described numerical information, and described a series of geological information is for simulation process.
Described resolution (resolution) or size of mesh opening (Gridsize) are undertaken adjusting by the amplification (magnification) of described net region or the process shrink factor in the present invention.Wherein Fig. 4 b comprises the process that the host node territory pattern of CMP and size of mesh opening reduce in the embodiment of the invention, can be observed by this process, in the prior art, first described host node domain selects domain instrument to be reduced described host node domain by process shrink factor f, then the domain after reducing is extracted by size of mesh opening m, after extraction, described grid identifying information and geological information all reduce relative to host node domain, as shown in fig. 4 a.
And in the embodiment of the application, described host node domain is directly extracted by size of mesh opening n, pass between wherein said n and m is m=n × f, as shown in Figure 4 b, in the method for prior art He in the method for the invention, there is identical lattice number or identical mesh shape, unlike, in the method for the invention, the identifying information of described grid and geological information all do not reduce after the extraction.
Size of mesh opening described in the present invention or resolution are by the product of the inverse of grid resolution of the prior art or size of mesh opening M and process shrink factor f, described size of mesh opening does not reduce in the present invention, obtains after directly being divided by described host node domain.
In practical operation, described processing step reduces from host node domain the wafer obtaining half node territory pattern carry out operating for having, therefore, VCMP simulation must run according to described half-section point geometry information, therefore perform step (c) and described geological information is contracted to half-section point geometry information, carry out half node CMP according to described half-section point geometry information and simulate.
Described step (c) comprises following sub-step:
The geological information represented in the described numerical information of host node domain is reduced by the process shrink factor by step (c-1), to obtain described half-section point geometry information, to represent half node domain;
Step (c-2) carries out CMP simulation, to obtain analog result according to described half-section point geometry information.
Particularly, in the prior art, after extracting layout information, described layout information reduces, so directly VCMP simulation can be carried out, and in the method for the invention, the layout information of described extraction does not reduce, therefore before carrying out VCMP simulation, a reduction process must be performed, described reduction process is realized by process shrink factor f in VCMP flow process in this embodiment, in this embodiment, described reduction process is carried out for extracting the geological information data obtained, physical layout is not reduced, carry out processing for geological information data and save a large amount of time.
Improvements of the present invention are not reduced by the geometric figure of domain, but the layout information extracted is carried out reducing process, to represent half node layout information, thus avoid in prior art the step that domain reduces, save a large amount of time, particularly in batch process.
Then the layout information after reducing is used to carry out CMP simulation, described VCMP analogy method is identical with method in prior art, carry out for reducing rear geometry domain, just the method for the invention reduces described numerical information after extracting numerical information, then simulate, do not repeat them here.
After the information of expression half node domain carries out simulation acquisition analog result, export analog result, to obtain described defect point and related data, to search the defect point in described simulation process, comprise following sub-step:
Step (d-1) obtains simulation value information in being simulated by simulation CMP and exports, to obtain analog result;
Step (d-2) checks described simulation value information according to the filter algorithm of writing in advance, the simulation value information of abnormality is leached;
The identifying information of step (d-3) corresponding to the simulation value of described abnormality finds grid corresponding on described host node domain, to determine defect point.
Particularly, after simulation steps, along with the output of identifying information and geological information, thus acquisition analog result, thickness and CMP depression (dishing) etc. is comprised in described analog result, meanwhile, the grid of some special (extraordinary) can be leached by the filtering algorithm (filteringalgorithm) write in advance, and the described grid leached becomes defect point (hotspot).
Described defect point (hotspot) typically refers to analog result and exceeds anticipation, described defect point is mostly run counter to the pattern of design rule or irrational territory pattern, such as, have the density of ultralow or superelevation or have too large or too little live width etc.
By described geological information, the identifying information running counter to design rule can be very directly found, then according to this identifying information, directly described defect point grid can be found by domain preview instrument in domain the preview window.
In this step due to described layout information and described host node grid one_to_one corresponding, therefore do not need to process described information, corresponding net region directly can be found according to described layout information, thus avoid in prior art obtain analog result after need to be converted into the result (namely carry out amplification process) corresponding with host node domain, save the plenty of time.
On described host node domain, defect point analysis is carried out, to determine whether described defect point is the structure wishing to obtain, if the result of wishing does not need to modify, by checking in described step (e); If desired modify, perform step (f).
In described step (f) after modifying, repeated execution of steps (a)-step (f) is to passing through checking.
Particularly, produce amendment instruct rule according to described domain preview and geological information, such as increasing dummy pattern or inserting groove (Slot) increases or reduces the density in defect point region.
The difference of the method for the invention and prior art is, information extraction described in prior art is reduced, obtain amendment instruct rule be for the described domain reduced, in order to correct is located in host node domain, rule must be instructed to reduce the factor according to reduction process to described amendment to amplify, and identifying information, by host node domain extracting directly, does not reduce described in described method of the present invention, so avoid the step of amplifying domain.
Embodiment 2
Present invention also offers a kind of manufacturability design, comprise the operation method of half node CMP model in above-mentioned host node domain.
In addition, present invention also offers a kind of semiconductor layout preparation method, comprise the step of described manufacturability design.
Particularly, described domain preparation method comprises provides domain, then inserts sealing ring and inserts, insert dummy pattern, carry out the checking designed, if described domain is not revised, the preparation carrying out domain exports, if there is amendment, then amended domain is re-started inspection.
The checking of wherein said design comprises manufacturability design (DesignforManufacturing, and DRC (DRC DFM), DesignRuleCheck), wherein, described DFM comprises virtual chemically mechanical polishing (VirtualChemicalMechanicalPolishing, VCMP), photoetching electronic analysis (LithoElectricAnalysis), critical area analyzes (CriticalAreaAnalysis), domain approach effect (LayoutProximityEffect), domain independence effect (LayoutDepenmentEffect) etc.
Wherein, described virtual chemically mechanical polishing (VirtualChemicalMechanicalPolishing, VCMP) selects the method described in embodiment 1, uses VCMP to simulate the change of thickness and the thickness can predicted after the cmp step.By using special filter algorithm (filteringalgorithm), the wafer landform surpassed the expectation or thickness are filtered off, become defect point (hotspot), described defect point (hotspot) will be identified and analyze as design and distributing adjustment or amendment further.
The present invention is in order to solve problems of the prior art, provide a kind of VCMP simulated technological process method be applied in host node domain, described method is by the size of mesh opening (Gridsize) in adjustment VCMP method, namely by simulation resolution (VCMPsimulationResolution) and the process shrink factor of adjustment VCMP, avoid the processing step of two at substantial times in prior art, to improve simulation precision.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (9)
1. the operation method of half node CMP model in host node domain, comprising:
Step (a): host node domain is provided;
Step (b): described host node domain is divided into some net regions, and directly geometry extraction is carried out to each described net region, acquisition number value information;
Step (c): the geological information in described numerical information is reduced obtain half-section point geometry information, carry out half node CMP according to described half-section point geometry information and simulate;
Step (d): export analog result data, and determine the defect point in described simulation process;
Step (e): on described host node domain, described defect point is analyzed;
Step (f): produce domain amendment and instruct rule, and modify.
2. method according to claim 1, is characterized in that, described step (b) comprises following sub-step:
Step (b-1): described host node domain is divided into some described net regions according to grid resolution;
Step (b-2): described net region does not reduce, directly carries out geometry extraction, and acquisition number value information is to represent described host node domain.
3. method according to claim 1, is characterized in that, described numerical information comprises identifying information and geological information.
4. method according to claim 3, is characterized in that, described identifying information comprises grid numbering and mesh coordinate;
Described geological information comprises mesh-density, grid live width and grid girth.
5. method according to claim 1, is characterized in that, described step (c) comprises following sub-step:
Step (c-1): reduced by the described geological information representing host node domain by the process shrink factor, to obtain the described half-section point geometry information representing described half node domain;
Step (c-2): half node CMP is carried out to the described half-section point geometry information obtained and simulates, to obtain described analog result.
6. method according to claim 1, is characterized in that, described step (d) comprises following sub-step:
Step (d-1): the simulation value information obtained in being simulated by described half node CMP exports, to obtain described analog result;
Step (d-2) checks described simulation value information, the simulation value information of abnormality is leached;
The identifying information of step (d-3) corresponding to the simulation value of described abnormality finds grid corresponding on described host node domain, to determine defect point.
7. method according to claim 1, is characterized in that, described defect point refers to the net region that analog result surpasss the expectation, and described net region is run counter to the pattern of design rule or irrational territory pattern.
8. method according to claim 1, is characterized in that, after carrying out described amendment, repeated execution of steps (a)-step (f) is till passing through checking.
9. a semiconductor layout preparation method, described method comprises the step selecting the described method of one of claim 1 to 8 to carry out half node CMP simulation in host node domain.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105760604A (en) * | 2016-02-19 | 2016-07-13 | 上海集成电路研发中心有限公司 | Modeling method for statistic model based on territory proximity effect |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101620644A (en) * | 2008-06-25 | 2010-01-06 | 台湾积体电路制造股份有限公司 | Integrated circuit design in optical shrink technology node |
| CN102024083A (en) * | 2010-12-15 | 2011-04-20 | 中国科学院微电子研究所 | Method for extracting capacitance of interconnection structures containing redundant metal |
| CN102110182A (en) * | 2009-12-28 | 2011-06-29 | 台湾积体电路制造股份有限公司 | Integrated circuit design method |
| CN102521468A (en) * | 2011-12-30 | 2012-06-27 | 中国科学院微电子研究所 | Method for extracting parasitic parameters of interconnection lines and device |
| CN103559364A (en) * | 2013-11-13 | 2014-02-05 | 中国科学院微电子研究所 | Method for extracting graphic features of layout of chip and CMP simulation method |
-
2014
- 2014-04-22 CN CN201410163106.3A patent/CN105095532B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101620644A (en) * | 2008-06-25 | 2010-01-06 | 台湾积体电路制造股份有限公司 | Integrated circuit design in optical shrink technology node |
| CN102110182A (en) * | 2009-12-28 | 2011-06-29 | 台湾积体电路制造股份有限公司 | Integrated circuit design method |
| CN102024083A (en) * | 2010-12-15 | 2011-04-20 | 中国科学院微电子研究所 | Method for extracting capacitance of interconnection structures containing redundant metal |
| CN102521468A (en) * | 2011-12-30 | 2012-06-27 | 中国科学院微电子研究所 | Method for extracting parasitic parameters of interconnection lines and device |
| CN103559364A (en) * | 2013-11-13 | 2014-02-05 | 中国科学院微电子研究所 | Method for extracting graphic features of layout of chip and CMP simulation method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105760604A (en) * | 2016-02-19 | 2016-07-13 | 上海集成电路研发中心有限公司 | Modeling method for statistic model based on territory proximity effect |
| CN105760604B (en) * | 2016-02-19 | 2019-01-18 | 上海集成电路研发中心有限公司 | The modeling method of statistical model based on domain kindred effect |
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