CN105072068A - Automatic carrier wave demodulation control circuit for short-distance wireless communication - Google Patents
Automatic carrier wave demodulation control circuit for short-distance wireless communication Download PDFInfo
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- CN105072068A CN105072068A CN201510536355.7A CN201510536355A CN105072068A CN 105072068 A CN105072068 A CN 105072068A CN 201510536355 A CN201510536355 A CN 201510536355A CN 105072068 A CN105072068 A CN 105072068A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0002—Modulated-carrier systems analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line
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Abstract
The invention provides an automatic carrier wave demodulation control circuit for short-distance wireless communication. The automatic carrier wave demodulation control circuit comprises a miller pulse burr filtering circuit, a miller pulse detection circuit and a demodulation control state machine; the miller pulse burr filtering circuit is used for filtering burr of a miller code stream input under a system clock domain; the miller pulse detection circuit is used for counting and detecting pulse of the miller code stream by adopting four fractional frequency clocks of a system clock; and the demodulation control state machine is used for switching a sending state and a receiving state according to a miller coding time sequence and a count value of the miller pulse detection circuit by adopting the four fractional frequency clocks of the system clock and generating an enable signal for controlling an analogue demodulation circuit. According to the automatic carrier wave demodulation control circuit disclosed by the invention, in case of no instruction input, a receiving circuit judges sending start and sending stop only according to a sent miller coding waveform; and a control signal simulating carrier wave demodulation is generated according to an internal demodulation signal and related waiting signals.
Description
Technical field
The present invention relates to a kind of circuit of wireless communication field, specifically relate to a kind of carrier wave demodulation automatic control circuit for short-distance wireless communication.
Background technology
Miller code technology is used in active antenna near-field communication field always, but the high correlation of its code length and time length is very effective for the coding of some special instruction, such as gesture, voice etc.The present invention applies for this coding exactly, devises a set of carrier wave demodulation automatic control circuit that can be applicable to short haul connection, for the carrier wave demodulation of the Miller code based on the signal such as gesture, voice.
Summary of the invention
For overcoming above-mentioned the deficiencies in the prior art, the invention provides a kind of carrier wave demodulation automatic control circuit for wireless near field communication, realizing automatically controlling analog demodulation circuit, reduce circuit power consumption.
Realizing the solution that above-mentioned purpose adopts is:
For a carrier wave demodulation automatic control circuit for short-distance wireless communication, its improvements are: described circuit comprises the Miller pulse filter burr circuit, the Miller pulse-detecting circuit reconciliation regulation and control state machine processed that connect successively;
Described Miller pulse filter burr circuit, for carrying out the process of filter burr to the miller code stream of input under system clock domain;
Described Miller pulse-detecting circuit, adopts 4 frequency-dividing clocks of system clock, for carrying out count detection to the pulse of Miller code stream;
Described demodulation state of a control machine, adopts 4 frequency-dividing clocks of system clock, for switching transmission state and accepting state according to the count value of Miller code sequential and Miller pulse-detecting circuit, and produces the enable signal being used for control simulation demodulator circuit.
Preferably, described Miller pulse filter burr circuit, comprising: the first d type flip flop, the second d type flip flop, 3d flip-flop and comparator;
System clock inputs the input end of clock of described first d type flip flop, described second d type flip flop and described 3d flip-flop respectively;
The input D termination of described first d type flip flop receives Miller code stream, and the output Q end of described first d type flip flop connects the input D end of the second d type flip flop and the input of described comparator respectively;
The output Q of described second d type flip flop holds another input phase connecting described comparator; The input D of the described 3d flip-flop of output connection of described comparator holds;
Miller code stream under described first d type flip flop and described second d type flip flop system clock sampling wireless near field communication pattern;
The output of described comparator to described first d type flip flop and described second d type flip flop compares, if the output of the two is equal, then system clock is adopted to sample by described 3d flip-flop, and hold at the output Q of 3d flip-flop the Miller pulse signal to be detected exporting deburring, if different, then the output signal of 3d flip-flop is not sampled.
Preferably, described Miller pulse filter burr circuit, comprising: status comparator, inverter, selector and 7bit counter;
Described status comparator accepting state signal, described inverter receives synchronous Miller code signal;
Described selector receives described synchronous Miller code signal and the synchronous Miller code signal after described inverter process, it selects control end to be connected with the output of described status comparator, selects the inversion signal of synchronous Miller code signal or synchronous Miller code signal under the control of described status comparator;
The synchronous reset end of described 7bit counter is connected with the output of described selector, and its counting input end receives 4 frequency-dividing clocks of 13.56MHz system clock, using this 4 frequency-dividing clock as counting clock;
The counting operation of described 7bits counter controls by state machine, when state machine is transmission state, the low duration of counting Miller pulse, when state machine be idle condition or accepting state time, detect the high level lasting time of described Miller pulse, the synchronous reset end of 7bits counter is switched by status comparator.
Preferably, control the signal of described state machine with 2 bits of encoded demodulation, comprise idle condition, transmission state, accepting state and pre-receiving state.
Preferably, when described state machine detects the count value of Miller pulse detection counter in idle condition under described idle condition, after effective Miller low level pulse being detected, described transmission state is entered;
Detect in described transmission state Miller pulse high level detect count value, when count value meter to 64 time, namely described state machine enters pre-receiving state;
Whether in described pre-receiving state, detect waiting signal before receiving be ready to, latency counter meter provides after wait is ready to after expiring before from the reception of system clock domain, and namely described state machine jumps to described accepting state;
The subcarrier useful signal of detection system in described accepting state, when after subcarrier useful signal step-down, finishes receiving state machine and jumps into described idle condition.
Compared with immediate prior art, the present invention has following beneficial effect:
Carrier wave demodulation automatic control circuit provided by the invention, can not have under instruction input condition, receiving circuit is made only to judge send beginning and terminate according to the Miller code waveform sended over, and according to the restituted signal of inside and the control signal of associated wait signal generation analog carrier demodulation.
Adopt cascaded triggers feedback mechanism, can automatically detect Miller pulse duration, adjudicate the condition being sent completely and sending beginning in conjunction with ISO/IEC14443 protocol specification, and carry out the opening and closing of control simulation demodulator circuit by demodulation state of a control machine.
It achieves the automatic control to analog demodulation circuit, and do not need the intervention of main control chip MCU, can independently make circuit complete the switch control rule of the analog carrier circuit of transceiving data as a control logic, while realizing above function, also reduce the power consumption of circuit.
Carried out processing targetedly to the transmission coding characteristic of 106KtypeA in conjunction with in ISO/IEC14443 agreement for special applications scene, this carrier wave demodulation automatic control circuit can meet the application requirement of wireless near field communication.
Accompanying drawing explanation
Fig. 1 is the envelope diagram of the carrier waveform of Miller code in the present invention and the time span definition schematic diagram of contoured shaped recess thereof;
Fig. 2 is the carrier wave demodulation automatic control circuit theory diagram being applied to short-distance wireless communication provided by the invention;
Fig. 3 is Miller pulse filter burr schematic block circuit diagram in the present embodiment;
Fig. 4 is Miller pulse detection counter principle block diagram in the present embodiment;
Fig. 5 is demodulation state of a control machine state transition diagram in the present embodiment.
Embodiment
Below with reference to accompanying drawings exemplary embodiment of the present disclosure is described in more detail.Although show exemplary embodiment of the present disclosure in accompanying drawing, but be to be understood that, can realize in a variety of manners the disclosure and not should limit by the embodiment set forth here, other embodiments can comprise structure, logic, electric, process and other change.Embodiment only represents possible change.On the contrary, provide these embodiments to be in order to more thoroughly the disclosure can be understood, and complete for the scope of the present disclosure can be conveyed to those skilled in the art.Herein, these embodiments of the present invention can be represented with term " invention " individually or always, this is only used to conveniently, and if in fact disclose the invention more than, be not the scope that will limit this application is automatically any single invention or inventive concept.
Fig. 1 is the envelope diagram of the carrier waveform of Miller code in the present invention and the time span definition of contoured shaped recess thereof;
Fig. 2 is the carrier wave demodulation automatic control circuit theory diagram being applied to short-distance wireless communication provided by the invention; Control circuit provided by the invention is a kind of carrier wave demodulation automatic control circuit being applied to short-distance wireless communication based on ISO/IEC14443 agreement typeA.
This automatic control circuit comprises: Miller pulse filter burr circuit, Miller pulse-detecting circuit conciliate regulation and control state machine processed.
Wherein, Miller pulse filter burr circuit and Miller pulse-detecting circuit are interconnected, and Miller pulse-detecting circuit is conciliate regulation and control state machine processed and is interconnected.
Conciliate regulation and control state machine processed further illustrate respectively for above-mentioned Miller pulse filter burr circuit, Miller pulse-detecting circuit.
Miller pulse filter burr circuit
As shown in Figure 3, Fig. 3 is Miller pulse filter burr schematic block circuit diagram in the present embodiment; Described Miller pulse filter burr circuit, comprising: the first d type flip flop, the second d type flip flop, 3d flip-flop and a comparator.
The clock input system clock of the first d type flip flop DCF1, the second d type flip flop DCF2 and 3d flip-flop DCF3.
The input D termination of the first d type flip flop DCF1 receives Miller code stream, and the output Q end of the first d type flip flop DCF1 holds with the input D of the second d type flip flop DCF2 the input being connected described comparator respectively; The output Q of the second d type flip flop DCF2 holds another input of described comparator to be connected;
The output of comparator is held with the input D of 3d flip-flop DCF3 and is connected;
The Miller code stream of first d type flip flop DCF1 and the second d type flip flop DCF2 under system clock sampling short-distance wireless communication pattern; The Output rusults of comparator to the first d type flip flop DCF1 and the second d type flip flop DCF2 compares, if the output of the two is equal, then adopt system clock to sample by 3d flip-flop DCF3, and hold at the output Q of 3d flip-flop the Miller pulse signal to be detected exporting deburring; If the output of the two is unequal, then the output signal of 3d flip-flop is not sampled.
Miller pulse-detecting circuit
As shown in Figure 4, Fig. 4 is Miller pulse detection counter principle block diagram in the present embodiment; This Miller pulse-detecting circuit, comprising: status comparator, inverter, selector and 7bit counter.
Wherein, status comparator, accepting state signal Fsm_state [1:0], the input selection of controlled selector;
Inverter NOT, receives Miller_stream_syn signal (synchronous Miller code signal);
Selector mux, receive described Miller_stream_syn signal and the Miller_stream_syn signal after described inverter process, it selects control end to be connected with the output of described status comparator, under the accepting state signal Fsm_state [1:0] of described status comparator controls, namely " 01 " represents selection Miller_stream_syn signal, and " 10 " represent the inversion signal selecting Miller_stream_syn;
7bit counter, its synchronous reset end is connected with the output of selector mux, and its counting input end receives 4 frequency-dividing clocks of 13.56MHz system clock, using this 4 frequency-dividing clock as counting clock.
The counting operation of 7bits counter controls by state machine, when state machine is transmission state, the low duration of counting miller_pulse (Miller pulse), when state machine be idle condition or accepting state time, detect the high level lasting time of miller_pulse, the synchronous reset end of 7bits counter is switched by status comparator.
With the demodulation state of a control machine signal of 2bit coding, totally 4 states, i.e. idle condition (idle), transmission state (send), accepting state (rcv) and pre-receiving state (rcv_pre), the redirect relation of each state as shown in Figure 5.
The low level detecting miller_pulse in idle condition detects counting, and namely Miller pulse detection counter is in the count value of idle condition, after effective Miller low level pulse being detected, namely enters transmission state; The high level detecting miller_pulse in transmission state detects count value, when count value meter to 64 time, represent continuous 2 etu (1 etu is 9.472us) the not modulation of Miller code stream, namely state machine enters pre-receiving state; Before pre-receiving state-detection receives, whether waiting signal is ready to, and after providing wait ready after latency counter meter before the reception from etu clock zone is full, namely state machine jumps to accepting state; At the sub-carrier modulation useful signal s_valid of accepting state detection system, when after sub-carrier modulation useful signal s_valid step-down, namely represent and finish receiving, state machine jumps into idle condition.
Detect that effective groove marking signal (Mf_in) is for after mfin_npause_valid (namely groove mark is effective), state machine enters transmission state.
In transmission state, start continuous 2 high/low level sensitive circuits of etu of Mf_in, after detecting that Mf_in_sync (i.e. Miller_stream_syn) is for continuous print 2 etu time high level, namely enter pre-receiving state.When detecting that Mf_in_sync is for after being greater than 4.5 μ s time low levels, namely enters idle condition, again detects effective Mf_in_sync groove.
Redirect marking signal during this state is mfin_npause_stop signal.Wherein,
mfin_npause_stop＝(state＝＝send)&&(clk4_det_cnt＝＝64)。
In pre-receiving state, starting rx_wait_cnt (receive and wait for counter), doing from subtracting counting, after rx_wait_end (namely reception is waited for and being stopped) signal being detected, enter accepting state.This state slave_only_analog_en (servo enable signal) puts 1, pre-unlatching analog carrier demodulator circuit.This is because usually have a stationary phase in the carrier wave demodulation incipient stage, open analog carrier demodulator circuit in this critical condition, reserve enough time and reach stable state by analog carrier demodulator circuit.
In accepting state, stay open analog carrier demodulator circuit, namely slave_only_analog_en puts 1, in accepting state, by detection 2 signals, one is effective groove of Mf_in_sync and the decline edge of s_valid signal, namely, when being in accepting state, can be interrupted and closing receiving demodulation circuit reentering transmission state by the effective Mf_in groove sent from master, or normally ought receive end, after the trailing edge of s_valid signal being detected, state machine enters idle condition.
Wherein, s_valid signal is the sub-carrier modulation useful signal of the subcarrier demodulator circuit of receiving terminal inside, when this signal is 1, represents and receives beginning, represent do not had sub-carrier modulation, receive when this signal is 0.
Finally should be noted that: above embodiment is only for illustration of the technical scheme of the application but not the restriction to its protection range; although with reference to above-described embodiment to present application has been detailed description; those of ordinary skill in the field are to be understood that: those skilled in the art still can carry out all changes, amendment or equivalent replacement to the embodiment of application after reading the application; but these change, revise or be equal to replacement, all applying within the claims awaited the reply.
Claims (5)
1. for a carrier wave demodulation automatic control circuit for short-distance wireless communication, it is characterized in that: described circuit comprises the Miller pulse filter burr circuit, the Miller pulse-detecting circuit reconciliation regulation and control state machine processed that connect successively;
Described Miller pulse filter burr circuit, for carrying out the process of filter burr to the miller code stream of input under system clock domain;
Described Miller pulse-detecting circuit, adopts 4 frequency-dividing clocks of system clock, for carrying out count detection to the pulse of Miller code stream;
Described demodulation state of a control machine, adopts 4 frequency-dividing clocks of system clock, for switching transmission state and accepting state according to the count value of Miller code sequential and Miller pulse-detecting circuit, and produces the enable signal being used for control simulation demodulator circuit.
2. a kind of carrier wave demodulation automatic control circuit for short-distance wireless communication as claimed in claim 1, is characterized in that: described Miller pulse filter burr circuit, comprising: the first d type flip flop, the second d type flip flop, 3d flip-flop and comparator;
System clock inputs the input end of clock of described first d type flip flop, described second d type flip flop and described 3d flip-flop respectively;
The input D termination of described first d type flip flop receives Miller code stream, and the output Q end of described first d type flip flop connects the input D end of the second d type flip flop and the input of described comparator respectively;
The output Q of described second d type flip flop holds another input phase connecting described comparator; The input D of the described 3d flip-flop of output connection of described comparator holds;
Miller code stream under described first d type flip flop and described second d type flip flop system clock sampling wireless near field communication pattern;
The output of described comparator to described first d type flip flop and described second d type flip flop compares, if the output of the two is equal, then system clock is adopted to sample by described 3d flip-flop, and hold at the output Q of 3d flip-flop the Miller pulse signal to be detected exporting deburring, if different, then the output signal of 3d flip-flop is not sampled.
3. a kind of carrier wave demodulation automatic control circuit for short-distance wireless communication as claimed in claim 1, is characterized in that: described Miller pulse filter burr circuit, comprising: status comparator, inverter, selector and 7bit counter;
Described status comparator accepting state signal, described inverter receives synchronous Miller code signal;
Described selector receives described synchronous Miller code signal and the synchronous Miller code signal after described inverter process, it selects control end to be connected with the output of described status comparator, selects the inversion signal of synchronous Miller code signal or synchronous Miller code signal under the control of described status comparator;
The synchronous reset end of described 7bit counter is connected with the output of described selector, and its counting input end receives 4 frequency-dividing clocks of 13.56MHz system clock, using this 4 frequency-dividing clock as counting clock;
The counting operation of described 7bits counter controls by state machine, when state machine is transmission state, the low duration of counting Miller pulse, when state machine be idle condition or accepting state time, detect the high level lasting time of described Miller pulse, the synchronous reset end of 7bits counter is switched by status comparator.
4. a kind of carrier wave demodulation automatic control circuit for short-distance wireless communication as claimed in claim 3, is characterized in that: the signal controlling described state machine with 2 bits of encoded demodulation, comprises idle condition, transmission state, accepting state and pre-receiving state.
5. a kind of carrier wave demodulation automatic control circuit for short-distance wireless communication as claimed in claim 4, it is characterized in that: when described state machine detects the count value of Miller pulse detection counter in idle condition under described idle condition, after effective Miller low level pulse being detected, enter described transmission state;
Detect in described transmission state Miller pulse high level detect count value, when count value meter to 64 time, namely described state machine enters pre-receiving state;
Whether in described pre-receiving state, detect waiting signal before receiving be ready to, latency counter meter provides after wait is ready to after expiring before from the reception of system clock domain, and namely described state machine jumps to described accepting state;
The subcarrier useful signal of detection system in described accepting state, when after subcarrier useful signal step-down, finishes receiving state machine and jumps into described idle condition.
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| CN110246325A (en) * | 2019-06-21 | 2019-09-17 | 广州科技贸易职业学院 | A kind of digital infrared remote-controlled signal modulation circuit and its modulator approach |
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| CN104702545A (en) * | 2013-12-05 | 2015-06-10 | 上海华虹集成电路有限责任公司 | Carrier demodulation and automatic control circuit under typeA active antenna application slave mode |
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| CN101512563A (en) * | 2006-09-06 | 2009-08-19 | Nxp股份有限公司 | Method for supplying electrical energy from a first electronic circuit to a second electronic circuit via at least one wire line |
| CN101741390A (en) * | 2008-11-21 | 2010-06-16 | 爱思开电讯投资（中国）有限公司 | Differential Miller coding and decoding methods and devices for near field communication system |
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Effective date of registration: 20170524 Address after: Suzhou City, Jiangsu province 215000 town Kunshan City Jin Yang Lu No. 15 room 2 Applicant after: Kunshan wisdom Electronic Technology Co., Ltd. Address before: 201315, room 12, building 250, Lane 302, Shen Shen road, Shanghai, Pudong New Area Applicant before: Zhao Shuang |
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Application publication date: 20151118 |