CN105071808B - A kind of phase quantization analog-digital converter circuit with the calibration of addition weight - Google Patents
A kind of phase quantization analog-digital converter circuit with the calibration of addition weight Download PDFInfo
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Abstract
The invention discloses a kind of phase quantization analog-digital converter circuit with the calibration of addition weight, it is related to a kind of microcircuit structures, more particularly to a kind of analog-digital converter circuit for realizing phase quantization.For traditional circuit in phase weighting the problems such as the difference of the non-linear amplitude weight between out of phase of adder Module, the present invention proposes a kind of new circuit framework：Addition weight calibration module is added on the basis of traditional circuit, the module includes error voltage detection sub-module and quiescent current adjustment submodule.By addition weight calibration module, adder output voltage is detected, controls the working condition of adder Module, realizes that addition weight is calibrated.The present invention can eliminate the phase error that the difference of the non-linear amplitude weight between out of phase of adder Module introduces, and improve circuit performance, save time and the cost of research and development, have a good application prospect.
Description
Technical field
The present invention relates to a kind of microcircuit structures, more particularly to one kind can realize phase quantization, and and can is weighed by addition
Recalibration eliminates the analog-digital converter circuit that quantization error is introduced by amplitude error.
Background technology
ECM role in modern war is more and more important, it has also become determines the pass of battlefield control
Key factor.Meanwhile with the high speed development of Radar Technology, its working frequency range has no longer been single wave band, but include whole
Microwave band, working system are also that progressively instead of letter by the coherent system radar such as compression in pulse Doppler (PD) system and arteries and veins
Single pulse regime.Therefore, have to radar electronic warfare technology and update higher requirement, in Development of Novel Radar ECM technology
During, digital radiofrequency memory (DRFM) technology is accompanied, using high-speed sampling and stored digital as its technology base
Plinth, there is the storage to radio frequency and microwave signal and reproduction, there is good Disturbance and deceit effect to coherent radar, turn into
The hot spot technology of various countries' research, application prospect are very extensive.
The circuit framework of digital radiofrequency memory is as shown in figure 1, phase quantization analog-digital converter circuit is its important composition
Part, for realizing the sampling and quantization of input signal, its speed sampled and precision determine digital radiofrequency memory circuit
Performance.It is different from traditional amplitude quantizing analog-digital converter, the phase letter of phase quantization analog-digital converter concern sampled signal
Breath, have the characteristics that the signal to noise ratio requirement to input signal is low, input signal dynamic range is big and working frequency is wide.Its is basic
Structure is as shown in Figure 2.
The existing phase quantization analog-digital converter circuit course of work is as follows：Radiofrequency signal exports I after quadrature frequency conversion,
Q two paths of signals, after equiphase interval multichannel differential signal is obtained after adder circuit, multichannel differential signal is sent into corresponding
Comparator circuit, comparative result realize the conversion of data format via digital encoding circuit, and last serial-parallel conversion circuit will be completed
The signal of serioparallel exchange is sent.
But with the continuous improvement of quantified precision and speed, the drawbacks of existing phase quantization analog-digital converter circuit
Also it is increasingly apparent.During phase weighting is realized, the difference of the non-linear amplitude weight between out of phase of adder circuit
It is different, it can cause the output phase information of adder that deviation occurs, so as to deteriorate the output result of comparator circuit, finally significantly drop
The quantified precision of low phase quantization analog-digital converter circuit, add the bit error rate of circuit.
The content of the invention
The purpose of the present invention is intended to propose a kind of phase quantization analog-digital converter circuit with the calibration of addition weight, solves
Addition weight unbalance in existing phase quantization analog-digital converter circuit.The present invention can eliminate the non-linear of adder circuit
The difference of amplitude weight between out of phase, it is ensured that the equilibrium of adder circuit output result, meet phase quantization analog-to-digital conversion
Performance requirement of the device circuit under high accuracy and high workload frequency condition.
To achieve these goals, technical solution of the invention is：A kind of phase quantization with the calibration of addition weight
Analog-digital converter circuit, including adder Module 1, addition weight calibration module 2, comparator module 3, digital coding module 4, string
And modular converter 5 and low-voltage differential signal sending module 6, adder Module 1 receive I road signals and Q roads signal, I roads are believed
Number with Q roads signal carry out phase be added after obtain multichannel differential signal, multichannel differential signal is respectively outputted to comparator module 3
With addition weight calibration module 2；Multichannel differential signal is carried out amplitude detection and phase-detection by addition weight calibration module 2 respectively
After obtain current modifying signal and output this to adder Module 1；Adder Module 1 is more under the control of current modifying signal
The amplitude equiphase interval multichannel differential signal such as obtain after the result that secondary adjustment I roads signal is added with Q roads signal phase and export
To comparator module 3；Comparator module 3 will export comparative result to digital coding module after input signal progress phase bit comparison
4；Digital coding module 4 is exported to serioparallel exchange module 5 after changing the data format of comparative result；Serioparallel exchange module 5 will turn
The comparative result for changing data format carries out parallel processing and obtained after multidiameter delay data signal through Low Voltage Differential Signal sending module 6
Signal is sent.
Wherein, addition weight calibration module 2 includes error voltage detection circuit 7 and quiescent current adjustment circuit 8, wherein,
Error voltage detection circuit 7 is used for the amplitude and phase for detecting the output signal of adder Module 1, and testing result is formed into error control
Signal processed is sent into quiescent current adjustment circuit 8；Quiescent current adjustment circuit 8 adjusts according to error controling signal output current to be believed
Number, the current modifying signal is used for the operating current for adjusting adder Module 1.
The present invention the advantages of comparing technical background is：
After the improvement input application that the phase quantization analog-digital converter (ADC) that the present invention is developed is calibrated through addition weight,
Existing analog-digital converter before relatively, the difference for eliminating the non-linear amplitude weight between out of phase of adder circuit introduce
Phase error, improve the output characteristics of phase quantization analog-digital converter circuit, greatly improve in high accuracy and high workload
The service behaviour of circuit under frequency condition.
Brief description of the drawings
The structural representation of the existing digital radiofrequency memory chips of Fig. 1；
The existing phase quantization analog-digital converter circuit structural representations of Fig. 2；
The phase quantization analog-digital converter circuit structural representation with the calibration of addition weight of Fig. 3 present invention；
The addition weight calibration module structural representation of Fig. 4 present invention.
Embodiment
In order that the purpose of the present invention, technical scheme and applicating superiority are more clearly understood, below in conjunction with the accompanying drawings to this
The embodiment of invention is described in further detail.
Existing phase quantization analog-digital converter circuit with reference to shown in Fig. 2, IQ input signals pass through adder Module 1
Afterwards, the range signal that multichannel carries out of phase information can be produced, which determines the output result of comparator module 3.Work as phase
, it is necessary to which more adder Module 1 extracts the phase information of input signal when quantified precision rises, and different phase informations
Between corresponding amplitude information have differences, this species diversity if without calibration if be sent directly into comparator module 1,
The dutycycle of the output signal of comparator module 3 will necessarily be reduced.Simultaneously when the operating rate of circuit rises, adder Module 1
Nonlinear characteristic tend to be obvious, output result can produce a certain degree of distortion, lose phase entrained in original signal
Information, deteriorate the output result of integrated circuit.
As shown in Figure 3 and Figure 4, be the present invention innovation improvement phase quantization analog-digital converter circuit structural representation and its
Addition weight calibration circuit is preferable to carry out schematic diagram.The phase quantization analog-digital converter circuit of the present invention includes：Adder mould
Block 1, addition weight calibration module 2, comparator module 3, digital coding module 4, serioparallel exchange module 5 and low-voltage differential signal
Sending module 6, wherein addition weight calibration module 2 are made up of error voltage detection circuit 7 and quiescent current adjustment circuit 8.
Its basic functional principle is identical with existing phase quantization analog-digital converter circuit, has elaborated above, here just not superfluous
State.And as this paper character of innovation, added between adder Module 1 and comparator module 3 and electricity is detected by error voltage
The addition weight calibration module 2 that road 7 and quiescent current adjustment circuit 8 form, the different phases exported by detecting adder Module 1
The amplitude information of interdigit eliminates due to the difference of the non-linear amplitude weight between out of phase of adder Module 1, reduction amount
Change the bit error rate of output, service behaviour of the lifting circuit under high accuracy and senior engineer's working frequency.
Adder multipath output signals are introduced into error voltage detection circuit 7 in this paper design, the circuit is simultaneously right
The amplitude information of multichannel input signal is monitored, if difference and distortion occurs in the amplitude information of multichannel input signal, by mistake
Potential difference detection circuit 7 can produce an adjustment signal and be sent into quiescent current adjustment circuit 8, and the circuit can believe this adjustment
Number it is identified and converts, and then the operating current of adder Module 1 is adjusted by quiescent current adjustment circuit 8, eliminates
The shadow that the range error that the non-linear amplitude weight difference between out of phase of adder Module 1 introduces is brought to late-class circuit
Ring.
The calibration circuit to the quantified precision of phase quantization analog to digital conversion circuit and operating rate be substantially improved by compared with
It is big to help, and the calibration circuit structure is simple, it is not necessary to and other circuits carry out external bias, meanwhile, the circuit will not be to base
This sample circuit, which introduces, quantifies deviation, ensures the output characteristics of phase quantization analog to digital conversion circuit conscientiously.
Described above in association with the embodiment of accompanying drawing, it is intended to readily appreciate the innovation essence of the present invention, but not limited with this
The embodiment of its versatility processed and the claims of requirement.In every case the present invention is understood, and according to above-mentioned reality
The equivalent structure change or component for applying example progress are replaced, and can be realized the design of identical purpose and effect, are regarded as special to this
The infringement of profit application protection content.
Claims (1)
1. a kind of phase quantization analog-digital converter circuit with the calibration of addition weight, including adder Module (1), comparator module
(3), digital coding module (4), serioparallel exchange module (5), it is characterised in that：Also include addition weight calibration module (2) and low
Voltage differential signal sending module (6), adder Module (1) receives I road signals and Q roads signal, by I roads signal and Q roads signal
Multichannel differential signal is obtained after carrying out phase addition, multichannel differential signal is respectively outputted to comparator module (3) and addition is weighed
Recalibration module (2)；Addition weight calibration module (2) obtains after multichannel differential signal to be carried out to amplitude detection and phase-detection respectively
To current modifying signal and output this to adder Module (1)；Adder Module (1) is more under the control of current modifying signal
The amplitude equiphase interval multichannel differential signal such as obtain after the result that secondary adjustment I roads signal is added with Q roads signal phase and export
To comparator module (3)；Comparator module (3) will export comparative result to digital coding after input signal progress phase bit comparison
Module (4)；Exported after the data format of digital coding module (4) conversion comparative result to serioparallel exchange module (5)；Serioparallel exchange
The comparative result of change data form is carried out parallel processing and obtains through low-voltage differential believing after multidiameter delay data signal by module (5)
Number sending module (6) sends signal；Wherein, described addition weight calibration module (2) includes error voltage detection electricity
Road (7) and quiescent current adjustment circuit (8), wherein, error voltage detection circuit (7) is used to detect adder Module (1) output
The amplitude and phase of signal, testing result is formed into error controling signal and is sent into quiescent current adjustment circuit (8)；Quiescent current is adjusted
Whole circuit (8) adjusts signal according to error controling signal output current, and the current modifying signal is used to adjust adder Module (1)
Operating current.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510481118.5A CN105071808B (en) | 2015-08-07 | 2015-08-07 | A kind of phase quantization analog-digital converter circuit with the calibration of addition weight |
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| CN201510481118.5A CN105071808B (en) | 2015-08-07 | 2015-08-07 | A kind of phase quantization analog-digital converter circuit with the calibration of addition weight |
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| CN105071808B true CN105071808B (en) | 2018-02-06 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105763195B (en) * | 2016-02-25 | 2018-12-14 | 中国电子科技集团公司第五十四研究所 | A kind of phase quantization analog-digital converter circuit |
| US10574247B1 (en) * | 2018-09-14 | 2020-02-25 | Analog Devices Global Unlimited Company | Digital-to-analog converter transfer function modification |
| CN109490839B (en) * | 2018-10-29 | 2022-11-22 | 北京遥感设备研究所 | Temperature feedback phase correction circuit and method |
| CN113496274A (en) * | 2020-03-20 | 2021-10-12 | 郑桂忠 | Quantification method and system based on operation circuit architecture in memory |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1080796A (en) * | 1993-06-24 | 1994-01-12 | 周国富 | Phase quantization A/D conversion method and device thereof |
| CN103178850A (en) * | 2013-03-06 | 2013-06-26 | 南京国博电子有限公司 | Circuit structure of 4bit phase quantization analog-to-digital converter |
-
2015
- 2015-08-07 CN CN201510481118.5A patent/CN105071808B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1080796A (en) * | 1993-06-24 | 1994-01-12 | 周国富 | Phase quantization A/D conversion method and device thereof |
| CN103178850A (en) * | 2013-03-06 | 2013-06-26 | 南京国博电子有限公司 | Circuit structure of 4bit phase quantization analog-to-digital converter |
Non-Patent Citations (3)
| Title |
|---|
| 3.4GS/s 3 Bit Phase Digitizing ADC and DAC for DRFM;Min Zhang 等;《ASICON 09,IEEE 8th International Conference on》;20091211;第226-229页 * |
| 4bit相位量化ADC设计与实现;张敏 等;《固体电子学研究与进展》;20140625;第34卷(第3期);第206-210页 * |
| 一种4 bit 相位量化ADC电路分析;邹振杰 等;《综合电子信息技术》;20111218;第37卷(第6期);第40-42页 * |
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