CN105070702B - Promote the chip DRAM pad arrangement structure of encapsulation compatibility - Google Patents
Promote the chip DRAM pad arrangement structure of encapsulation compatibility Download PDFInfo
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- CN105070702B CN105070702B CN201510564604.3A CN201510564604A CN105070702B CN 105070702 B CN105070702 B CN 105070702B CN 201510564604 A CN201510564604 A CN 201510564604A CN 105070702 B CN105070702 B CN 105070702B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Semiconductor Memories (AREA)
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Abstract
The present invention discloses a kind of chip DRAM pad arrangement structure for promoting encapsulation compatibility, the DRAM pad of chip includes multiple first pads, multiple second pads and multiple third pads, multiple first pads are alternatively arranged to form interior row's pad group, multiple second pads are alternatively arranged to form middle row's pad group, multiple third pads are alternatively arranged to form outlet pad group, interior row's pad group is located between the center of chip and middle row's pad group, middle row's pad group is between interior row's pad group and outlet pad group, and outlet pad group is between middle row's pad group and the boundary of chip.The chip DRAM pad arrangement structure of above-mentioned promotion encapsulation compatibility, compatibility is strong, without packaging cost is increased, can meet the routing requirement of the frames class wrapper such as WB BGA package and eLQFP simultaneously.
Description
Technical field
The present invention relates to chip encapsulation technology field more particularly to a kind of chip DRAM pad rows for promoting encapsulation compatibility
Cloth structure.
Background technique
Present electronic system Market competition, how fast responding market demand, export lower-cost electronic product,
An important factor for as competition is won.For a user, it would be desirable to buy the high product of cost performance for meeting actual demand.It is right
For planner, it can be directed to the user demand of high-order, scala media and low order respectively, the products scheme of customization, Jiang Nengti are provided
High profit on sales simultaneously reduces production development cost.For AP (Application Processor, application processor) manufacturer
Speech can release compatible strong, stable IC (Integrated circuit, integrated circuit) design, will shorten exploitation week
Phase reduces design cost, improves benefit.
The chip package of mainstream has BGA (Ball Grid Array, ball-like pins Background Grid array packages) class, frame at present
Class (such as eLQFP (Exposed Pad Low-profile Quad Flat Package, the exposed slim quad flat envelope of carrier
Dress) etc.), and it is based on the SIP (System of DRAM (Dynamic Random Access Memory, dynamic RAM)
In a Package, system in package) class these three.Existing chip bonding pad arrangement design generally only takes into account single kind of support
Chip package.The key point of chip package compatible design is that chip bonding pad designs, and existing is supported the weldering of one chip encapsulation
Disk designs so that SIP design and the compatibility of single-chip package design are lower.
Summary of the invention
Based on this, it is necessary to provide a kind of chip DRAM pad arrangement structure for promoting encapsulation compatibility, meet a variety of masters
Flow the compatibility requirement of chip package.
A kind of chip DRAM pad arrangement structure promoting encapsulation compatibility, the DRAM pad of chip include multiple first welderings
Disk, multiple second pads and multiple third pads, the multiple first pad is alternatively arranged to form interior row's pad group, the multiple
Second pad is alternatively arranged to form middle row's pad group, and the multiple third pad is alternatively arranged to form outlet pad group, described interior
Row's pad group is located between the center of the chip and middle row's pad group, and middle row's pad group is located at the interior row
Between pad group and the outlet pad group, the outlet pad group be located at middle row's pad group and the chip boundary it
Between.
First pad is shifted to install with second pad in one of the embodiments, second pad with
The third pad shifts to install.
Interior row's pad group includes DRAM power pad and earth signal pad in one of the embodiments, it is described in
Row's pad group includes the data pads of DRAM and control signal pad, the outlet pad group include and interior row's pad group phase
Same DRAM power pad and earth signal pad.
The fringe region of the chip is arranged in the DRAM pad in one of the embodiments,.
The DRAM pad of the chip is L-shaped in one of the embodiments, is arranged on the chip.
Interior row's pad group, middle row's pad group and the outlet pad group are opposite in one of the embodiments,
The part answered is arranged in parallel.
The DRAM pad of chip is arranged on the chip in "-" type in one of the embodiments,.
Interior row's pad group, middle row's pad group and the outlet pad group are mutual in one of the embodiments,
It is arranged in parallel.
The DRAM pad of chip is arranged on the chip in both sides type in one of the embodiments,.
Interior row's pad group, middle row's pad group and the outlet pad group are mutual in one of the embodiments,
It is arranged in parallel.
The chip DRAM pad arrangement structure of above-mentioned promotion encapsulation compatibility, the DRAM pad of chip include multiple first welderings
Disk, multiple second pads and multiple third pads, multiple first pads are alternatively arranged to form interior row's pad group, multiple second pads
It is alternatively arranged and to form middle row's pad group and multiple third pads are alternatively arranged to form outlet pad group, interior row's pad group is located at chip
Center and middle row's pad group between, middle row's pad group is between interior row's pad group and outlet pad group, outlet pad
Group is between middle row's pad group and chip boundary, so that the difficulty of DRAM substrate layout and ball distribution when WB BGA package designs
Spend lower, and NC (No Connected is not connected to) pin when eLQFP encapsulation design is less, and compatibility is strong, can expire simultaneously
The routing requirement of the frames class wrapper such as sufficient WB BGA package and eLQFP.
Detailed description of the invention
Fig. 1 is the schematic diagram of chip DRAM pad arrangement structure one embodiment that the present invention promotes encapsulation compatibility；Figure
In, G1 indicates that Group 1, G2 indicate that Group 2, G3 indicate Group 3；
Fig. 2 is that the present invention promotes the WB BGA envelope encapsulated in compatible chip DRAM pad arrangement structure one embodiment
The partial schematic diagram of dress；In figure, G1 indicates that Group 1, G2 indicate that Group 2, G3 indicate that Group 3, BALL indicate WB BGA
Packaging pin (being indicated in figure with dashed circle), two straight lines are the segment boundary of chip package；
Fig. 3 is that the present invention promotes the DDR2 SIP encapsulated in compatible chip DRAM pad arrangement structure one embodiment
The side view that eLQFP 128 is encapsulated；In figure, DIE indicates chip, and DDR2 indicates DRAM KGD, and (Known Good Die, non-defective unit are brilliant
Grain), GND indicates that the earth signal of encapsulation, PIN indicate packaging pin；
Fig. 4 is that the present invention promotes the DDR2 SIP encapsulated in compatible chip DRAM pad arrangement structure one embodiment
The top view and pad schematic diagram that eLQFP 128 is encapsulated.
Specific embodiment
To make the objectives, technical solutions, and advantages of the present invention more comprehensible, the present invention is promoted below in conjunction with attached drawing
The chip DRAM pad arrangement structure and specific embodiment for encapsulating compatibility are illustrated.It should be appreciated that described herein
Specific embodiment is only used to explain the present invention, is not intended to limit the present invention.
The present invention is directed to actual IPC (IP Camera, web camera) market demand, proposes a solution, full
It is enough lower demand:
Chip design is able to satisfy WB BGA package scheme, provides a global function product for scala media and low order client；
(second generation double data rate is synchronous dynamic with the DDR2 of two difference DRAM manufacturers for satisfaction simultaneously for the design of same chip
State random access memory) KGD carries out the eLQFP 128 of SIP design and encapsulates design, i.e., one is provided for the ultimate attainment type client of cost
A lower-cost product.
SIP due to being related to DDR2 is designed, but also must be compatible with Liang Jia DRAM manufacturer, and in general various manufacturers
DDR2 pad arrangement sequence it is not exactly the same, while DRAM substrate layout and pin row when needing to consider WB BGA package
Cloth, therefore the DRAM pad design of chip just becomes the principal element of whole system design, and to also need to meet DRAM steady for product
Demand in qualitative and speed.
Referring to Fig. 1, in one embodiment, a kind of chip DRAM pad arrangement structure for promoting encapsulation compatibility is provided,
The DRAM pad of chip may include multiple first pads 100, multiple second pads 200 and multiple third pads 300.Wherein,
Multiple first pads 100 are alternatively arranged to form interior row's pad group G1, and multiple second pads 200 are alternatively arranged to form middle row's pad group
G2, multiple third pads 300 are alternatively arranged to form outlet pad group G3.Specifically, interior row's pad group G1 includes the power supply of DRAM
Pad and earth signal pad.Middle row's pad group G2 includes the data pads and control signal pad of DRAM.Outlet pad group G3 packet
The power pad and earth signal pad of DRAM are included, and outlet pad group G3 circuit implementations and interior row's pad group G1 circuit are realized
Mode is identical.
Interior row's pad group G1 is located between the center of chip and middle row's pad group G2, and middle row's pad group G2 is located at interior row
Between pad group G1 and outlet pad group G3, outlet pad group G3 is between middle row's pad group G2 and chip boundary.Interior row's weldering
The arrangement of disk group G1, middle row's pad group G2 and outlet pad group G3 are from the direction that chip edge is directed toward in chip center position, shape
At three layers.Also, interior row's pad group G1 and middle row's pad group G2 is in staggered pattern, middle row's pad group G2 and outlet pad group
G3 is also at staggered pattern, and interior row's pad group G1 and the outlet pad position group G3 correspond.Referring to Fig. 1, the first pad
100 and second pad 200 shift to install, the second pad 200 and third pad 300 shift to install.The DRAM pad of chip is arranged
In the fringe region of chip, facilitate routing.
The design of said chip DRAM pad arrangement has following several flexible processing modes to mainstream encapsulation design:
The part DRAM is designed for WB BGA package, it can a centering row pad group G2 and outlet pad group G3 progress routing
Design.Outlet pad group G3 is due to being power supply and earth signal pad, using the routing mode of low bank.Middle row's pad group G2
It is that data and control signal pad are not intersected using the routing mode of high bank with low bank, guarantees to send out when encapsulation production
Raw short circuit phenomenon.
For DRAM SIP frame class wrapper design, generally if desired with the KGD of DRAM carry out SIP design when, DRAM
KGD, which is generally required, does one layer of RDL layer (Redistribution Layer reroutes layer), and the number of DRAM KGD is adjusted with this
It is convenient to carry out routing connection with chip DRAM pad according to, the pad arrangement of control and power ground.At this point it is possible to arrange weldering in
Disk group G2 and interior row's pad group G1 carries out height arc routing with DRAM KGD and connect.Middle row's pad group G2 uses low bank, with
DRAM KGD carries out data and connects with the routing for controlling signal.Interior row's pad group G1 uses high bank, can regard actual needs, directly
It takes on line to packaging pin, or carries out routing connection with DRAM KGD.
For there was only the design of the frame class wrapper of chip, similar processing side is designed with WB BGA package then can take
Formula completes encapsulation design only with the mode of interior row and outlet pad group routing.
Below by way of specific package example, chip DRAM pad arrangement structure of the present invention is described in detail.
Package example needs to realize that the same chip is not only compatible with WB BGA package, but also the eLQFP 128 of compatible DDR2 SIP
Frame class wrapper.
WB BGA package to be designed, power supply and ground pin are generally placed in package center position, and signal pins are placed in periphery,
To facilitate pcb board cabling and heat dissipation.As shown in Fig. 2, outlet pad group G3 beats the power supply that low bank is connected to package center position
With ground pin (packaging pin that center BALL, BALL are WB BGA), middle row's pad group G2 beats high bank and is connected to encapsulation periphery
The signal pins (peripheral BALL) of position.And interior row's pad group G1 not routing.Due to there was only two kinds of banks of height, for encapsulating factory
Production is easy to control production technology when to encapsulation plastic packaging, and routing cost is lower.
Referring to Fig. 3 and Fig. 4, for the design that the eLQFP 128 based on DDR2SIP is encapsulated, DDR2 KGD is using increase by one
The mode and chip of layer RDL routing layer take mounted on top, and the 45 degree of angles that are staggered (guarantee that the pad of DDR2 KGD is not hidden
Mode firmly) is packaged design.DDR2 KGD is placed in lower section, and chip is placed in top.Middle row's pad group G2 beats low bank
It is attached with the data and control signal of DDR2 KGD, interior row's pad group G1 is directly connected to encapsulation by way of high bank
On pin PIN, and it is connected on GND EPAD (Ground Exposed PAD open ground pad).The earth signal of DDR2 KGD
Pad is also directly beaten on high bank or low bank to packaging pin PIN or on GND EPAD.Pass through the intersection of height bank
It uses, the production process for encapsulating difficulty of chip can also equally reduced, and reduce routing cost, improve production yield.
Three row's arrangement of chip DRAM pad in the present embodiment has already passed through actual consumer product production volume production and tests
Card, the same chip have been compatible with 128 frame clsss of SIP eLQFP of single-chip WB BGA package and Liang Jia DDR2 manufacturer respectively
Three kinds of packing forms altogether, and encapsulation performance reaches market expectations requirement.
In addition, the DRAM pad of chip is L-shaped to be arranged on chip, interior row's pad group G1, middle row's pad in the present embodiment
Group G2 and the corresponding part outlet pad group G3 are arranged in parallel, are more convenient wire-bonding package.In other embodiments, chip
DRAM pad can also be arranged on chip in "-" type, interior row's pad group G1, middle row's pad group G2 and outlet pad group G3 phase
It is mutually arranged in parallel, to facilitate wire-bonding package."-" type is that four fringe regions of chip are arranged in wherein in the DRAM pad of chip
One fringe region.In another embodiment, the DRAM pad of chip can also be arranged on chip in both sides type, interior row's weldering
Disk group G1, middle row's pad group G2 and outlet pad group G3 are arranged in parallel, to facilitate wire-bonding package.Both sides type is chip
The opposite fringe region of two of them of four fringe regions of chip is arranged in DRAM pad.
The chip DRAM pad of above-mentioned promotion encapsulation compatibility, the DRAM pad of chip includes multiple first pads 100, more
A second pad 200 and multiple third pads 300, multiple first pads 100 are alternatively arranged to form interior row's pad group G1, Duo Ge
Two pads 200 are alternatively arranged to form middle row's pad group G2, and multiple third pads 300 are alternatively arranged to form outlet pad group G3, interior
Row pad group G1 be located between the center of chip and middle row's pad group G2, middle row's pad group G2 be located at interior row's pad group G1 with
Between outlet pad group G3, so that the difficulty of DRAM substrate layout and ball distribution when WB BGA package designs is lower, and eLQFP
NC (No Connected is not connected to) pin when encapsulation design is less, and circuit design is simple, and compatibility is strong, can meet simultaneously
The routing requirement of the frames class wrapper such as WB BGA package and eLQFP.And do not increase package area, also do not increase additionally and is packaged into
This, nor affects on user's pcb board wires design.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
Limitations on the scope of the patent of the present invention therefore cannot be interpreted as.It should be pointed out that for those of ordinary skill in the art
For, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to guarantor of the invention
Protect range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (9)
1. a kind of chip DRAM pad arrangement structure for promoting encapsulation compatibility, which is characterized in that the DRAM pad of chip includes
Multiple first pads, multiple second pads and multiple third pads, the multiple first pad are alternatively arranged to form interior row's pad
Group, the multiple second pad are alternatively arranged to form middle row's pad group, and the multiple third pad is alternatively arranged to form outlet weldering
Disk group, interior row's pad group are located between the center of the chip and middle row's pad group, middle row's pad group
Between interior row's pad group and the outlet pad group, the outlet pad group be located at middle row's pad group with it is described
Between the boundary of chip；
Interior row's pad group includes DRAM power pad and earth signal pad, and middle row's pad group includes the data weldering of DRAM
Disk and control signal pad, the outlet pad group include that DRAM power pad identical with interior row's pad group and ground are believed
Number pad；
The chip DRAM pad arrangement structure is used for WB BGA package or DRAM SIP frame class wrapper, or only chip
Frame class wrapper.
2. the chip DRAM pad arrangement structure according to claim 1 for promoting encapsulation compatibility, which is characterized in that described
First pad is shifted to install with second pad, and second pad is shifted to install with the third pad.
3. the chip DRAM pad arrangement structure as claimed in any of claims 1 to 2 for promoting encapsulation compatibility,
It is characterized in that, the fringe region of the chip is arranged in the DRAM pad of the chip.
4. the chip DRAM pad arrangement structure according to claim 3 for promoting encapsulation compatibility, which is characterized in that described
The DRAM pad of chip is L-shaped to be arranged on master control DIE.
5. the chip DRAM pad arrangement structure according to claim 4 for promoting encapsulation compatibility, which is characterized in that described
Interior row's pad group, middle row's pad group and the corresponding part of the outlet pad group are arranged in parallel.
6. the chip DRAM pad arrangement structure according to claim 3 for promoting encapsulation compatibility, which is characterized in that described
The DRAM pad of chip is arranged on the chip in "-" type.
7. the chip DRAM pad arrangement structure according to claim 6 for promoting encapsulation compatibility, which is characterized in that described
Interior row's pad group, middle row's pad group and the outlet pad group are arranged in parallel.
8. the chip DRAM pad arrangement structure according to claim 3 for promoting encapsulation compatibility, which is characterized in that described
The DRAM pad of chip is arranged on the chip in both sides type.
9. the chip DRAM pad arrangement structure according to claim 8 for promoting encapsulation compatibility, which is characterized in that described
Interior row's pad group, middle row's pad group and the outlet pad group are arranged in parallel.
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| CN1094719C (en) * | 1997-08-21 | 2002-11-20 | 联华电子股份有限公司 | Storage module capable of repairing and maintaining and method for repairing and maintaining same |
| CN1411061A (en) * | 2001-09-27 | 2003-04-16 | 联华电子股份有限公司 | Dynamic random access memory module package |
| CN1195323C (en) * | 2001-11-05 | 2005-03-30 | 扬智科技股份有限公司 | Package structure of chip with pad array |
| US20100283141A1 (en) * | 2009-05-11 | 2010-11-11 | Chun-Wei Chang | Semiconductor chip package |
| CN203882997U (en) * | 2014-05-28 | 2014-10-15 | 展讯通信（上海）有限公司 | Circuit structure capable enabling occupied space reduction of external capacitor of chip |
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