CN105070265A - Liquid crystal display and multi-channel distributor control circuit - Google Patents
Liquid crystal display and multi-channel distributor control circuit Download PDFInfo
- Publication number
- CN105070265A CN105070265A CN201510572122.2A CN201510572122A CN105070265A CN 105070265 A CN105070265 A CN 105070265A CN 201510572122 A CN201510572122 A CN 201510572122A CN 105070265 A CN105070265 A CN 105070265A
- Authority
- CN
- China
- Prior art keywords
- type tft
- demultplexer
- control
- liquid crystal
- crystal display
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Liquid Crystal Display Device Control (AREA)
- Liquid Crystal (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides a multi-channel distributor control circuit of a liquid crystal display. The multi-channel distributor control circuit includes a control unit and a multi-channel distributor which is electrically connected with the control unit; the multi-channel distributor includes transmission gates; and array testing is performed on the liquid crystal display, the control unit provides control signals for the multi-channel distributor, so that the transmission gates of the multi-channel distributor can be switched on and switched off successively under control. The invention also provides a liquid crystal display with the multi-channel distributor control circuit. With the multi-channel distributor control circuit and the liquid crystal display with the multi-channel distributor control circuit of the invention adopted, the width of the frame of a display panel can be the effectively reduced. After the liquid crystal display performs normal display, the transmission gates of the multi-channel distributor are all in a switched-off state, and therefore, on the one hand, the load force of the multi-channel distributor can be decreased, and on the other hand, the risk of the lead of electrostatic discharge into signal ends can be decreased.
Description
Technical field
The present invention relates to field of liquid crystal display, especially relate to a kind of demultplexer control circuit and a kind of liquid crystal display with this demultplexer.
Background technology
Existing display panel such as mobile phone display panel, computer display panel etc., when manufacturing and designing, can reserve array test usually.Refer to Fig. 1, Fig. 1 is the plane cabling schematic diagram of existing liquid crystal display, concrete method of testing is, one group of test pad 61 is set in the side of display panel 60, when then normally being shown by described display panel 60, required signal is provided to this display panel 60, to test by described test pad 61 by external mode.Above-mentioned display panel 60 also comprises setting integrated circuit 63 in the inner and demultplexer (not shown).This demultplexer is connected with test pad 61 respectively by second group of cabling B of the first group of cabling A the being positioned at display panel 60 side opposite side relative with being positioned at display panel 60.This first group of cabling A and second group cabling B is used for when carrying out array test, provides control signal, closed by its transmission gate to demultplexer, prevents it from electric leakage occurring and affects the effect of array test.
Wherein, if this demultplexer just adopts N-type TFT (ThinFilmTransistor, thin film transistor (TFT)) or P type TFT as transmission gate, then extraction 3 circuits are needed respectively.If this demultplexer adopts N-type TFT and P type TFT as transmission gate simultaneously, then need extraction 6 circuits.Thus, not only add the complexity of wiring, but also need to reserve the space holding this circuit in the relative both sides of this display panel 60, and cause the border width of described display panel 60 both sides to increase to a certain extent.Meanwhile, when this display panel 60 normally shows, this part circuit can increase the load force of this demultplexer, and especially for the display panel 60 of ultrahigh resolution, its impact can be more serious.
Summary of the invention
The invention provides a kind of demultplexer control circuit and have the liquid crystal display of this demultplexer, it can reduce the border width of display panel both sides, meanwhile, when display panel normally shows, reduces the load force of this demultplexer.
One aspect of the present invention provides a kind of demultplexer control circuit, the demultplexer that described demultplexer control circuit comprises control module and is electrically connected with this control module, described demultplexer comprises transmission gate, when described liquid crystal display carries out array test, described control module provides control signal to described demultplexer, with the first conducting of the transmission gate controlling described demultplexer, rear disconnection.
Wherein, described demultplexer adopts N-type TFT (ThinFilmTransistor, thin film transistor (TFT)) as transmission gate, described control module comprises the first control end, grid and described first control end of described N-type TFT are electrically connected, the drain electrode of described N-type TFT is electrically connected with the signal end of described demultplexer respectively, the source electrode of described N-type TFT is electronegative potential, when described liquid crystal display carries out array test, described first control end provides noble potential to the grid of described N-type TFT, control this N-type TFT conducting, the signal end of described demultplexer is made to be pulled down to electronegative potential, thus described N-type TFT is disconnected.
Wherein, when described liquid crystal display normally shows, described first control end provides electronegative potential to the grid of described N-type TFT, disconnects to control this N-type TFT.
Wherein, described demultplexer adopts P type TFT as transmission gate, described control module comprises the second control end, grid and described second control end of this P type TFT are electrically connected, the drain electrode of this P type TFT is electrically connected with the signal end of described demultplexer respectively, the source electrode of this P type TFT is noble potential, when described liquid crystal display carries out array test, this second control end provides electronegative potential to the grid of described P type TFT, to control this P type TFT conducting, make the signal end of described demultplexer be driven high noble potential, thus described P type TFT is disconnected.
Wherein, when described liquid crystal display normally shows, described second control end provides noble potential to the grid of described P type TFT, disconnects to control this P type TFT.
Wherein, when described demultplexer adopts N-type TFT and P type TFT as transmission gate simultaneously, described control module comprises the first control end and the second control end, wherein, grid and described first control end of described N-type TFT are electrically connected, the drain electrode of described N-type TFT is electrically connected with the signal end of described demultplexer respectively, the source electrode of described N-type TFT is electronegative potential, when described liquid crystal display carries out array test, this first control end provides noble potential to the grid of described N-type TFT, to control this N-type TFT conducting, the signal end of this demultplexer is made to be pulled down to electronegative potential, thus described N-type TFT is disconnected, grid and this second control end of described P type TFT are electrically connected, the drain electrode of described P type TFT is electrically connected with the signal end of described demultplexer respectively, the source electrode of described P type TFT is noble potential, when described liquid crystal display carries out array test, this second control end provides electronegative potential to the grid of described P type TFT, to control this P type TFT conducting, make the signal end of this demultplexer be driven high noble potential, thus described P type TFT is disconnected.
Wherein, when described liquid crystal display normally shows, described first control end provides electronegative potential to the grid of described N-type TFT, disconnects to control this N-type TFT.
Wherein, when described liquid crystal display normally shows, described second control end provides noble potential to the grid of described P type TFT, disconnects to control this P type TFT
The present invention provides a kind of liquid crystal display on the other hand, it comprises display panel and demultplexer control circuit, this display panel is provided with test pad, this demultplexer control circuit is by this test pad incoming control signal, and this demultplexer control circuit comprises above-mentioned demultplexer control circuit.
Compared to prior art, in demultplexer control circuit and the liquid crystal display of the embodiment of the present invention, not only can the complexity of simplified wiring, but also effectively can reduce the border width of display panel.Meanwhile, after liquid crystal display normally shows, the transmission gate of demultplexer is all in off-state, can reduce the load force of this demultplexer on the one hand, can reduce the risk that signal end imports static discharge on the other hand.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.
Fig. 1 is the plane cabling schematic diagram of existing liquid crystal display.
Fig. 2 is the circuit diagram of the demultplexer control circuit of embodiments of the invention.
Fig. 3 be demultplexer control circuit of the present invention when carrying out array test, the sequential chart of the control signal that the first control end provides.
Fig. 4 demultplexer control circuit of the present invention when normally showing, the sequential chart of the control signal that the first control end provides.
Fig. 5 is the circuit diagram of the demultplexer control circuit of another embodiment of the present invention.
Fig. 6 be demultplexer control circuit of the present invention when carrying out array test, the sequential chart of the control signal that the second control end provides.
Fig. 7 demultplexer control circuit of the present invention when normally showing, the sequential chart of the control signal that the second control end provides.
Fig. 8 is the circuit diagram of the demultplexer control circuit of another embodiment of the present invention.
Fig. 9 is the floor map of the liquid crystal display of embodiments of the invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
In addition, the explanation of following embodiment is with reference to additional diagram, can in order to the specific embodiment implemented in order to illustrate the present invention.The direction term mentioned in the present invention, such as, " on ", D score, "front", "rear", "left", "right", " interior ", " outward ", " side " etc., it is only the direction with reference to annexed drawings, therefore, the direction term used be in order to better, be illustrated more clearly in and understand the present invention, instead of instruction or infer the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore can not be interpreted as limitation of the present invention.
In describing the invention, it should be noted that, unless otherwise clearly defined and limited, term " installation ", " being connected ", " connection " should be interpreted broadly, and such as, can be fixedly connected with, also can be removably connect, or connect integratedly; It can be mechanical connection; Can be directly be connected, also indirectly can be connected by intermediary, can be the connection of two element internals.For the ordinary skill in the art, concrete condition above-mentioned term concrete meaning in the present invention can be understood.
In addition, in describing the invention, except as otherwise noted, the implication of " multiple " is two or more.If there is the term of " operation " in this instructions, it not only refers to independently operation, when cannot clearly distinguish with other operation, as long as the effect that can realize desired by this operation is then also included within this term.In addition, refer to by the numerical range that " ~ " represents the scope that the numerical value recorded before and after " ~ " is included as minimum value and maximal value in this instructions.In the accompanying drawings, the unit that structure is similar or identical represents with identical label.
Refer to Fig. 2, Fig. 2 is the circuit diagram of demultplexer control circuit of the present invention, and this demultplexer can be used for liquid crystal display.As shown in Figure 2, the demultplexer 30 that this demultplexer control circuit 100 comprises control module 10 and is electrical connected with this control module 10, transmission gate 31 drawn together by this demultplexer bag 30, when this liquid crystal display carries out array test, this control module 10 provides control signal to this demultplexer 30, by the first conducting of described transmission gate 31, rear disconnection.
In this preferred embodiment, this demultplexer 30 adopts N-type TFT (ThinFilmTransistor, thin film transistor (TFT)) as transmission gate 31, and this control module 10 comprises the first control end Control-N.The grid G of this N-type TFT and this first control end Control-N are electrically connected, and its drain D is electrically connected with signal end CKHR, CKHG, CKHB of described demultplexer 30 respectively, and its source S is electronegative potential VGL.Refer to Fig. 3, Fig. 3 be demultplexer control circuit of the present invention when carrying out array test, the sequential chart of the control signal that the first control end provides.When carrying out array test, this first control end Control-N provides the grid G of noble potential VGH to this N-type TFT, then control N-type TFT conducting, make signal end CKHR, CKHG, CKHB of this demultplexer 30 be pulled down to electronegative potential VGL, thus described N-type TFT is disconnected.
Refer to Fig. 4, Fig. 4 demultplexer control circuit of the present invention when normally showing, the sequential chart of the control signal that the first control end provides.When this liquid crystal display normally shows, this first control end Control-N provides the grid G of electronegative potential VGL to this N-type TFT, controls this N-type TFT and disconnects.
Refer to figure, Fig. 5 is the circuit diagram of the demultplexer control circuit of another embodiment of the present invention.In an embodiment of the present invention, this demultplexer 50 adopts P type TFT as transmission gate, this control module 10 comprises the second control end Control-P, grid G and this second control end Control-P of this P type TFT are electrically connected, its drain D is electrically connected with signal end XCKHR, XCKHG, XCKHB of this demultplexer 50 respectively, and its source S is noble potential VGH.Refer to Fig. 6, Fig. 6 be demultplexer control circuit of the present invention when carrying out array test, the sequential chart of the control signal that the second control end provides.When carrying out array test, this second control end Control-P provides electronegative potential VGL to the grid G of this P type TFT, control this P type TFT conducting, make signal end CKHR, CKHG, CKHB of this demultplexer 50 be driven high noble potential VGH, thus P type TFT is disconnected.
Refer to Fig. 7, Fig. 7 demultplexer control circuit of the present invention when normally showing, the sequential chart of the control signal that the second control end provides.This second control end Control-P provides noble potential to the grid G of this P type TFT, controls this P type TFT and disconnects.
Refer to Fig. 8, Fig. 8 is the circuit diagram of the demultplexer control circuit of another embodiment of the present invention.In an embodiment of the present invention, this demultplexer 70 adopts N-type TFT and P type TFT as transmission gate simultaneously, this control module 10 comprises the first control end Control-N and the second control end Control-P, wherein, the grid G of this N-type TFT and this first control end Control-N are electrically connected, the drain D of this N-type TFT is electrically connected with signal end CKHR, CKHG, CKHB of demultplexer 30 respectively, and the source S of this N-type TFT is electronegative potential VGL.Refer to Fig. 3, when carrying out array test, this first control end Control-N provides the grid G of noble potential VGH to this N-type TFT, controls described N-type TFT conducting, make signal end CKHR, CKHG, CKHB of this demultplexer 30 be pulled down to electronegative potential VGL, thus N-type TFT is disconnected.Grid G and this second control end Control-P of this P type TFT are electrically connected, the drain D of this P type TFT is connected with signal end XCKHR, XCKHG, XCKHB of described demultplexer 50 respectively, the source S of this P type TFT is noble potential VGH, refer to Fig. 6, when carrying out array test, this second control end Control-P provides electronegative potential VGL to the grid G of this P type TFT, then control P type TFT conducting, make signal end CKHR, CKHG, CKHB of this demultplexer 50 be driven high noble potential VGH, thus P type TFT is disconnected.
When this liquid crystal display normally shows, this first control end Control-N provides the grid G of electronegative potential VGL to this N-type TFT, thus controls this N-type TFT and disconnect.This second control end Control-P provides noble potential to the grid G of this P type TFT, thus controls this P type TFT and disconnect.
Refer to Fig. 9, Fig. 9 is the floor map with the liquid crystal display 200 of above-mentioned demultplexer control circuit 100 of the present invention.This liquid crystal display 200 also comprise display panel 80, this display panel 80 is provided with test pad 81, and this first control end Control-N and this second control end Control-P accesses high electronegative potential by test pad 81 from outside, to carry out array test.
In sum, demultplexer control circuit 100 described in the embodiment of the present invention for adopt N-type TFT or P type TFT as transmission gate 31,51 demultplexer 30,50 for, only need 1 cabling, for adopt simultaneously N-type TFT and P type TFT as transmission gate 71 demultplexer 70 for, also only 2 cablings are needed, thus not only can the complexity of simplified wiring, but also effectively can reduce the border width of display panel 80.Simultaneously, after liquid crystal display 200 normally display, signal end CKHR, CKHG, CKHB, XCKHR, XCKHG, XCKHB of demultplexer 30,50 and 70 are in off-state, the load force of this demultplexer 30,50 and 70 can be reduced on the one hand, the risk that signal end CKHR, CKHG, CKHB, XCKHR, XCKHG, XCKHB import static discharge can be reduced on the other hand.
In the description of this instructions, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, identical embodiment or example are not necessarily referred to the schematic representation of above-mentioned term.And the specific features of description, structure, material or feature can combine in an appropriate manner in any one or more embodiment or example.
Above disclosedly be only a kind of preferred embodiment of the present invention, certainly the interest field of the present invention can not be limited with this, one of ordinary skill in the art will appreciate that all or part of flow process realizing above-described embodiment, and according to the equivalent variations that the claims in the present invention are done, still belong to the scope that invention is contained.
Claims (9)
1. the demultplexer control circuit for liquid crystal display, it is characterized in that, the demultplexer that described demultplexer control circuit comprises control module and is electrically connected with this control module, described demultplexer comprises transmission gate, when described liquid crystal display carries out array test, described control module provides control signal to described demultplexer, with the first conducting of the transmission gate controlling described demultplexer, and rear disconnection.
2. demultplexer control circuit as claimed in claim 1, it is characterized in that, described demultplexer adopts N-type TFT (ThinFilmTransistor, thin film transistor (TFT)) as transmission gate, described control module comprises the first control end, grid and described first control end of described N-type TFT are electrically connected, the drain electrode of described N-type TFT is electrically connected with the signal end of described demultplexer respectively, the source electrode of described N-type TFT is electronegative potential, when described liquid crystal display carries out array test, described first control end provides noble potential to the grid of described N-type TFT, control this N-type TFT conducting, the signal end of described demultplexer is made to be pulled down to electronegative potential, thus described N-type TFT is disconnected.
3. demultplexer control circuit as claimed in claim 2, is characterized in that, when described liquid crystal display normally shows, described first control end provides electronegative potential to the grid of described N-type TFT, disconnects to control this N-type TFT.
4. demultplexer control circuit as claimed in claim 1, it is characterized in that, described demultplexer adopts P type TFT as transmission gate, described control module comprises the second control end, grid and described second control end of this P type TFT are electrically connected, the drain electrode of this P type TFT is electrically connected with the signal end of described demultplexer respectively, the source electrode of this P type TFT is noble potential, when described liquid crystal display carries out array test, this second control end provides electronegative potential to the grid of described P type TFT, to control this P type TFT conducting, the signal end of described demultplexer is made to be driven high noble potential, thus described P type TFT is disconnected.
5. demultplexer control circuit according to claim 2, is characterized in that, when described liquid crystal display normally shows, described second control end provides noble potential to the grid of described P type TFT, disconnects to control this P type TFT.
6. demultplexer control circuit as claimed in claim 1, it is characterized in that, when described demultplexer adopts N-type TFT and P type TFT as transmission gate simultaneously, described control module comprises the first control end and the second control end, wherein, grid and described first control end of described N-type TFT are electrically connected, the drain electrode of described N-type TFT is electrically connected with the signal end of described demultplexer respectively, the source electrode of described N-type TFT is electronegative potential, when described liquid crystal display carries out array test, this first control end provides noble potential to the grid of described N-type TFT, to control this N-type TFT conducting, the signal end of this demultplexer is made to be pulled down to electronegative potential, thus described N-type TFT is disconnected, grid and this second control end of described P type TFT are electrically connected, the drain electrode of described P type TFT is electrically connected with the signal end of described demultplexer respectively, the source electrode of described P type TFT is noble potential, when described liquid crystal display carries out array test, this second control end provides electronegative potential to the grid of described P type TFT, to control this P type TFT conducting, make the signal end of this demultplexer be driven high noble potential, thus described P type TFT is disconnected.
7. demultplexer control circuit according to claim 6, is characterized in that, when described liquid crystal display normally shows, described first control end provides electronegative potential to the grid of described N-type TFT, disconnects to control this N-type TFT.
8. demultplexer control circuit according to claim 6, is characterized in that, when described liquid crystal display normally shows, described second control end provides noble potential to the grid of described P type TFT, disconnects to control this P type TFT.
9. a liquid crystal display, it comprises display panel and demultplexer control circuit, described display panel is provided with test pad, described demultplexer control circuit is by described test pad incoming control signal, it is characterized in that, described demultplexer control circuit comprises the demultplexer control circuit in claim 1-8 item described in any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510572122.2A CN105070265B (en) | 2015-09-09 | 2015-09-09 | Liquid crystal display and its demultplexer control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510572122.2A CN105070265B (en) | 2015-09-09 | 2015-09-09 | Liquid crystal display and its demultplexer control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105070265A true CN105070265A (en) | 2015-11-18 |
| CN105070265B CN105070265B (en) | 2017-12-08 |
Family
ID=54499618
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510572122.2A Active CN105070265B (en) | 2015-09-09 | 2015-09-09 | Liquid crystal display and its demultplexer control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105070265B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070080913A1 (en) * | 2005-10-12 | 2007-04-12 | Samsung Electronics Co., Ltd. | Display device and testing method for display device |
| CN101114414A (en) * | 2006-07-27 | 2008-01-30 | 三星电子株式会社 | Driving apparatus for display device and display device including the same |
| CN104217672A (en) * | 2013-05-31 | 2014-12-17 | 三星显示有限公司 | Organic light emitting display panel |
| CN104217671A (en) * | 2013-06-03 | 2014-12-17 | 三星显示有限公司 | Organic light emitting display panel |
| CN104867430A (en) * | 2014-02-25 | 2015-08-26 | 三星显示有限公司 | Display apparatus |
-
2015
- 2015-09-09 CN CN201510572122.2A patent/CN105070265B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070080913A1 (en) * | 2005-10-12 | 2007-04-12 | Samsung Electronics Co., Ltd. | Display device and testing method for display device |
| CN101114414A (en) * | 2006-07-27 | 2008-01-30 | 三星电子株式会社 | Driving apparatus for display device and display device including the same |
| CN104217672A (en) * | 2013-05-31 | 2014-12-17 | 三星显示有限公司 | Organic light emitting display panel |
| CN104217671A (en) * | 2013-06-03 | 2014-12-17 | 三星显示有限公司 | Organic light emitting display panel |
| CN104867430A (en) * | 2014-02-25 | 2015-08-26 | 三星显示有限公司 | Display apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105070265B (en) | 2017-12-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11296125B2 (en) | Array substrate and display panel | |
| CN106842749B (en) | Liquid crystal display panel and liquid crystal display device | |
| US9470943B2 (en) | Array substrate, display panel and display device | |
| CN202736443U (en) | Display, array substrate and test circuit of array substrate | |
| US9459730B2 (en) | Shift register unit, display device and driving method | |
| CN104699347A (en) | Array substrate, display panel and electronic equipment | |
| US10102783B2 (en) | Array substrate and detecting method for an array substrate | |
| US20150077681A1 (en) | Liquid crystal display panel | |
| CN104536229A (en) | Array substrate and display panel | |
| CN105355234A (en) | Shift register | |
| CN112331118B (en) | Display panel and display device | |
| CN106873225B (en) | Array substrate, display panel, display device and array substrate driving method | |
| CN103345898B (en) | Display device | |
| CN104866158A (en) | Embedded type touch screen and display device | |
| CN103926717A (en) | Display panel, detection circuit of display panel and detection method of display panel | |
| WO2019223623A1 (en) | Display substrate, display panel and display device | |
| CN104020881A (en) | Touch display panel, driving method thereof and display device | |
| CN103149713B (en) | array panel detection circuit structure | |
| CN104280920A (en) | Touch screen integrated liquid crystal display panel and liquid crystal display device | |
| CN103869516B (en) | display panel discharge circuit and display device | |
| CN103199513B (en) | Electrostatic discharge protective circuit, display unit and electrostatic protection method | |
| CN104570417A (en) | Liquid crystal display screen and electronic equipment | |
| CN110737140A (en) | Display panel, control method thereof and display device | |
| US9842525B2 (en) | Display panel, detection circuit, and detection method thereof | |
| CN101852956A (en) | Pixel driving circuit structure with repair line |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |