CN105047126A - Control circuit, array substrate, display panel and 3D display device - Google Patents
Control circuit, array substrate, display panel and 3D display device Download PDFInfo
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- CN105047126A CN105047126A CN201510602559.6A CN201510602559A CN105047126A CN 105047126 A CN105047126 A CN 105047126A CN 201510602559 A CN201510602559 A CN 201510602559A CN 105047126 A CN105047126 A CN 105047126A
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Abstract
The invention provides a control circuit, an array substrate, a display panel and a 3D display device. The control circuit comprises a first input end, a second input end, a third input end, a fourth input end, a control unit, a first output end, a second output end, a third output end and a fourth output end. The first input end and the fourth input end are used for inputting first signals, and the second input end and the third input end are used for inputting second signals. The control unit is used for synchronously outputting the first signals to the second output end and the fourth output end and synchronously outputting the second signals to the first output end and the third output end, or synchronously outputting the first signals to the second output end and the third output end and synchronously outputting the second signals to the first output end and the fourth output end, or synchronously outputting the first signals are synchronously output to the first output end and the third output end and synchronously outputting the second signals to the second output end and the fourth output end, or synchronously outputting the first signals to the first output end and the fourth output end and synchronously outputting the second signals to the second output end and the third output end. The problem that an existing 3D display screen is high in cost is solved.
Description
Technical field
The present invention relates to luminescence display technical field, more particularly, relate to a kind of control circuit, array base palte, display panel and 3D display device.
Background technology
In the display panel of existing 3D display screen, when showing 2D effect, carrying out image data processing signal by image processing system, making the viewdata signal of adjacent lines pixel identical; When showing conventional 3D effect, carrying out image data processing signal by image processing system, make the viewdata signal of adjacent lines pixel different, and the viewdata signal of adjacent rows pixel being respectively left eye image data signal and right eye image data signal;
When showing the 3D effect that eye is followed the tracks of, for reaching best 3D display effect, the data needs of pixel adjust according to the angle of human eye and position, realize following four kinds of states: one, as shown in Figure 1a, 1st row and the 2nd row pixel input left eye data signal L, the 3rd row and the 4th row pixel input right eye data signal R, by that analogy, M+1 is capable and M+2 capable pixel input left eye data signal L, M+3 are capable and M+4 capable pixel input right eye data signal R; Two, as shown in Figure 1 b, 1st row and the 4th row pixel input right eye data signal R, the 2nd row and the 3rd row pixel input left eye data signal L, by that analogy, M+1 is capable and M+4 capable pixel input right eye data signal R, M+2 are capable and M+3 capable pixel input left eye data signal L; Three, as illustrated in figure 1 c, 1st row and the 2nd row pixel input right eye data signal R, the 3rd row and the 4th row pixel input left eye data signal L, by that analogy, M+1 is capable and M+2 capable pixel input right eye data signal R, M+3 are capable and M+4 capable pixel input left eye data signal L; Four, as shown in Figure 1 d, 1st row and the 4th row pixel are left eye data signal L, and the 2nd row and the 3rd row pixel are right eye data signal R, by that analogy, capable and the capable pixel of M+4 of M+1 is left eye data signal L, and the capable and capable pixel of M+3 of M+2 is right eye data signal R.Wherein, M is more than or equal to the integer of 1.
By image processing system, special processing is carried out to viewdata signal in prior art, realize the 3D effect that eye is followed the tracks of.But, because image processing system has the problems such as the high and software program of Driving Scheme complexity, hardware cost is complicated, therefore, can cause supporting eye to follow the tracks of the cost of the 3D display screen of 3D effect higher.
Summary of the invention
In view of this, the invention provides a kind of control circuit, array base palte, display panel and 3D display device, with the problem that the 3D display screen cost solving the tracking of existing support eye is higher.
For achieving the above object, the invention provides following technical scheme:
A kind of control circuit, comprises first input end ~ the four-input terminal, control module, the first output terminal ~ the 4th output terminal; Described first input end and four-input terminal input the first signal, described second input end and the 3rd input end input secondary signal;
Described control module is used for by described first signal synchronism output to described second output terminal and the 4th output terminal, by described secondary signal synchronism output to described first output terminal and the 3rd output terminal;
Or, by described first signal synchronism output to described second output terminal and the 3rd output terminal, by described secondary signal synchronism output to described first output terminal and the 4th output terminal;
Or, by described first signal synchronism output to described first output terminal and the 3rd output terminal, by described secondary signal synchronism output to described second output terminal and the 4th output terminal;
Or, by described first signal synchronism output to described first output terminal and the 4th output terminal, by described secondary signal synchronism output to described second output terminal and the 3rd output terminal.
A kind of array base palte, comprise multiple grid line groups, first grid driving circuit, second grid driving circuit, drive integrated circult and multiple control circuit, described control circuit is the control circuit as above described in any one;
Described grid line groups comprises the first grid polar curve, second gate line, the 3rd gate line and the 4th gate line that are arranged in order;
Described first grid driving circuit comprises multiple first grid driver element, described first grid driver element comprises the first shift register and the second shift register, described first shift register connects with corresponding described first grid polar curve, and the second shift register connects with corresponding described 3rd gate line;
Described second grid driving circuit comprises multiple second grid driver element, described second grid driver element comprises the 3rd shift register and the 4th shift register, described 3rd shift register connects with corresponding described second gate line, and described 4th shift register connects with corresponding described 4th gate line;
Described drive integrated circult comprises multiple signal line group, and described signal line group comprises the first signal wire and secondary signal line, and described first signal wire exports the first signal, and described secondary signal line exports secondary signal;
Described in each, control circuit correspondence controls the signal that described in, signal line group exports; First input end in control circuit described in each is connected with corresponding described first signal wire with four-input terminal, and the second input end is connected with corresponding described secondary signal line with the 3rd input end; First output terminal of control circuit described in each is connected with described first shift register, second output terminal is connected with described second shift register, described 3rd output terminal is connected with described 3rd shift register, and described 4th output terminal is connected with described 4th shift register;
Wherein, during 2D display, described first signal and secondary signal are identical signal; During 3D display, described first signal and secondary signal are different signals.
A kind of display panel, comprises the array base palte as above described in any one.
A kind of 3D display device, comprises display panel as above.
Compared with prior art, technical scheme provided by the present invention has the following advantages:
Control circuit provided by the present invention, array base palte, display panel and 3D display device, control circuit can by the first signal as left eye data signal synchronism output to two output terminal, by secondary signal if right eye data signal synchronism output is to two other output terminal, and by controlling the difference of output first signal and secondary signal output terminal, make the gate line in 3D display device have 4 kinds of scan modes, and then realize 4 kinds of states of eye tracking.That is, the present invention does not need to carry out special processing by image processing system to data source, 4 kinds of states of eye tracking just can be realized by means of only the output terminal difference controlling this control circuit output signal, thus the problem that the 3D display screen cost solving the tracking of existing support eye is higher.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, accompanying drawing in the following describes is only embodiments of the invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the accompanying drawing provided.
Fig. 1 a ~ Fig. 1 d is the 4 kinds of pixel status schematic diagram following the tracks of 3D effect for 3D display screen display eye;
The structural representation of the control circuit that Fig. 2 provides for the embodiment of the present invention one;
The structural representation of the control module of the control circuit that Fig. 3 provides for the embodiment of the present invention one;
The part-structure schematic diagram of the array base palte that Fig. 4 provides for the embodiment of the present invention two;
The annexation schematic diagram of the signal line group that Fig. 5 provides for the embodiment of the present invention two and shift register;
The initial sweep signal timing diagram of each gate line in the array base palte that Fig. 6 a ~ Fig. 6 d provides for the embodiment of the present invention two.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Embodiments of the invention one provide a kind of control circuit, and as shown in Figure 2, this control circuit comprises first input end IN
1, the second input end IN
2, the 3rd input end IN
3, four-input terminal IN
4, control module M, the first output terminal OUT
1, the second output terminal OUT
2, the 3rd output terminal OUT
3with the 4th output terminal OUT
4, wherein, first input end IN
1with four-input terminal IN
4input the first signal L
0, the second input end IN
2with the 3rd input end IN
3input secondary signal R
0.
Wherein, control module M is used for the first signal L
0synchronism output to the second output terminal OUT
2with the 4th output terminal OUT
4, by secondary signal R
0synchronism output to the first output terminal OUT
1with the 3rd output terminal OUT
3;
Or, by the first signal L
0synchronism output to the second output terminal OUT
2with the 3rd output terminal OUT
3, by secondary signal R
0synchronism output to the first output terminal OUT
1with the 4th output terminal OUT
4;
Or, by the first signal L
0synchronism output to the first output terminal OUT
1with the 3rd output terminal OUT
3, by secondary signal R
0synchronism output to the second output terminal OUT
2with the 4th output terminal OUT
4;
Or, by the first signal L
0synchronism output to the first output terminal OUT
1with the 4th output terminal OUT
4, by secondary signal R
0synchronism output to the second output terminal OUT
2with the 3rd output terminal OUT
3.
Control circuit in the present embodiment can be connected with the drive integrated circult in 3D display device and main control chip, and the left eye data signal that this drive integrated circult exports is as the first signal L
0input control circuit, the right eye data signal that drive integrated circult exports is as secondary signal R
0input control circuit, wherein, left eye data signal comprises left-eye image sweep signal and clock signal etc., and right eye data signal comprises eye image sweep signal and clock signal etc.
Control circuit by left eye data signal synchronism output to two output terminal, as the second output terminal OUT
2with the 4th output terminal OUT
4, by right eye data signal synchronism output to two other output terminal, as the first output terminal OUT
1with the 3rd output terminal OUT
3, and different with the synchronous output end of right eye data signal by controlling to export left eye data signal, make the gate line in 3D display device have 4 kinds of scan modes, and then realize 4 kinds of states of eye tracking, these 4 kinds of states are respectively as shown in Fig. 1 a ~ Fig. 1 d.Can be described in detail above-mentioned 4 kinds of scan modes in conjunction with the concrete structure of 3D display device in subsequent embodiment, not repeat them here.
Wherein, the synchronous output end difference controlling left eye data signal refers to and can control left eye data signal synchronism output to the second output terminal OUT
2with the 4th output terminal OUT
4, also can control left eye data signal synchronism output to the second output terminal OUT
2with the 3rd output terminal OUT
3; The synchronous output end difference controlling right eye data signal refers to and can control right eye data signal synchronism output to the first output terminal OUT
1with the 3rd output terminal OUT
3, also can control right eye data signal synchronism output to the first output terminal OUT
1with the 4th output terminal OUT
4.
In a specific embodiment of the present invention, as shown in Figure 3, control module M comprises the first switch T
1, second switch T
2, the 3rd switch T
3, the 4th switch T
4, the 5th switch T
5, the 6th switch T
6, the 7th switch T
7, the 8th switch T
8, the first control end SW
1, the second control end SW
2, the first phase inverter K
1with the second phase inverter K
2.
As shown in Figure 3, the first switch T
1first end and second switch T
2first end all with the first output terminal OUT
1connect, the first switch T
1the second end and first input end IN
1connect, the first switch T
1the 3rd end and the first control end SW
1connect, second switch T
2the second end and the 3rd input end IN
3connect, second switch T
2the 3rd end by the first phase inverter K
1with the first control end SW
1connect;
3rd switch T
3first end and the 4th switch T
4first end all with the second output terminal OUT
2connect, the 3rd switch T
3the second end and the second input end IN
2connect, the 3rd switch T
3the 3rd end and the first control end SW
1connect, the 4th switch T
4the second end and four-input terminal IN
4connect, the 4th switch T
4the 3rd end by the first phase inverter K
1with the first control end SW
1connect;
5th switch T
5first end and the 6th switch T
6first end all with the 3rd output terminal OUT
3connect, the 5th switch T
5the second end and first input end IN
1connect, the 5th switch T
5the 3rd end and the second control end SW
2connect, the 6th switch T
6the second end and the 3rd input end IN
3connect, the 6th switch T
6the 3rd end by the second phase inverter K
2with the second control end SW
2connect;
7th switch T
7first end and the 8th switch T
8first end all with the 4th output terminal OUT
4connect, the 7th switch T
7the second end and the second input end IN
2connect, the 7th switch T
7the 3rd end and the second control end SW
2connect, the 8th switch T
8the second end and four-input terminal IN
4connect, the 8th switch T
8the 3rd end by the second phase inverter K
2with the second control end SW
2connect.
Optionally, the first switch T
1~ the eight switch T
8for PMOS transistor, or, the first switch T
1~ the eight switch T
8for nmos pass transistor.Based on this, the first switch T
1~ the eight switch T
8first end be drain electrode, the second end is source electrode, the 3rd end is grid.
In the present embodiment, by the drive integrated circult of 3D display device to the first control end SW
1with the second control end SW
2input control signal, controls the first switch T
1~ the eight switch T
8conducting or closedown, certainly, also can be carried out input control signal by independent control chip, the present invention is not limited to this.
If the first switch T
1~ the eight switch T
8for PMOS (PositivechannelMetal-Oxide-Semiconductor, P-channel metal-oxide-semiconductor field effect transistor), then when control signal is low level signal, switch conduction, when control signal is high level signal, switch cuts out; If the first switch T
1~ the eight switch T
8for NMOS tube (NegativechannelMetal-Oxide-Semiconductor, N NMOS N-channel MOS N field effect transistor), then when control signal is high level signal, switch conduction, when control signal is low level signal, switch cuts out.
Below with the first switch T
1~ the eight switch T
8for PMOS, control signal are the first level signal and second electrical level signal, and the first level signal be high level signal, second electrical level signal be low level signal is example, the course of work of control circuit is described in detail.
As the first control end SW
1with the second control end SW
2when inputting the first level signal and high level signal, high level signal makes the first switch T
1, the 3rd switch T
3, the 5th switch T
5with the 7th switch T
7disconnect; Through the first phase inverter K
1with the second phase inverter K
2high level signal be inverted into low level signal, the low level signal that obtains after anti-phase input second switch T
2, the 4th switch T
4, the 6th switch T
6with the 8th switch T
8after, make second switch T
2, the 4th switch T
4, the 6th switch T
6with the 8th switch T
8conducting.
Wherein, second switch T
2secondary signal R0 can be exported to the first output terminal OUT after conducting
1, the 4th switch T
4can the first signal L0 be exported to second output terminal OUT after conducting
2, the 6th switch T
6secondary signal R0 can be exported to the 3rd output terminal OUT after conducting
3, the 8th switch T
8can the first signal L0 be exported to the 4th output terminal OUT after conducting
4.Namely control module M can by the first signal L0 synchronism output to the second output terminal OUT
2with the 4th output terminal OUT
4, by secondary signal R0 synchronism output to the first output terminal OUT
1with the 3rd output terminal OUT
3.
As the first control end SW
1input the first level signal and high level signal, the second control end SW
2when input second electrical level signal and low level signal, high level signal makes the first switch T
1with the 3rd switch T
3disconnect, low level signal makes the 5th switch T
5with the 7th switch T
7conducting, the first phase inverter K
1the low level signal obtained after anti-phase makes second switch T
2with the 4th switch T
4conducting, the second phase inverter K
2the high level signal obtained after anti-phase makes the 6th switch T
6with the 8th switch T
8disconnect;
Wherein, the second switch T after conducting
2make secondary signal R
0export the first output terminal OUT to
1, the 4th switch T after conducting
4make the first signal L
0export the second output terminal OUT to
2, the 5th switch T after conducting
5make the first signal L
0export the 3rd output terminal OUT to
3, the 7th switch T after conducting
7make secondary signal R
0export the 4th output terminal OUT to
4; Namely control module M is by the first signal L
0synchronism output to the second output terminal OUT
2with the 3rd output terminal OUT
3, secondary signal R
0synchronism output to the first output terminal OUT
1with the 4th output terminal OUT
4.
In like manner, as the first control end SW
1with the second control end SW
2when input second electrical level signal and low level signal, low level signal makes the first switch T
1, the 3rd switch T
3, the 5th switch T
5with the 7th switch T
7conducting, the first phase inverter K
1with the second phase inverter K
2the high level signal obtained after anti-phase makes second switch T
2, the 4th switch T
4, the 6th switch T
6with the 8th switch T
8disconnect;
The first switch T after conducting
1make the first signal L
0export the first output terminal OUT to
1, the 3rd switch T after conducting
3make secondary signal R
0export the second output terminal OUT to
2, the 5th switch T after conducting
5make the first signal L
0export the 3rd output terminal OUT to
3, the 7th switch T after conducting
7make secondary signal R
0export the 4th output terminal OUT to
4; Namely control module M is by the first signal L
0synchronism output to the first output terminal OUT
1with the 3rd output terminal OUT
3, by secondary signal R
0synchronism output to the second output terminal OUT
2with the 4th output terminal OUT
4.
As the first control end SW
1input second electrical level signal and low level signal, the second control end SW
2when inputting the first level signal and high level signal, high level signal makes the 5th switch T
5with the 7th switch T
7disconnect, low level signal makes the first switch T
1with the 3rd switch T
3conducting, the first phase inverter K
1the high level signal obtained after anti-phase makes second switch T
2with the 4th switch T
4disconnect, the second phase inverter K
2the low level signal obtained after anti-phase makes the 6th switch T
6with the 8th switch T
8conducting;
Wherein, the first switch T after conducting
1make the first signal L
0export the first output terminal OUT to
1, the 3rd switch T after conducting
3make secondary signal R
0export the second output terminal OUT to
2, the 6th switch T after conducting
6make secondary signal R
0export the 3rd output terminal OUT to
3, the 8th switch T after conducting
8make the first signal L
0export the 4th output terminal OUT to
4; Namely control module M is by the first signal L
0synchronism output to the first output terminal OUT
1with the 4th output terminal OUT
4, by secondary signal R
0synchronism output to the second output terminal OUT
2with the 3rd output terminal OUT
3.
The control circuit that the present embodiment provides, control circuit can by the first signal as left eye data signal synchronism output to two output terminal, by secondary signal if right eye data signal synchronism output is to two other output terminal, and by controlling the difference of output first signal and secondary signal synchronous output end, make the gate line in 3D display device have 4 kinds of scan modes, and then realize 4 kinds of states of eye tracking.That is, the present invention does not need to carry out special processing by image processing system to data source, 4 kinds of states of eye tracking just can be realized by means of only the difference controlling this control circuit output signal synchronous output end, thus the problem that the 3D display screen cost solving the tracking of existing support eye is higher.
Embodiments of the invention two provide a kind of array base palte, this array base palte comprises multiple grid line groups, first grid driving circuit, second grid driving circuit, drive integrated circult and multiple control circuit, certainly, this array base palte also comprises data line, pixel electrode and public electrode etc., does not repeat them here.
As shown in Figure 4, grid line groups comprises the first grid polar curve G be arranged in order along arrow in Fig. 4 (i.e. the bearing of trend of data line)
1, second gate line G
2, the 3rd gate lines G
3with the 4th gate lines G
4, and multiple grid line groups is arranged in order along arrow in Fig. 4.Wherein, gate line is electrically connected with the grid of the thin film transistor (TFT) in pixel, for providing scanning drive signal to respective pixel.
First grid driving circuit 2 comprises multiple first grid driver element 20, and first grid driver element 20 comprises the first shift register 201 and the second shift register 202.First shift register 201 and corresponding first grid polar curve G
1connect, for the first grid polar curve G to correspondence
1input scanning drive signal.Second shift register 202 and the 3rd corresponding gate lines G
3connect, for the 3rd gate lines G to correspondence
3input scanning drive signal.
Second grid driving circuit 3 comprises multiple second grid driver element 30, and second grid driver element 30 comprises the 3rd shift register 301 and the 4th shift register 302.3rd shift register 301 and corresponding second gate line G
2connect, for the second gate line G to correspondence
2input scanning drive signal.4th shift register 302 and the 4th corresponding gate lines G
4connect, for the 4th gate lines G to correspondence
4input scanning drive signal.
Optionally, first grid driving circuit 2 and second grid driving circuit 3 are positioned at the both sides of array base palte, and first grid driving circuit 2 is positioned at the left side of array base palte, second grid driving circuit 3 is positioned at the right side of array base palte, but the present invention is not limited to this, in other embodiments, first grid driving circuit 2 can be positioned at the right side of array base palte, and second grid driving circuit 3 can be positioned at the left side of array base palte.
Particularly, be cascade between each first shift register 201 in first grid driving circuit 2, be cascade between the second shift register 202, be cascade between each the 3rd shift register 301 in second grid driving circuit 3, be cascade between the 4th shift register 302, and can forward scan between the shift register of cascade, also can reverse scan.
For forward scan, as shown in Figure 5, the output terminal OUT of the first shift register 201 in previous first grid driver element 20
5with the input end IN of the first shift register 201 in a rear first grid driver element 20
5connect, the output terminal OUT of the second shift register 202 in previous first grid driver element 20
6with the input end IN of the second shift register 202 in a rear first grid driver element 20
6connect;
The output terminal OUT of the 3rd shift register 301 in previous second grid driver element 30
7with the input end IN of the 3rd shift register 301 in a rear second grid driver element 30
7connect, the output terminal OUT of the 4th shift register 302 in previous second grid driver element 30
8with the input end IN of the 4th shift register 302 in a rear second grid driver element 30
8connect.
For the first shift register 201, the start signal of first shift register 201 of the 1st grade is the first scanning start signal, the start signal of n-th grade of first shift register 201 is the output signal of (n-1)th grade of shift register, wherein, n be greater than 1 positive integer.
In other embodiments of the invention, when shift register reverse scan in first grid driving circuit 2 and second grid driving circuit 3, the output terminal OUT of the first shift register 201 in a rear first grid driver element 20
5with the input end IN of the first shift register 201 in previous first grid driver element 20
5connect, the output terminal OUT of the second shift register 202 in a rear first grid driver element 20
6with the input end IN of the second shift register 202 in previous first grid driver element 20
6connect;
The output terminal OUT of the 3rd shift register 301 in a rear second grid driver element 30
7with the input end IN of the 3rd shift register 301 in previous second grid driver element 30
7connect, the output terminal OUT of the 4th shift register 302 in a rear second grid driver element 30
8with the input end IN of the 4th shift register 302 in previous second grid driver element 30
8connect.
In the present embodiment, drive integrated circult comprises multiple signal line group, and namely main control chip is connected with multiple signal line group, and this signal line group comprises the first signal wire and secondary signal line, and the first signal wire exports the first signal, and secondary signal line exports secondary signal; Wherein, during 2D display, the first signal and secondary signal are identical signal; During 3D display, the first signal and secondary signal are different signals, and if the first signal can be left eye image data signal, secondary signal can be right eye image data signal.
The control circuit that control circuit in the present embodiment provides for above-mentioned any embodiment.This control circuit comprises first input end IN
1~ the four-input terminal IN
4, the first output terminal OUT
1~ the four output terminal OUT
4, the first switch T
1~ the eight switch T
8, the first control end SW
1, the second control end SW
2, the first phase inverter K
1with the second phase inverter K
2.
Further, each the control circuit correspondence in the present embodiment controls the signal that a signal line group exports; First input end IN in each control circuit
1with four-input terminal IN
4connect with the first corresponding signal wire, the second input end IN
2with the 3rd input end IN
3connect with corresponding secondary signal line; First output terminal OUT of each control circuit
1be connected with the first shift register 201, the second output terminal OUT
2be connected with the second shift register 202, the 3rd output terminal OUT
3be connected with the 3rd shift register 301, the 4th output terminal OUT
4be connected with the 4th shift register 302.
Comprise three signal line group and drive integrated circult for drive integrated circult to be below connected with 6 signal wires and to be described, but, the present invention is not limited to this, in other embodiments, drive integrated circult can be connected with four signal line group, and namely drive integrated circult is connected with 8 signal wires.
Above-mentioned three signal line group comprise start signal line group, the first clock cable group and second clock signal line group.Start signal line group comprises the first initial signal wire and the second start signal line, and the first clock cable group comprises the first clock cable and second clock signal wire, and second clock signal line group comprises the 3rd clock cable and the 4th clock cable.
Wherein, first initial signal wire is connected with the 1st control circuit with the second start signal line, namely the first input end of the first initial signal wire and this control circuit and four-input terminal are connected, for scanning start signal to first input end and four-input terminal input first, second input end and the 3rd input end of the second start signal line and this control circuit are connected, for the second input end and the 3rd input end input second scanning start signal.
First clock cable is connected with the 2nd control circuit with second clock signal wire, namely the first input end of the first clock cable and this control circuit and four-input terminal are connected, for inputting the first clock signal to first input end and four-input terminal, second input end and the 3rd input end of second clock signal wire and this control circuit are connected, for the second input end and the 3rd input end input second clock signal.
3rd clock cable is connected with the 3rd control circuit with the 4th clock cable, namely the first input end of the 3rd clock cable and this control circuit and four-input terminal are connected, for inputting the 3rd clock signal to first input end and four-input terminal, second input end and the 3rd input end of the 4th clock cable and this control circuit are connected, for the second input end and the 3rd input end input the 4th clock signal.
For forward scan, as shown in Figure 5, the first output terminal OUT of the 1st control circuit
10with the input end IN of the first shift register 201 in the 1st first grid driver element 20
5connect, the second output terminal OUT
20with the input end IN of the second shift register 202 in the 1st first grid driver element 20
6connect, the 3rd output terminal OUT
30with the input end IN of the 3rd shift register 301 in the 1st second grid driver element 30
7connect, the 4th output terminal OUT
40with the input end IN of the 4th shift register 302 in the 1st second grid driver element 30
7connect.
First output terminal OUT of the 2nd control circuit
11with the first clock signal terminal CK of each the first shift register 201
1connect, the second output terminal OUT
21with the first clock signal C K of each the second shift register 202
2end connects, the 3rd output terminal OUT
31with the first clock signal terminal CK of each the 3rd shift register 301
3connect, the 4th output terminal OUT
41with the first clock signal terminal CK of each the 4th shift register 302
4connect.
First output terminal OUT of the 2nd control circuit
12with the second clock signal end CK of each the first shift register 201
5connect, the second output terminal OUT
22with the second clock signal end CK of each the second shift register 202
6connect, the 3rd output terminal OUT
32with the second clock signal end CK of each the 3rd shift register 301
7connect, the 4th output terminal OUT
42with the second clock signal end CK of each the 4th shift register 302
8connect.
Based on this, in the first scan mode of array base palte, control the 1st control circuit by the first scanning start signal synchronism output to the second output terminal OUT by drive integrated circult
20with the 4th output terminal OUT
40, by the second scanning start signal synchronism output to the first output terminal OUT
10with the 3rd output terminal OUT
30; Control the 2nd control circuit and export the first clock signal synchronization to second output terminal OUT
21with the 4th output terminal OUT
41, by second clock signal synchronism output to the first output terminal OUT
11with the 3rd output terminal OUT
31; Control the 3rd control circuit and export the 3rd clock signal synchronization to second output terminal OUT
22with the 4th output terminal OUT
42, export the 4th clock signal synchronization to first output terminal OUT
12with the 3rd output terminal OUT
32.
Wherein, the 1st control circuit, the 2nd control circuit are identical with the control procedure that above-described embodiment describes with the control procedure of the 3rd control circuit, namely by control first switch T
1~ the eight switch T
8conducting or to close the synchronous output end controlling to output signal different, concrete control procedure does not repeat them here.
For the first scanning start signal and the second scanning start signal, due to the first output terminal OUT
10by the first shift register 201 and first grid polar curve G
1connect, the 3rd output terminal OUT
30by the 3rd shift register 301 and second gate line G
2connect, therefore, the second scanning start signal synchronism output is to first grid polar curve G
1with second gate line G
2.Due to the second output terminal OUT
20by the second shift register 202 and the 3rd gate lines G
3connect, the 4th output terminal OUT
40by the 4th shift register 302 and the 4th gate lines G
4connect, therefore, the first scanning start signal synchronism output is to the 3rd gate lines G
3with the 4th gate lines G
4.
Because the pixel of same gate line with same a line is connected, for providing signal to the pixel of same a line, therefore, the second scanning start signal synchronism output is to the first row pixel and the second row pixel, and the first scanning start signal synchronism output is to the third line pixel and fourth line pixel.
When the first scanning start signal is right eye image data signal R
0, the second scanning start signal is left eye image data signal L
0time, above-mentioned scan mode can realize the eye tracking mode shown in Fig. 1 a.Wherein, first grid polar curve G
1, second gate line G
2, the 3rd gate lines G
3with the 4th gate lines G
4in the first scanning start signal and right eye image data signal R
0or second scans start signal and left eye image data signal L
0sequential chart as shown in Figure 6 a.
In the second scan mode of array base palte, control the 1st control circuit by the first scanning start signal synchronism output to the second output terminal OUT by drive integrated circult
20with the 3rd output terminal OUT
30, by the second scanning start signal synchronism output to the first output terminal OUT
10with the 4th output terminal OUT
40; Control the 2nd control circuit and export the first clock signal synchronization to second output terminal OUT
21with the 3rd output terminal OUT
31, by second clock signal synchronism output to the first output terminal OUT
11with the 4th output terminal OUT
41; Control the 3rd control circuit and export the 3rd clock signal synchronization to second output terminal OUT
22with the 3rd output terminal OUT
32, export the 4th clock signal synchronization to first output terminal OUT
12with the 4th output terminal OUT
42.
In like manner, for the first scanning start signal and the second scanning start signal, when the first scanning start signal is right eye image data signal R
0, the second scanning start signal is left eye image data signal L
0time, above-mentioned scan mode can realize the eye tracking mode shown in Fig. 1 b.First grid polar curve G
1, second gate line G
2, the 3rd gate lines G
3with the 4th gate lines G
4in the first scanning start signal and right eye image data signal R
0or second scans start signal and left eye image data signal L
0sequential chart as shown in Figure 6 b.
In the third scan mode of array base palte, control the 1st control circuit by the first scanning start signal synchronism output to the first output terminal OUT by drive integrated circult
10with the 3rd output terminal OUT
30, by the second scanning start signal synchronism output to the second output terminal OUT
20with the 4th output terminal OUT
40; Control the 2nd control circuit and export the first clock signal synchronization to first output terminal OUT
11with the 3rd output terminal OUT
31, by second clock signal synchronism output to the second output terminal OUT
21with the 4th output terminal OUT
41; Control the 3rd control circuit and export the 3rd clock signal synchronization to first output terminal OUT
12with the 3rd output terminal OUT
32, export the 4th clock signal synchronization to second output terminal OUT
22with the 4th output terminal OUT
42;
In like manner, this scan mode can realize the eye tracking mode shown in Fig. 1 c.First grid polar curve G
1, second gate line G
2, the 3rd gate lines G
3with the 4th gate lines G
4in the first scanning start signal and right eye image data signal R
0or second scans start signal and left eye image data signal L
0sequential chart as fig. 6 c.
In the 4th kind of scan mode of array base palte, control the 1st control circuit by the first scanning start signal synchronism output to the first output terminal OUT by drive integrated circult
10with the 4th output terminal OUT
40, by the second scanning start signal synchronism output to the second output terminal OUT
20with the 3rd output terminal OUT
30; Control the 2nd control circuit and export the first clock signal synchronization to first output terminal OUT
11with the 4th output terminal OUT
41, by second clock signal synchronism output to the second output terminal OUT
21with the 3rd output terminal OUT
31; Control the 3rd control circuit and export the 3rd clock signal synchronization to first output terminal OUT
12with the 4th output terminal OUT
42, export the 4th clock signal synchronization to second output terminal OUT
22with the 3rd output terminal OUT
32;
In like manner, this scan mode can realize the eye tracking mode shown in Fig. 1 d.First grid polar curve G
1, second gate line G
2, the 3rd gate lines G
3with the 4th gate lines G
4in the first scanning start signal and right eye image data signal R
0or second scans start signal and left eye image data signal L
0sequential chart as shown in fig 6d.
Wherein, array base palte is when showing 2D effect, first scanning start signal and the second scanning start signal are identical data-signal, and the first clock signal and second clock signal are identical data-signal, and the 3rd clock signal and the 4th clock signal are identical data-signal.
When showing 3D effect, first scanning start signal and the second scanning start signal are different data-signals, first clock signal and second clock signal are different data-signals, 3rd clock signal and the 4th clock signal are different data-signals, such as, the first scanning start signal, the first clock signal and the 3rd clock signal is left eye image data signal L
0, the second scanning start signal, second clock signal and the 4th clock signal is right eye image data signal R
0.
In other embodiments, during shift register reverse scan, the first output terminal OUT of the 1st control circuit
10with the input end IN of the first shift register 201 in last first grid driver element 20
5connect, the second output terminal OUT
20with the input end IN of the second shift register 202 in last first grid driver element 20
6connect, the 3rd output terminal OUT
30with the input end IN of the 3rd shift register 301 in last second grid driver element 30
7connect, the 4th output terminal OUT
40with the input end IN of the 4th shift register 302 in last second grid driver element 30
7connect.
The array base palte that the present embodiment provides, control circuit can by the first signal as left eye data signal synchronism output to two output terminal, by secondary signal if right eye data signal synchronism output is to two other output terminal, and by controlling the difference of output first signal and secondary signal synchronous output end, make the gate line in 3D display device have 4 kinds of scan modes, and then realize 4 kinds of states of eye tracking.That is, the array base palte that the present embodiment provides does not need to carry out special processing by image processing system to data source, 4 kinds of states of eye tracking just can be realized by means of only the difference controlling this control circuit output signal synchronous output end, thus the problem that the 3D display screen cost solving the tracking of existing support eye is higher.
Embodiments of the invention three provide a kind of display panel, and this display panel comprises the array base palte that as above any embodiment provides.
Embodiments of the invention four provide a kind of display device, and this display device comprises the display panel that above-described embodiment provides.
The display panel that the present embodiment provides and 3D display device, control circuit can by the first signal as left eye data signal synchronism output to two output terminal, by secondary signal if right eye data signal synchronism output is to two other output terminal, and by controlling the difference of output first signal and secondary signal synchronous output end, make the gate line in 3D display device have 4 kinds of scan modes, and then realize 4 kinds of states of eye tracking.That is, the array base palte that the present embodiment provides does not need to carry out special processing by image processing system to data source, 4 kinds of states of eye tracking just can be realized by means of only the difference controlling this control circuit output signal synchronous output end, thus the problem that the 3D display screen cost solving the tracking of existing support eye is higher.
In this instructions, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the present invention.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein can without departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.
Claims (11)
1. a control circuit, is characterized in that, comprises first input end ~ the four-input terminal, control module, the first output terminal ~ the 4th output terminal; Described first input end and four-input terminal input the first signal, described second input end and the 3rd input end input secondary signal;
Described control module is used for by described first signal synchronism output to described second output terminal and the 4th output terminal, by described secondary signal synchronism output to described first output terminal and the 3rd output terminal;
Or, by described first signal synchronism output to described second output terminal and the 3rd output terminal, by described secondary signal synchronism output to described first output terminal and the 4th output terminal;
Or, by described first signal synchronism output to described first output terminal and the 3rd output terminal, by described secondary signal synchronism output to described second output terminal and the 4th output terminal;
Or, by described first signal synchronism output to described first output terminal and the 4th output terminal, by described secondary signal synchronism output to described second output terminal and the 3rd output terminal.
2. control circuit according to claim 1, is characterized in that, described control module comprises the first switch ~ the 8th switch;
The first end of described first switch is all connected with described first output terminal with the first end of described second switch, second end of described first switch is connected with described first input end, second end of described second switch is connected with described 3rd input end, 3rd end of described first switch is connected with the first control end, and the 3rd end of described second switch is connected with described first control end by the first phase inverter;
The first end of described 3rd switch is all connected with described second output terminal with the first end of described 4th switch, second end of described 3rd switch is connected with described second input end, second end of described 4th switch is connected with described four-input terminal, 3rd end of described 3rd switch is connected with the first control end, and the 3rd end of described 4th switch is connected with described first control end by the first phase inverter;
The first end of described 5th switch is all connected with described 3rd output terminal with the first end of described 6th switch, second end of described 5th switch is connected with described first input end, second end of described 6th switch is connected with described 3rd input end, 3rd end of described 5th switch is connected with the second control end, and the 3rd end of described 6th switch is connected with described second control end by the second phase inverter;
The first end of described 7th switch is all connected with described 4th output terminal with the first end of described 8th switch, second end of described 7th switch is connected with described second input end, second end of described 8th switch is connected with described four-input terminal, 3rd end of described 7th switch is connected with the second control end, and the 3rd end of described 8th switch is connected with described second control end by the second phase inverter.
3. control circuit according to claim 2, it is characterized in that, when described second switch, the 4th switch, the 6th switch and the 8th switch conduction, when described first switch, the 3rd switch, the 5th switch and the 7th switch disconnect, described control module by described first signal synchronism output to described second output terminal and the 4th output terminal, by described secondary signal synchronism output to described first output terminal and the 3rd output terminal;
When described second switch, the 4th switch, the 5th switch and the 7th switch conduction, when described first switch, the 3rd switch, the 6th switch and the 8th switch disconnect, described control module by described first signal synchronism output to described second output terminal and the 3rd output terminal, by described secondary signal synchronism output to described first output terminal and the 4th output terminal;
When described first switch, the 3rd switch, the 5th switch and the 7th switch conduction, when described second switch, the 4th switch, the 6th switch and the 8th switch disconnect, described control module by described first signal synchronism output to described first output terminal and the 3rd output terminal, by described secondary signal synchronism output to described second output terminal and the 4th output terminal;
When described first switch, the 3rd switch, the 6th switch and the 8th switch conduction, when described second switch, the 4th switch, the 5th switch and the 7th switch disconnect, described control module by described first signal synchronism output to described first output terminal and the 4th output terminal, by described secondary signal synchronism output to described second output terminal and the 3rd output terminal.
4. array base palte according to claim 3, it is characterized in that, when described first control end and described second control end input the first level signal, described second switch, the 4th switch, the 6th switch and the 8th switch conduction, described first switch, the 3rd switch, the 5th switch and the 7th switch disconnect;
When described first control end and described second control end input second electrical level signal, described first switch, the 3rd switch, the 5th switch and the 7th switch conduction, described second switch, the 4th switch, the 6th switch and the 8th switch disconnect;
When described first control end inputs the first level signal, during described second control end input second electrical level signal, described second switch, the 4th switch, the 5th switch and the 7th switch conduction, described first switch, the 3rd switch, the 6th switch and the 8th switch disconnect;
When described first control end input second electrical level signal, when described second control end inputs the first level signal, described first switch, the 3rd switch, the 6th switch and the 8th switch conduction, described second switch, the 4th switch, the 5th switch and the 7th switch disconnect.
5. array base palte according to claim 2, is characterized in that, described first switch ~ the 8th switch is PMOS transistor or nmos pass transistor, and described first end is drain electrode, and described second end is source electrode, and described 3rd end is grid.
6. an array base palte, is characterized in that, comprises multiple grid line groups, first grid driving circuit, second grid driving circuit, drive integrated circult and multiple control circuit, and described control circuit is the control circuit described in any one of Claims 1 to 5;
Described grid line groups comprises the first grid polar curve, second gate line, the 3rd gate line and the 4th gate line that are arranged in order;
Described first grid driving circuit comprises multiple first grid driver element, described first grid driver element comprises the first shift register and the second shift register, described first shift register connects with corresponding described first grid polar curve, and the second shift register connects with corresponding described 3rd gate line;
Described second grid driving circuit comprises multiple second grid driver element, described second grid driver element comprises the 3rd shift register and the 4th shift register, described 3rd shift register connects with corresponding described second gate line, and described 4th shift register connects with corresponding described 4th gate line;
Described drive integrated circult comprises multiple signal line group, and described signal line group comprises the first signal wire and secondary signal line, and described first signal wire exports the first signal, and described secondary signal line exports secondary signal;
Described in each, control circuit correspondence controls the signal that described in, signal line group exports; First input end in control circuit described in each is connected with corresponding described first signal wire with four-input terminal, and the second input end is connected with corresponding described secondary signal line with the 3rd input end; First output terminal of control circuit described in each is connected with described first shift register, second output terminal is connected with described second shift register, described 3rd output terminal is connected with described 3rd shift register, and described 4th output terminal is connected with described 4th shift register;
Wherein, during 2D display, described first signal and secondary signal are identical signal; During 3D display, described first signal and secondary signal are different signals.
7. array base palte according to claim 6, is characterized in that, the shift register forward scan in described first grid driving circuit and second grid driving circuit;
Wherein, the output terminal of the first shift register in previous described first grid driver element is connected with the input end of the first shift register in a rear described first grid driver element, and the output terminal of the second shift register in previous described first grid driver element is connected with the input end of the second shift register in a rear described first grid driver element;
The output terminal of the 3rd shift register in previous described second grid driver element is connected with the input end of the 3rd shift register in a rear described second grid driver element, and the output terminal of the 4th shift register in previous described second grid driver element is connected with the input end of the 4th shift register in a rear described second grid driver element.
8. array base palte according to claim 6, is characterized in that, the shift register reverse scan in described first grid driving circuit and second grid driving circuit;
Wherein, the output terminal of the first shift register in a rear described first grid driver element is connected with the input end of the first shift register in previous described first grid driver element, and the output terminal of the second shift register in a rear described first grid driver element is connected with the input end of the second shift register in previous described first grid driver element;
The output terminal of the 3rd shift register in a rear described second grid driver element is connected with the input end of the 3rd shift register in previous described second grid driver element, and the output terminal of the 4th shift register in a rear described second grid driver element is connected with the input end of the 4th shift register in previous described second grid driver element.
9. the array base palte according to claim 7 or 8, is characterized in that, described drive integrated circult comprises three signal line group, and described three signal line group comprise start signal line group, the first clock cable group and second clock signal line group;
When described signal line group is start signal line group, and during described shift register forward scan, first output terminal of corresponding described control circuit is connected with the first shift register in the 1st first grid driver element, second output terminal is connected with the second shift register in the 1st first grid driver element, 3rd output terminal is connected with the 3rd shift register in the 1st second grid driver element, and the 4th output terminal is connected with the 4th shift register in the 1st second grid driver element;
When described signal line group is start signal line group, and during described shift register reverse scan, first output terminal of corresponding described control circuit is connected with the first shift register in last first grid driver element, second output terminal is connected with the second shift register in last first grid driver element, 3rd output terminal is connected with the 3rd shift register in last second grid driver element, and the 4th output terminal is connected with the 4th shift register in last second grid driver element;
When described signal line group be the first clock cable group or second clock signal line group time, first output terminal of corresponding described control circuit is connected with the first shift register described in each, second output terminal is connected with the second shift register described in each, described 3rd output terminal is connected with the 3rd shift register described in each, and described 4th output terminal is connected with the 4th shift register described in each.
10. a display panel, is characterized in that, comprises the array base palte described in any one of claim 1 ~ 9.
11. 1 kinds of 3D display device, is characterized in that, comprise display panel according to claim 10.
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| CN102779103A (en) * | 2011-05-12 | 2012-11-14 | 宏碁股份有限公司 | Switching circuit, electronic device and independent display card module |
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| CN203909440U (en) * | 2014-04-30 | 2014-10-29 | 深圳市亿思达显示科技有限公司 | Liquid-crystal lens electronic grating and naked-eye three-dimensional display device |
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| CN1881474A (en) * | 2005-06-13 | 2006-12-20 | 三星电子株式会社 | Shift register and a display device including the shift register |
| US20080055293A1 (en) * | 2006-09-01 | 2008-03-06 | Au Optronics Corp. | Signal-driving system and shift register unit thereof |
| CN102779103A (en) * | 2011-05-12 | 2012-11-14 | 宏碁股份有限公司 | Switching circuit, electronic device and independent display card module |
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