CN105047126B - Control circuit, array substrate, display panel and 3D display device - Google Patents
Control circuit, array substrate, display panel and 3D display device Download PDFInfo
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Abstract
The present invention provides a kind of control circuit, array substrate, display panel and 3D display device, including first input end~the 4th input terminal, control unit, the output terminal of the first output terminal~the 4th；First input end and the 4th input terminal input the first signal, the second input terminal and third input terminal input second signal；Control unit is used for the first signal synchronism output to second output terminal and the 4th output terminal, by second signal synchronism output to the first output terminal and third output terminal；By the first signal synchronism output to second output terminal and third output terminal, by second signal synchronism output to the first output terminal and the 4th output terminal；By the first signal synchronism output to the first output terminal and third output terminal, by second signal synchronism output to second output terminal and the 4th output terminal；By the first signal synchronism output to the first output terminal and the 4th output terminal, by second signal synchronism output to second output terminal and third output terminal.Solve the problems, such as that existing 3D display screen cost is higher.
Description
Technical field
The present invention relates to luminescence display technical field, more specifically to a kind of control circuit, array substrate, display
Panel and 3D display device.
Background technology
In the display panel of existing 3D display screen, when showing 2D effects, image is handled by image processing system
Data-signal so that the viewdata signal of adjacent rows pixel is identical；In the conventional 3D effect of display, pass through image processing system
To handle viewdata signal so that the viewdata signal of adjacent rows pixel is different, and the image data of adjacent rows pixel
Signal is respectively left eye image data signal and right eye image data signal；
In the 3D effect for showing eye tracking, to reach best 3D display effect, the data of pixel are needed according to people
The angles and positions of eye are adjusted, and realize following four kinds of states：First, as shown in Figure 1a, the 1st row and the input of the 2nd row pixel are left
Eye data-signal L, the 3rd row and the 4th row pixel input right eye data signal R, and so on, M+1 rows and M+2 row pixels are defeated
Enter left eye data signal L, M+3 rows and M+4 rows pixel input right eye data signal R；2nd, as shown in Figure 1 b, the 1st row and
4 row pixels input right eye data signal R, the 2nd row and the 3rd row pixel input left eye data signal L, and so on, M+1 rows and
M+4 rows pixel inputs right eye data signal R, M+2 rows and M+3 rows pixel input left eye data signal L；3rd, such as Fig. 1 c
Shown, the 1st row and the 2nd row pixel input right eye data signal R, the 3rd row and the 4th row pixel input left eye data signal L, with this
Analogize, M+1 rows and M+2 rows pixel input right eye data signal R, M+3 rows and M+4 rows pixel input left eye data letter
Number L；4th, as shown in Figure 1 d, the 1st row and the 4th row pixel are left eye data signal L, and the 2nd row and the 3rd row pixel are right eye data
Signal R, and so on, M+1 rows and M+4 rows pixel are left eye data signal L, and M+2 rows and M+3 rows pixel are right eye
Data-signal R.Wherein, M is greater than or equal to 1 integer.
Specially treated is carried out to viewdata signal by image processing system in the prior art, to realize eye tracking
3D effect.But since image processing system has complicated Driving Scheme, hardware cost height and software program complexity etc.
Therefore problem, can cause to support that the cost of the 3D display screen of eye tracking 3D effect is higher.
Invention content
In view of this, the present invention provides a kind of control circuit, array substrate, display panel and 3D display device, with solution
The problem of 3D display screen cost of certainly existing support eye tracking is higher.
To achieve the above object, the present invention provides following technical solution：
A kind of control circuit, including first input end~the 4th input terminal, control unit, the output of the first output terminal~4th
End；The first input end and the 4th input terminal input the first signal, second input terminal and third input terminal input second
Signal；
Described control unit is used for the first signal synchronism output to the second output terminal and the 4th output terminal, will
The second signal synchronism output is to first output terminal and third output terminal；
Alternatively, by the first signal synchronism output to the second output terminal and third output terminal, described second is believed
Number synchronism output is to first output terminal and the 4th output terminal；
Alternatively, by the first signal synchronism output to first output terminal and third output terminal, described second is believed
Number synchronism output is to the second output terminal and the 4th output terminal；
Alternatively, by the first signal synchronism output to first output terminal and the 4th output terminal, described second is believed
Number synchronism output is to the second output terminal and third output terminal.
A kind of array substrate, including multiple grid line groups, first grid driving circuit, second grid driving circuit, driving
Integrated circuit and multiple control circuits, the control circuit are as above any one of them control circuit；
The grid line groups include the first grid polar curve, second gate line, third gate line and the 4th grid that are arranged in order
Line；
The first grid driving circuit includes multiple first grid driving units, and the first grid driving unit includes
First shift register and the second shift register, first shift register are connected with the corresponding first grid polar curve,
Second shift register is connected with the corresponding third gate line；
The second grid driving circuit includes multiple second grid driving units, and the second grid driving unit includes
Third shift register and the 4th shift register, the third shift register are connected with the corresponding second gate line,
4th shift register is connected with corresponding 4th gate line；
The drive integrated circult includes multiple signal line groups, and the signal line group includes the first signal wire and second signal
Line, first signal wire export the first signal, and the second signal line exports second signal；
Each control circuit corresponds to the signal of the one signal line group output of control；In each control circuit
First input end and the 4th input terminal are connected with corresponding first signal wire, the second input terminal and third input terminal with it is corresponding
The second signal line connection；First output terminal of each control circuit is connect with first shift register, the
Two output terminals are connect with second shift register, and the third output terminal is connect with the third shift register, described
4th output terminal is connect with the 4th shift register；
Wherein, when 2D is shown, the first signal and the second signal are identical signal；During 3D display, first letter
Number and second signal be different signals.
A kind of display panel, including as above any one of them array substrate.
A kind of 3D display device, including display panel as described above.
Compared with prior art, technical solution provided by the present invention has the following advantages：
Control circuit provided by the present invention, array substrate, display panel and 3D display device, control circuit can be by first
Signal such as left eye data signal synchronism output is to two output terminals, by second signal such as right eye data signal synchronism output in addition
Two output terminals, and pass through the difference of control output the first signal and the second signal output terminal, to cause in 3D display device
Gate line has 4 kinds of scan modes, and then realizes 4 kinds of states of eye tracking.That is, the present invention is not required to by image
Reason system carries out specially treated to data source, only by the way that the output terminal difference of the control circuit output signal is controlled to can be realized as
4 kinds of states of eye tracking, so as to solve the problems, such as that the 3D display screen cost of existing support eye tracking is higher.
Description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, to embodiment or will show below
There is attached drawing needed in technology description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention, for those of ordinary skill in the art, without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 a~Fig. 1 d are to show that eye tracks 4 kinds of pixel status schematic diagrames of 3D effect for 3D display screen；
Fig. 2 is the structure diagram of control circuit that the embodiment of the present invention one provides；
Fig. 3 is the structure diagram of the control unit of control circuit that the embodiment of the present invention one provides；
Fig. 4 is the part-structure schematic diagram of array substrate provided by Embodiment 2 of the present invention；
Fig. 5 is signal line group provided by Embodiment 2 of the present invention and the connection relationship diagram of shift register；
Fig. 6 a~Fig. 6 d are the initial sweep signal sequence of each gate line in array substrate provided by Embodiment 2 of the present invention
Figure.
Specific embodiment
Below in conjunction with the attached drawing in the embodiment of the present invention, the technical solution in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other without making creative work
Embodiment shall fall within the protection scope of the present invention.
The embodiment of the present invention one provides a kind of control circuit, as shown in Fig. 2, the control circuit includes first input end
IN1, the second input terminal IN2, third input terminal IN3, the 4th input terminal IN4, control unit M, the first output terminal OUT1, second output
Hold OUT2, third output terminal OUT3With the 4th output terminal OUT4, wherein, first input end IN1With the 4th input terminal IN4Input first
Signal L0, the second input terminal IN2With third input terminal IN3Input second signal R0。
Wherein, control unit M is used for the first signal L0Synchronism output is to second output terminal OUT2With the 4th output terminal
OUT4, by second signal R0Synchronism output is to the first output terminal OUT1With third output terminal OUT3；
Alternatively, by the first signal L0Synchronism output is to second output terminal OUT2With third output terminal OUT3, by second signal R0
Synchronism output is to the first output terminal OUT1With the 4th output terminal OUT4；
Alternatively, by the first signal L0Synchronism output is to the first output terminal OUT1With third output terminal OUT3, by second signal R0
Synchronism output is to second output terminal OUT2With the 4th output terminal OUT4；
Alternatively, by the first signal L0Synchronism output is to the first output terminal OUT1With the 4th output terminal OUT4, by second signal R0
Synchronism output is to second output terminal OUT2With third output terminal OUT3。
Control circuit in the present embodiment can be connected with drive integrated circult, that is, main control chip in 3D display device, the drive
The left eye data signal of dynamic integrated circuit output is as the first signal L0Input control circuit, the right eye of drive integrated circult output
Data-signal is as second signal R0Input control circuit, wherein, left eye data signal include left-eye image scanning signal and when
Clock signal etc., right eye data signal include eye image scanning signal and clock signal etc..
Control circuit by left eye data signal synchronism output to two output terminals, such as second output terminal OUT2With the 4th output
Hold OUT4, by right eye data signal synchronism output to other two output terminal, such as the first output terminal OUT1With third output terminal
OUT3, and pass through the synchronous output end difference of control output left eye data signal and right eye data signal, 3D display to be caused to fill
Gate line in putting has 4 kinds of scan modes, and then realizes 4 kinds of states of eye tracking, this 4 kinds of states are respectively such as Fig. 1 a~figure
Shown in 1d.Above-mentioned 4 kinds of scan modes are described in detail in the concrete structure that 3D display device can be combined in subsequent embodiment,
This is repeated no more.
Wherein, the synchronous output end difference of control left eye data signal refers to that left eye data signal synchronism output can be controlled
To second output terminal OUT2With the 4th output terminal OUT4, left eye data signal synchronism output can also be controlled to second output terminal
OUT2With third output terminal OUT3；The synchronous output end difference of control right eye data signal refers to that right eye data signal can be controlled
Synchronism output is to the first output terminal OUT1With third output terminal OUT3, right eye data signal synchronism output can also be controlled to first
Output terminal OUT1With the 4th output terminal OUT4。
In the specific embodiment of the present invention, as shown in figure 3, control unit M includes first switch T1, second open
Close T2, third switch T3, the 4th switch T4, the 5th switch T5, the 6th switch T6, the 7th switch T7, the 8th switch T8, first control
Hold SW1, the second control terminal SW2, the first phase inverter K1With the second phase inverter K2。
As shown in figure 3, first switch T1First end and second switch T2First end with the first output terminal OUT1Even
It connects, first switch T1Second end and first input end IN1Connection, first switch T1Third end and the first control terminal SW1Even
It connects, second switch T2Second end and third input terminal IN3Connection, second switch T2Third end pass through the first phase inverter K1With
First control terminal SW1Connection；
Third switchs T3First end and the 4th switch T4First end with second output terminal OUT2Connection, third switch
T3Second end and the second input terminal IN2Connection, third switch T3Third end and the first control terminal SW1Connection, the 4th switch T4
Second end and the 4th input terminal IN4Connection, the 4th switch T4Third end pass through the first phase inverter K1With the first control terminal SW1
Connection；
5th switch T5First end and the 6th switch T6First end with third output terminal OUT3Connection, the 5th switch
T5Second end and first input end IN1Connection, the 5th switch T5Third end and the second control terminal SW2Connection, the 6th switch T6
Second end and third input terminal IN3Connection, the 6th switch T6Third end pass through the second phase inverter K2With the second control terminal SW2
Connection；
7th switch T7First end and the 8th switch T8First end with the 4th output terminal OUT4Connection, the 7th switch
T7Second end and the second input terminal IN2Connection, the 7th switch T7Third end and the second control terminal SW2Connection, the 8th switch T8
Second end and the 4th input terminal IN4Connection, the 8th switch T8Third end pass through the second phase inverter K2With the second control terminal SW2
Connection.
Optionally, first switch T1~the eight switch T8For PMOS transistor, alternatively, first switch T1~the eight switch T8
For NMOS transistor.Based on this, first switch T1~the eight switch T8First end be drain electrode, second end is source electrode, third end is
Grid.
It, can be by the drive integrated circult of 3D display device to the first control terminal SW in the present embodiment1With the second control terminal
SW2Input control signal, to control first switch T1~the eight switch T8On and off, it is of course also possible to by individual
Control chip carrys out input control signal, and the present invention is not limited to this.
If first switch T1~the eight switch T8For PMOS tube (Positive channel Metal-Oxide-
Semiconductor, P-channel metal-oxide-semiconductor field-effect tube), then when controlling signal as low level signal, switch is led
Logical, when control signal is high level signal, switch is closed；If first switch T1~the eight switch T8For NMOS tube (Negative
Channel Metal-Oxide-Semiconductor, N-channel metal oxide semiconductor field effect tube), then control the signal to be
During high level signal, switch conduction, when control signal is low level signal, switch is closed.
Below with first switch T1~the eight switch T8It is the first level signal and second electrical level for PMOS tube, control signal
Signal, and the first level signal is high level signal, second electrical level signal is the work to control circuit for low level signal
Process is described in detail.
As the first control terminal SW1With the second control terminal SW2Input the first level signal i.e. high level signal when, high level letter
Number so that first switch T1, third switch T3, the 5th switch T5With the 7th switch T7It disconnects；By the first phase inverter K1It is anti-with second
Phase device K2High level signal be inverted into low level signal, the low level signal that is obtained after reverse phase input second switch T2, the 4th
Switch T4, the 6th switch T6With the 8th switch T8Afterwards so that second switch T2, the 4th switch T4, the 6th switch T6With the 8th switch
T8Conducting.
Wherein, second switch T2Second signal R0 can be exported after conducting to the first output terminal OUT1, the 4th switch T4Conducting
After the first signal L0 can be exported to second output terminal OUT2, the 6th switch T6Second signal R0 can be exported to third after conducting
Output terminal OUT3, the 8th switch T8The first signal L0 can be exported after conducting to the 4th output terminal OUT4.That is control unit M can be incited somebody to action
First signal L0 synchronism outputs are to second output terminal OUT2With the 4th output terminal OUT4, by second signal R0 synchronism outputs to first
Output terminal OUT1With third output terminal OUT3。
As the first control terminal SW1Input the first level signal i.e. high level signal, the second control terminal SW2Input second electrical level
During signal, that is, low level signal, high level signal causes first switch T1T is switched with third3It disconnects, low level signal causes the 5th
Switch T5With the 7th switch T7Conducting, the first phase inverter K1The low level signal obtained after reverse phase causes second switch T2With the 4th
Switch T4Conducting, the second phase inverter K2The high level signal obtained after reverse phase causes the 6th switch T6With the 8th switch T8It disconnects；
Wherein, the second switch T after conducting2Cause second signal R0It exports to the first output terminal OUT1, the after conducting the 4th
Switch T4Cause the first signal L0It exports to second output terminal OUT2, the 5th switch T after conducting5Cause the first signal L0Output is extremely
Third output terminal OUT3, the 7th switch T after conducting7Cause second signal R0It exports to the 4th output terminal OUT4；That is control unit
M is by the first signal L0Synchronism output is to second output terminal OUT2With third output terminal OUT3, second signal R0Synchronism output is to first
Output terminal OUT1With the 4th output terminal OUT4。
Similarly, as the first control terminal SW1With the second control terminal SW2When inputting second electrical level signal, that is, low level signal, low electricity
Ordinary mail number is so that first switch T1, third switch T3, the 5th switch T5With the 7th switch T7Conducting, the first phase inverter K1It is anti-with second
Phase device K2The high level signal obtained after reverse phase causes second switch T2, the 4th switch T4, the 6th switch T6With the 8th switch T8It is disconnected
It opens；
First switch T after conducting1Cause the first signal L0It exports to the first output terminal OUT1, the third switch after conducting
T3Cause second signal R0It exports to second output terminal OUT2, the 5th switch T after conducting5Cause the first signal L0It exports to third
Output terminal OUT3, the 7th switch T after conducting7Cause second signal R0It exports to the 4th output terminal OUT4；That is control unit M will
First signal L0Synchronism output is to the first output terminal OUT1With third output terminal OUT3, by second signal R0Synchronism output is to second
Output terminal OUT2With the 4th output terminal OUT4。
As the first control terminal SW1Input second electrical level signal, that is, low level signal, the second control terminal SW2Input the first level
During signal, that is, high level signal, high level signal causes the 5th switch T5With the 7th switch T7It disconnects, low level signal causes first
Switch T1T is switched with third3Conducting, the first phase inverter K1The high level signal obtained after reverse phase causes second switch T2With the 4th
Switch T4It disconnects, the second phase inverter K2The low level signal obtained after reverse phase causes the 6th switch T6With the 8th switch T8Conducting；
Wherein, the first switch T after conducting1Cause the first signal L0It exports to the first output terminal OUT1, the third after conducting
Switch T3Cause second signal R0It exports to second output terminal OUT2, the 6th switch T after conducting6Cause second signal R0Output is extremely
Third output terminal OUT3, the 8th switch T after conducting8Cause the first signal L0It exports to the 4th output terminal OUT4；That is control unit
M is by the first signal L0Synchronism output is to the first output terminal OUT1With the 4th output terminal OUT4, by second signal R0Synchronism output is to
Two output terminal OUT2With third output terminal OUT3。
Control circuit provided in this embodiment, control circuit can be by the first signal such as left eye data signal synchronism outputs to two
A output terminal by second signal such as right eye data signal synchronism output to other two output terminal, and passes through control output first
The difference of signal and second signal synchronous output end, to cause the gate line in 3D display device that there are 4 kinds of scan modes, and then
Realize 4 kinds of states of eye tracking.That is, the present invention is not required to carry out special place to data source by image processing system
Reason, only by the way that the difference of the control circuit output signal synchronous output end is controlled to can be realized as 4 kinds of states that eye tracks, from
And solve the problems, such as that the 3D display screen cost of existing support eye tracking is higher.
The embodiment of the present invention two provides a kind of array substrate, which includes multiple grid line groups, the first grid
Pole driving circuit, second grid driving circuit, drive integrated circult and multiple control circuits, certainly, which further includes
Data line, pixel electrode and public electrode etc., details are not described herein.
As shown in figure 4, grid line groups include the first grid that arrow (i.e. the extending direction of data line) is arranged in order along Fig. 4
Polar curve G1, second gate line G2, third gate lines G3With the 4th gate lines G4, and multiple grid line groups arrow along Fig. 4 is arranged successively
Row.Wherein, gate line is electrically connected with the grid of the thin film transistor (TFT) in pixel, for providing turntable driving letter to respective pixel
Number.
First grid driving circuit 2 includes multiple first grid driving units 20, and first grid driving unit 20 includes the
One shift register 201 and the second shift register 202.First shift register 201 and corresponding first grid polar curve G1Connection,
For to corresponding first grid polar curve G1Input scanning drive signal.Second shift register 202 and corresponding third gate lines G3
Connection, for corresponding third gate lines G3Input scanning drive signal.
Second grid driving circuit 3 includes multiple second grid driving units 30, and second grid driving unit 30 includes the
Three shift registers 301 and the 4th shift register 302.Third shift register 301 and corresponding second gate line G2Connection,
For to corresponding second gate line G2Input scanning drive signal.4th shift register 302 and corresponding 4th gate lines G4
Connection, for corresponding 4th gate lines G4Input scanning drive signal.
Optionally, first grid driving circuit 2 and second grid driving circuit 3 are located at the both sides of array substrate, and first
Gate driving circuit 2 is located at the left side of array substrate, and second grid driving circuit 3 is located at the right side of array substrate, still, this hair
Bright to be not limited to that, in other embodiments, first grid driving circuit 2 can be located at the right side of array substrate, second gate
Pole driving circuit 3 can be located at the left side of array substrate.
Specifically, between each first shift register 201 in first grid driving circuit 2 it is cascade, the second shifting
It is cascade between bit register 202, is cascade between each third shift register 301 in second grid driving circuit 3
, between the 4th shift register 302 be cascade, and can be with forward scan between cascade shift register, can also be anti-
To scanning.
By taking forward scan as an example, as shown in figure 5, the first shift register in previous first grid driving unit 20
201 output terminal OUT5With the input terminal IN of the first shift register 201 in the latter first grid driving unit 205Connection,
The output terminal OUT of the second shift register 202 in previous first grid driving unit 206It is driven with the latter first grid
The input terminal IN of the second shift register 202 in unit 206Connection；
The output terminal OUT of third shift register 301 in previous second grid driving unit 307With the latter second
The input terminal IN of third shift register 301 in drive element of the grid 307It connects, in previous second grid driving unit 30
The 4th shift register 302 output terminal OUT8With the 4th shift register in the latter second grid driving unit 30
302 input terminal IN8Connection.
By taking the first shift register 201 as an example, the open signal of the 1st grade of the first shift register 201 is the first scanning
Initial signal, the open signal of n-th grade of first shift register 201 are the output signal of (n-1)th grade of shift register, wherein, n
To be more than 1 positive integer.
In other embodiments of the invention, when the displacement in first grid driving circuit 2 and second grid driving circuit 3
During register reverse scan, the output terminal OUT of the first shift register 201 in the latter first grid driving unit 205With
The input terminal IN of the first shift register 201 in previous first grid driving unit 205Connection, the latter first grid drive
The output terminal OUT of the second shift register 202 in moving cell 206It is moved with second in previous first grid driving unit 20
The input terminal IN of bit register 2026Connection；
The output terminal OUT of third shift register 301 in the latter second grid driving unit 307With previous second
The input terminal IN of third shift register 301 in drive element of the grid 307It connects, in the latter second grid driving unit 30
The 4th shift register 302 output terminal OUT8With the 4th shift register in previous second grid driving unit 30
302 input terminal IN8Connection.
In the present embodiment, drive integrated circult includes multiple signal line groups, i.e. main control chip is connect with multiple signal line groups,
The signal line group includes the first signal wire and second signal line, and the first signal wire exports the first signal, second signal line output the
Binary signal；Wherein, when 2D is shown, the first signal and the second signal are identical signal；During 3D display, the first signal and the second letter
Number for different signals, such as the first signal can be left eye image data signal, and second signal can be that right eye image data is believed
Number.
Control circuit in the present embodiment is the control circuit that any of the above-described embodiment provides.The control circuit includes first
Input terminal IN1~the four input terminal IN4, the first output terminal OUT1~the four output terminal OUT4, first switch T1~the eight switch T8、
First control terminal SW1, the second control terminal SW2, the first phase inverter K1With the second phase inverter K2。
Also, each control circuit in the present embodiment corresponds to the signal of control one signal line group output；Each control electricity
First input end IN in road1With the 4th input terminal IN4It is connected with corresponding first signal wire, the second input terminal IN2It is defeated with third
Enter to hold IN3It is connected with corresponding second signal line；First output terminal OUT of each control circuit1With the first shift register 201
Connection, second output terminal OUT2It is connect with the second shift register 202, third output terminal OUT3Connect with third shift register 301
It connects, the 4th output terminal OUT4It is connect with the 4th shift register 302.
Below by taking drive integrated circult is connect including three signal line group, that is, drive integrated circults with 6 signal wires as an example into
Row explanation, still, the present invention is not limited to this, and in other embodiments, drive integrated circult can be with four signal line groups
Connection, i.e., drive integrated circult is connect with 8 signal wires.
Above three signal line group includes initial signal line group, the first clock cable group and second clock signal line group.
Initial signal line group includes the first starting signal wire and the second initial signal line, and the first clock cable group is believed including the first clock
Number line and second clock signal wire, second clock signal line group include third clock cable and the 4th clock cable.
Wherein, the first starting signal wire and the second initial signal line are connect with the 1st control circuit, i.e. the first initial signal
Line is connect with the first input end of the control circuit and the 4th input terminal, for first input end and the 4th input terminal input the
One scanning initial signal, the second initial signal line connect with the second input terminal and third input terminal of the control circuit, for
Second input terminal and third input terminal input the second scanning initial signal.
First clock cable and second clock signal wire are connect with the 2nd control circuit, i.e. the first clock cable with
The first input end of the control circuit and the 4th input terminal connection, for first input end and the 4th input terminal input first when
Clock signal, second clock signal wire are connect with the second input terminal and third input terminal of the control circuit, for being inputted to second
End and third input terminal input second clock signal.
Third clock cable and the 4th clock cable are connect with the 3rd control circuit, i.e., third clock cable with
The first input end of the control circuit and the 4th input terminal connection, for first input end and the 4th input terminal input third when
Clock signal, the 4th clock cable are connect with the second input terminal and third input terminal of the control circuit, for being inputted to second
End and third input terminal input the 4th clock signal.
By taking forward scan as an example, as shown in figure 5, the first output terminal OUT of the 1st control circuit10With the 1st first grid
The input terminal IN of the first shift register 201 in pole driving unit 205Connection, second output terminal OUT20With the 1st first grid
The input terminal IN of the second shift register 202 in pole driving unit 206Connection, third output terminal OUT30With the 1st second gate
The input terminal IN of third shift register 301 in pole driving unit 307Connection, the 4th output terminal OUT40With the 1st second gate
The input terminal IN of the 4th shift register 302 in pole driving unit 307Connection.
First output terminal OUT of the 2nd control circuit11With the first clock signal of every one first shift register 201
Hold CK1Connection, second output terminal OUT21With the first clock signal CK of every one second shift register 2022End connection, third are defeated
Outlet OUT31With the first clock signal terminal CK of each third shift register 3013Connection, the 4th output terminal OUT41With every 1
First clock signal terminal CK of four shift registers 3024Connection.
First output terminal OUT of the 2nd control circuit12With the second clock signal of every one first shift register 201
Hold CK5Connection, second output terminal OUT22With the second clock signal end CK of every one second shift register 2026Connection, third are defeated
Outlet OUT32With the second clock signal end CK of each third shift register 3017Connection, the 4th output terminal OUT42With every 1
The second clock signal end CK of four shift registers 3028Connection.
Based on this, in the first scan mode of array substrate, the 1st control circuit is controlled by drive integrated circult
By the first scanning initial signal synchronism output to second output terminal OUT20With the 4th output terminal OUT40, by the second scanning starting letter
Number synchronism output is to the first output terminal OUT10With third output terminal OUT30；Control the 2nd control circuit that the first clock signal is same
Step is exported to second output terminal OUT21With the 4th output terminal OUT41, by second clock signal synchronism output to the first output terminal
OUT11With third output terminal OUT31；The 3rd control circuit is controlled to export third clock signal synchronization to second output terminal OUT22
With the 4th output terminal OUT42, the 4th clock signal synchronization is exported to the first output terminal OUT12With third output terminal OUT32。
Wherein, the control process and above-described embodiment of the 1st control circuit, the 2nd control circuit and the 3rd control circuit
The control process of description is identical, i.e., by controlling first switch T1~the eight switch T8On and off control output signal
Synchronous output end it is different, it is specific to control process details are not described herein.
By taking the first scanning initial signal and the second scanning initial signal as an example, due to the first output terminal OUT10It is moved by first
Bit register 201 and first grid polar curve G1Connection, third output terminal OUT30Pass through third shift register 301 and second gate line
G2Connection, therefore, the second scanning initial signal synchronism output to first grid polar curve G1With second gate line G2.Due to the second output
Hold OUT20Pass through the second shift register 202 and third gate lines G3Connection, the 4th output terminal OUT40Pass through the 4th shift LD
302 and the 4th gate lines G of device4Connection, therefore, the first scanning initial signal synchronism output to third gate lines G3With the 4th grid
Line G4。
Since same gate line is connect with the pixel of same a line, for providing signal, therefore, second to the pixel of same a line
Initial signal synchronism output is scanned to the first row pixel and the second row pixel, the first scanning initial signal synchronism output to the third line
Pixel and fourth line pixel.
When the first scanning initial signal is right eye image data signal R0, the second scanning initial signal is left eye image data
Signal L0When, the eye tracking mode shown in Fig. 1 a can be realized in above-mentioned scan mode.Wherein, first grid polar curve G1, second grid
Line G2, third gate lines G3With the 4th gate lines G4In first scanning initial signal, that is, right eye image data signal R0Or second sweep
Retouch initial signal i.e. left eye image data signal L0Sequence diagram as shown in Figure 6 a.
In second of scan mode of array substrate, the 1st control circuit is controlled by first by drive integrated circult
Initial signal synchronism output is scanned to second output terminal OUT20With third output terminal OUT30, the second scanning initial signal is synchronized
It exports to the first output terminal OUT10With the 4th output terminal OUT40；The 2nd control circuit is controlled to export the first clock signal synchronization
To second output terminal OUT21With third output terminal OUT31, by second clock signal synchronism output to the first output terminal OUT11With
Four output terminal OUT41；The 3rd control circuit is controlled to export third clock signal synchronization to second output terminal OUT22It is defeated with third
Outlet OUT32, the 4th clock signal synchronization is exported to the first output terminal OUT12With the 4th output terminal OUT42。
Similarly, by taking the first scanning initial signal and the second scanning initial signal as an example, when the first scanning initial signal is the right side
Eye viewdata signal R0, the second scanning initial signal is left eye image data signal L0When, figure can be realized in above-mentioned scan mode
Eye tracking mode shown in 1b.First grid polar curve G1, second gate line G2, third gate lines G3With the 4th gate lines G4In
One scanning initial signal, that is, right eye image data signal R0Or second scanning initial signal, that is, left eye image data signal L0Sequential
Figure is as shown in Figure 6 b.
In the third scan mode of array substrate, the 1st control circuit is controlled by first by drive integrated circult
Initial signal synchronism output is scanned to the first output terminal OUT10With third output terminal OUT30, the second scanning initial signal is synchronized
It exports to second output terminal OUT20With the 4th output terminal OUT40；The 2nd control circuit is controlled to export the first clock signal synchronization
To the first output terminal OUT11With third output terminal OUT31, by second clock signal synchronism output to second output terminal OUT21With
Four output terminal OUT41；The 3rd control circuit is controlled to export third clock signal synchronization to the first output terminal OUT12It is defeated with third
Outlet OUT32, the 4th clock signal synchronization is exported to second output terminal OUT22With the 4th output terminal OUT42；
Similarly, this scan mode can realize the eye tracking mode shown in Fig. 1 c.First grid polar curve G1, second gate line
G2, third gate lines G3With the 4th gate lines G4In first scanning initial signal, that is, right eye image data signal R0Or second scanning
Initial signal, that is, left eye image data signal L0Sequence diagram as fig. 6 c.
In the 4th kind of scan mode of array substrate, the 1st control circuit is controlled by first by drive integrated circult
Initial signal synchronism output is scanned to the first output terminal OUT10With the 4th output terminal OUT40, the second scanning initial signal is synchronized
It exports to second output terminal OUT20With third output terminal OUT30；The 2nd control circuit is controlled to export the first clock signal synchronization
To the first output terminal OUT11With the 4th output terminal OUT41, by second clock signal synchronism output to second output terminal OUT21With
Three output terminal OUT31；The 3rd control circuit is controlled to export third clock signal synchronization to the first output terminal OUT12It is defeated with the 4th
Outlet OUT42, the 4th clock signal synchronization is exported to second output terminal OUT22With third output terminal OUT32；
Similarly, this scan mode can realize the eye tracking mode shown in Fig. 1 d.First grid polar curve G1, second gate line
G2, third gate lines G3With the 4th gate lines G4In first scanning initial signal, that is, right eye image data signal R0Or second scanning
Initial signal, that is, left eye image data signal L0Sequence diagram as shown in fig 6d.
Wherein, for array substrate when showing 2D effects, the first scanning initial signal and the second scanning initial signal are identical
Data-signal, the first clock signal and second clock signal are identical data-signal, third clock signal and the 4th clock
Signal is identical data-signal.
When showing 3D effect, the first scanning initial signal and the second scanning initial signal are different data-signals, the
One clock signal and second clock signal are different data-signals, and third clock signal and the 4th clock signal are different numbers
It is believed that number, for example, the first scanning initial signal, the first clock signal and third clock signal are left eye image data signal L0,
Second scanning initial signal, second clock signal and the 4th clock signal are right eye image data signal R0。
In other embodiments, during shift register reverse scan, the first output terminal OUT of the 1st control circuit10With most
The input terminal IN of the first shift register 201 in the latter first grid driving unit 205Connection, second output terminal OUT20With
The input terminal IN of the second shift register 202 in the last one first grid driving unit 206Connection, third output terminal OUT30
With the input terminal IN of the third shift register 301 in the last one second grid driving unit 307Connection, the 4th output terminal
OUT40With the input terminal IN of the 4th shift register 302 in the last one second grid driving unit 307Connection.
Array substrate provided in this embodiment, control circuit can be by the first signal such as left eye data signal synchronism outputs to two
A output terminal by second signal such as right eye data signal synchronism output to other two output terminal, and passes through control output first
The difference of signal and second signal synchronous output end, to cause the gate line in 3D display device that there are 4 kinds of scan modes, and then
Realize 4 kinds of states of eye tracking.That is, array substrate provided in this embodiment is not required to through image processing system logarithm
According to source carry out specially treated, only by control the difference of the control circuit output signal synchronous output end can be realized as eye with
4 kinds of states of track, so as to solve the problems, such as that the 3D display screen cost of existing support eye tracking is higher.
The embodiment of the present invention three provides a kind of display panel, which includes what as above any embodiment provided
Array substrate.
The embodiment of the present invention four provides a kind of display device, which includes the display that above-described embodiment provides
Panel.
Display panel provided in this embodiment and 3D display device, control circuit can be by the first signal such as left eye data signals
Synchronism output by second signal such as right eye data signal synchronism output to other two output terminal, and passes through to two output terminals
The difference of control output the first signal and the second signal synchronous output end, to cause the gate line in 3D display device that there are 4 kinds
Scan mode, and then realize 4 kinds of states of eye tracking.That is, array substrate provided in this embodiment is not required to pass through figure
Picture processing system carries out data source specially treated, only by controlling the difference of the control circuit output signal synchronous output end just
It can realize 4 kinds of states of eye tracking, the 3D display screen cost of existing support eye tracking is higher to ask so as to solve
Topic.
Each embodiment is described by the way of progressive in this specification, the highlights of each of the examples are with other
The difference of embodiment, just to refer each other for identical similar portion between each embodiment.To the upper of the disclosed embodiments
It states bright, professional and technical personnel in the field is enable to realize or use the present invention.To a variety of modifications of these embodiments to ability
It will be apparent for the professional technician in domain, the general principles defined herein can not depart from the present invention's
In the case of spirit or scope, realize in other embodiments.Therefore, the present invention be not intended to be limited to it is shown in this article these
Embodiment, and it is to fit to the most wide range consistent with the principles and novel features disclosed herein.
Claims (11)
1. a kind of control circuit, which is characterized in that including first input end~the 4th input terminal, control unit, the first output terminal
~the four output terminal；The first input end and the 4th input terminal input the first signal, second input terminal and third input
End input second signal；
Described control unit is used for the first signal synchronism output to the second output terminal and the 4th output terminal, by described in
Second signal synchronism output is to first output terminal and third output terminal；
Alternatively, by the first signal synchronism output to the second output terminal and third output terminal, the second signal is same
Step is exported to first output terminal and the 4th output terminal；
Alternatively, by the first signal synchronism output to first output terminal and third output terminal, the second signal is same
Step is exported to the second output terminal and the 4th output terminal；
Alternatively, by the first signal synchronism output to first output terminal and the 4th output terminal, the second signal is same
Step is exported to the second output terminal and third output terminal；
Wherein, described control unit includes the switch of first switch~8th；
The first end of the first switch and the first end of the second switch are connect with first output terminal, and described first
The second end of switch is connect with the first input end, and the second end of the second switch is connect with the third input terminal, institute
The third end for stating first switch is connect with the first control terminal；
The first end of the third switch and the first end of the 4th switch are connect with the second output terminal, the third
The second end of switch is connect with second input terminal, and the second end of the 4th switch is connect with the 4th input terminal, institute
The third end for stating third switch is connect with the first control terminal；
The first end of 5th switch and the first end of the 6th switch are connect with the third output terminal, and the described 5th
The second end of switch is connect with the first input end, and the second end of the 6th switch is connect with the third input terminal, institute
The third end for stating the 5th switch is connect with the second control terminal；
The first end of 7th switch and the first end of the 8th switch are connect with the 4th output terminal, and the described 7th
The second end of switch is connect with second input terminal, and the second end of the 8th switch is connect with the 4th input terminal, institute
The third end for stating the 7th switch is connect with the second control terminal.
2. control circuit according to claim 1, which is characterized in that
The third end of the second switch is connect by the first phase inverter with first control terminal；
The third end of 4th switch is connect by the first phase inverter with first control terminal；
The third end of 6th switch is connect by the second phase inverter with second control terminal；
The third end of 8th switch is connect by the second phase inverter with second control terminal.
3. control circuit according to claim 2, which is characterized in that when the second switch, the 4th switch, the 6th switch
With the 8th switch conduction, when the first switch, third switch, the 5th switch and the 7th switch disconnect, described control unit will
The first signal synchronism output is to the second output terminal and the 4th output terminal, by the second signal synchronism output to described
First output terminal and third output terminal；
As the second switch, the 4th switch, the 5th switch and the 7th switch conduction, the first switch, third switch, the 6th
When switch and the 8th switch disconnect, described control unit is by the first signal synchronism output to the second output terminal and third
Output terminal, by the second signal synchronism output to first output terminal and the 4th output terminal；
As the first switch, third switch, the 5th switch and the 7th switch conduction, the second switch, the 4th switch, the 6th
When switch and the 8th switch disconnect, described control unit is by the first signal synchronism output to first output terminal and third
Output terminal, by the second signal synchronism output to the second output terminal and the 4th output terminal；
As the first switch, third switch, the 6th switch and the 8th switch conduction, the second switch, the 4th switch, the 5th
When switch and the 7th switch disconnect, described control unit is by the first signal synchronism output to first output terminal and the 4th
Output terminal, by the second signal synchronism output to the second output terminal and third output terminal.
4. control circuit according to claim 3, which is characterized in that when first control terminal and second control terminal
When inputting the first level signal, the second switch, the 4th switch, the 6th switch and the 8th switch conduction, the first switch,
Third switch, the 5th switch and the 7th switch disconnect；
When first control terminal and second control terminal input second electrical level signal when, the first switch, third switch,
5th switch and the 7th switch conduction, the second switch, the 4th switch, the 6th switch and the 8th switch disconnect；
When first control terminal inputs the first level signal, during second control terminal input second electrical level signal, described the
Two switches, the 4th switch, the 5th switch and the 7th switch conduction, the first switch, third switch, the 6th switch and the 8th are opened
Shutdown is opened；
When first control terminal inputs second electrical level signal, and second control terminal inputs the first level signal, described the
One switch, third switch, the 6th switch and the 8th switch conduction, the second switch, the 4th switch, the 5th switch and the 7th are opened
Shutdown is opened.
5. control circuit according to claim 2, which is characterized in that the first switch~8th is switched as PMOS crystal
Pipe or NMOS transistor, the first end are drain electrode, and the second end is source electrode, and the third end is grid.
6. a kind of array substrate, which is characterized in that including multiple grid line groups, first grid driving circuit, second grid driving
Circuit, drive integrated circult and multiple control circuits, the control circuit are Claims 1 to 5 any one of them control electricity
Road；
The grid line groups include the first grid polar curve, second gate line, third gate line and the 4th gate line that are arranged in order；
The first grid driving circuit includes multiple first grid driving units, and the first grid driving unit includes first
Shift register and the second shift register, first shift register are connected with the corresponding first grid polar curve, and second
Shift register is connected with the corresponding third gate line；
The second grid driving circuit includes multiple second grid driving units, and the second grid driving unit includes third
Shift register and the 4th shift register, the third shift register is connected with the corresponding second gate line, described
4th shift register is connected with corresponding 4th gate line；
The drive integrated circult includes multiple signal line groups, and the signal line group includes the first signal wire and second signal line,
First signal wire exports the first signal, and the second signal line exports second signal；
Each control circuit corresponds to the signal of the one signal line group output of control；First in each control circuit
Input terminal and the 4th input terminal and the corresponding first signal wire connection, the second input terminal and third input terminal and corresponding institute
State the connection of second signal line；First output terminal of each control circuit is connect with first shift register, and second is defeated
Outlet is connect with second shift register, and the third output terminal is connect with the third shift register, and the described 4th
Output terminal is connect with the 4th shift register；
Wherein, when 2D is shown, the first signal and the second signal are identical signal；During 3D display, first signal and
Second signal is different signal.
7. array substrate according to claim 6, which is characterized in that the first grid driving circuit and second grid drive
Shift register forward scan in dynamic circuit；
Wherein, first described in the output terminal of the first shift register in the previous first grid driving unit and the latter
The input terminal of the first shift register in drive element of the grid connects, and second in the previous first grid driving unit
The input terminal connection of the second shift register in first grid driving unit described in the output terminal and the latter of shift register；
Second grid described in the output terminal and the latter of third shift register in the previous second grid driving unit
The input terminal of third shift register in driving unit connects, the 4th displacement in the previous second grid driving unit
The input terminal connection of the 4th shift register in second grid driving unit described in the output terminal and the latter of register.
8. array substrate according to claim 6, which is characterized in that the first grid driving circuit and second grid drive
Shift register reverse scan in dynamic circuit；
Wherein, the output terminal of the first shift register in first grid driving unit described in the latter and previous described first
The input terminal of the first shift register in drive element of the grid connects, and second in first grid driving unit described in the latter
The output terminal of shift register is connect with the input terminal of the second shift register in the previous first grid driving unit；
The output terminal of third shift register in second grid driving unit described in the latter and the previous second grid
The input terminal of third shift register in driving unit connects, the 4th displacement in second grid driving unit described in the latter
The output terminal of register is connect with the input terminal of the 4th shift register in the previous second grid driving unit.
9. array substrate according to claim 7 or 8, which is characterized in that the drive integrated circult includes three signals
Line group, three signal line groups include initial signal line group, the first clock cable group and second clock signal line group；
When the signal line group is initial signal line group, and during the shift register forward scan, the corresponding control is electric
First output terminal on road is connect with the first shift register in the 1st first grid driving unit, second output terminal with the 1st
The second shift register in first grid driving unit connects, in third output terminal and the 1st second grid driving unit
Third shift register connects, and the 4th output terminal is connect with the 4th shift register in the 1st second grid driving unit；
When the signal line group is initial signal line group, and during the shift register reverse scan, the corresponding control is electric
First output terminal on road is connect with the first shift register in the last one first grid driving unit, second output terminal with most
The second shift register connection in the latter first grid driving unit, third output terminal drive with the last one second grid
Third shift register connection in unit, the 4th output terminal are posted with the 4th displacement in the last one second grid driving unit
Storage connects；
When the signal line group is the first clock cable group or second clock signal line group, the corresponding control circuit
First output terminal is connect with each first shift register, and second output terminal connects with each second shift register
It connects, the third output terminal is connect with each third shift register, and the 4th output terminal is moved with each described 4th
Bit register connects.
10. a kind of display panel, which is characterized in that including claim 6~9 any one of them array substrate.
11. a kind of 3D display device, which is characterized in that including display panel according to any one of claims 10.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1881474A (en) * | 2005-06-13 | 2006-12-20 | 三星电子株式会社 | Shift register and a display device including the shift register |
| US20080055293A1 (en) * | 2006-09-01 | 2008-03-06 | Au Optronics Corp. | Signal-driving system and shift register unit thereof |
| CN102779103A (en) * | 2011-05-12 | 2012-11-14 | 宏碁股份有限公司 | Switching circuit, electronic device and independent display card module |
| CN103000121A (en) * | 2012-12-14 | 2013-03-27 | 京东方科技集团股份有限公司 | Gate driving circuit, array substrate and display device |
| CN203909440U (en) * | 2014-04-30 | 2014-10-29 | 深圳市亿思达显示科技有限公司 | Liquid-crystal lens electronic grating and naked-eye three-dimensional display device |
-
2015
- 2015-09-21 CN CN201510602559.6A patent/CN105047126B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1881474A (en) * | 2005-06-13 | 2006-12-20 | 三星电子株式会社 | Shift register and a display device including the shift register |
| US20080055293A1 (en) * | 2006-09-01 | 2008-03-06 | Au Optronics Corp. | Signal-driving system and shift register unit thereof |
| CN102779103A (en) * | 2011-05-12 | 2012-11-14 | 宏碁股份有限公司 | Switching circuit, electronic device and independent display card module |
| CN103000121A (en) * | 2012-12-14 | 2013-03-27 | 京东方科技集团股份有限公司 | Gate driving circuit, array substrate and display device |
| CN203909440U (en) * | 2014-04-30 | 2014-10-29 | 深圳市亿思达显示科技有限公司 | Liquid-crystal lens electronic grating and naked-eye three-dimensional display device |
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