CN105045646B - A kind of cluster structured partial predicate is realized and compiling optimization method - Google Patents
A kind of cluster structured partial predicate is realized and compiling optimization method Download PDFInfo
- Publication number
- CN105045646B CN105045646B CN201510475324.5A CN201510475324A CN105045646B CN 105045646 B CN105045646 B CN 105045646B CN 201510475324 A CN201510475324 A CN 201510475324A CN 105045646 B CN105045646 B CN 105045646B
- Authority
- CN
- China
- Prior art keywords
- predicate
- clusters
- cluster
- instruction
- cpred
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Devices For Executing Special Programs (AREA)
Abstract
Optimization method is realized and compiled the present invention relates to a kind of cluster structured partial predicate, calculating cluster X clusters, Y clusters, Z clusters and T clusters including carrying out both-way communication with each upper internal memory by data/address bus, and address cluster U clusters, V clusters and the W clusters of both-way communication are carried out with each upper internal memory by address bus, predicate register file CPred, each predicate register file CPred calculated on cluster is set to control the predicated execution of each calculating cluster respectively respectively on X clusters, Y clusters, Z clusters and T clusters.Realization of the partial predicate of the present invention on cluster structured, each cluster that calculates possesses the independent ability for carrying out conditional operation, and the condition field each calculated on cluster is not required for being true and false entirely, enhances the ability of conditional parallel execution；In addition, the realization of general predicate then supplements cluster structured predicate mechanism, the flexibility ratio and versatility of cluster structured predicate mechanism are improved.
Description
Technical field
The present invention relates to architecture Design and optimization field, especially a kind of cluster structured part meaning
Word is realized and compiling optimization method.
Background technology
It is the basic obstacle for carrying out instruction-level exploitation that branch, which redirects, and predicated execution is the machine that a kind of effectively elimination branch redirects
System, it is that program is controlled to the conversion relied on to data dependence.The elimination that branch redirects can improve the feasibility of program
Can, from hardware architecture, the elimination that branch redirects can reduce hardware spending caused by branch prediction failure；From compiling
Aspect says that the elimination that branch redirects can expand scheduling scope, it is allowed to multiple condition routing instructions it is overlapping it is parallel perform, dig
The instruction-level parallelism across multiple Program paths is dug.
The cluster structured instruction level parallelism that can be effectively increased chip architecture, it is relative with centralized architecture
Answer, be the need of the high parallel data processing application development of the digital processing fields such as radar, radio communication, video, image, video
Will.It is widely used by the technology of cluster structured lifting chip instruction-level disposal ability, sub-clustering has become chip architecture
One important selection during design.For it is cluster structured progress predicate mechanism design, be cluster structured Parallelism exploiting must
Right demand.Predicated execution is a kind of hardware architecture technology, have various processor architecture support predicated execution, and these
The predicate mechanism that processor provides, there is point of total predicate and partial predicate again.
Total predicate is also mainly characterized by all instructions and can all provide an extra predicate source operation into general predicate
Number carrys out the final implementation effect of control instruction, and its major advantage there is provided the flexibility of maximum and be excavated by predicate and instructed
The parallel maximum capacity of level, its shortcoming is that hardware supported cost is excessive.And partial predicate then only provides sub-fraction instruction
Condition is performed, and limited support is only provided to predicated execution, especially uncontrollable memory access read-write operation, its major advantage
It is hardware design cost very little, can be easy to support.
Academic circles at present and industrial quarters are not yet systematically studied for cluster structured predicate and compiling support method.
The content of the invention
Efficiently realized for cluster structured predicate it is an object of the invention to provide a kind of, greatly improve conditional statement
Parallel execution potentiality, can more effectively improve the cluster structured part meaning of the execution efficiency of the circulation containing control of having ready conditions
Word is realized and compiling optimization method.
To achieve the above object, present invention employs following technical scheme：A kind of cluster structured partial predicate realize and
Optimization method is compiled, including carries out calculating cluster X clusters, Y clusters, Z clusters and the T of both-way communication with each upper internal memory by data/address bus
Cluster, and address cluster U clusters, V clusters and W clusters by address bus and each upper internal memory progress both-way communication, in X clusters, Y clusters, Z
Predicate register file CPred, each predicate register file CPred calculated on cluster is set to control each meter respectively on cluster and T clusters respectively
Calculate the predicated execution of cluster；
In compiling, its step is as follows：
(1) in Compiler Optimization rear end, for containing intermediate code caused by the circulation of control of having ready conditions, carrying out basic block choosing
Select process；
(2) detect whether loop body containing have ready conditions control writes memory access, it is no into the 3rd step if judged result is no
Then, continue to judge that can what be controlled by program transformation conditions to release writes memory access, if can eliminate, into the 3rd step, otherwise, enter
Enter the 4th step；
(3) carry out loop unrolling and build super block, carry out if conversions and the code building of partial predicate, finally produce sub-clustering
The efficient assembly code of structure division predicate；
(4) super block is built, if conversions and the code building of general predicate is carried out, finally produces cluster structured general predicate
Assembly code.
The if conversions of the partial predicate comprise the following steps：
(1) basic block distribution portion predicate is given, four masked bits Mask for calculating the predicate register file CPred on cluster are corresponded to
Numerical value when being equal to C, then normal execute instruction row, the instruction of ELSE instruction row is cancelled；
(2) branch's jump instruction is deleted；
(3) placement part predicate definition instruction, when four r1cond r2 calculated on cluster are true, assignment 1 gives CPred
[0], otherwise assignment 0 gives CPred [1].
The if conversions of the general predicate comprise the following steps：
(1) general predicate, using general predicate form, general predicate register file U1 masked bits Mask are distributed to basic block
When corresponding numerical value is equal to C, then normal execute instruction row, the instruction of ELSE instruction row is cancelled；
(2) branch's jump instruction is deleted；
(3) general predicate definition instruction is placed.
As shown from the above technical solution, advantages of the present invention is as follows：First, realization of the partial predicate on cluster structured,
Each cluster that calculates possesses the independent ability for carrying out conditional operation, and the condition field each calculated on cluster is not required for being true entirely
Vacation, the parallel execution potentiality of conditional statement are greatly improved, can more effectively improve the execution of the circulation containing control of having ready conditions
Efficiency；Second, the realization of general predicate then supplements cluster structured predicate mechanism, improves the spirit of cluster structured predicate mechanism
Activity and versatility.
Brief description of the drawings
Fig. 1 is sub-clustering system assumption diagram；
Fig. 2 is the supporting frame figure of general predicate；
Fig. 3 is the Compilation Method flow chart that CPred predicates are partial predicate.
Embodiment
As shown in figure 1, a kind of cluster structured partial predicate is realized and compiling optimization method, including by data/address bus with
Each upper internal memory carries out calculating cluster X clusters, Y clusters, Z clusters and the T clusters of both-way communication, and upper interior with each by address bus
Address cluster U clusters, V clusters and the W clusters of row both-way communication are deposited into, predicate register file is set respectively on X clusters, Y clusters, Z clusters and T clusters
CPred, each predicate register file CPred calculated on cluster control the predicated execution of each calculating cluster respectively.Predicate register file
CPred totally 8, each represents a predicate control register.It is numerous including adder, multiplier, shift unit etc. to calculate cluster
Computing resource, U clusters, V clusters, W clusters include address register, the generation of responsible address and specific accessing operation.In view of dividing
The parallel branch executive capability of clustering architecture, can be by all setting predicate register file CPred on X clusters, Y clusters, Z clusters, T clusters.
In order to support cluster structured total predicate model, predicate register file can be set on address cluster U clusters, V clusters, W clusters
CPred, the predicated execution of access instruction corresponding to control, and X clusters, Y clusters, Z clusters, the predicated execution of four calculating clusters of T clusters.
UVW predicates are that the predicated execution of the i.e. partial predicate control of the predicated execution that total predicate controls and CPred predicates is not
With.CPred predicated executions have performs the potentiality of multiple branch conditions simultaneously, X clusters, Y clusters, Z clusters, predicate control corresponding to T clusters
Make and be necessarily all true or be all false, i.e., the execution state on each cluster is simultaneously certain consistent, and can only be held during UVW predicated executions
The same condition of row, if the same instruction of X clusters, Y clusters, Z clusters, T clusters can be controlled to perform just, execution state is consistent
's.
UVW predicates are total predicates in cluster structured simple extension, and it has ability of predicated execution of four calculating clusters,
Traditional predicate compiling supporting frame that it is used is supported, as shown in Figure 2.CPred predicates have powerful parallel ability, and it is
Partial predicate has powerful X clusters, Y clusters, Z clusters, the predicate parallel control ability on four clusters of T clusters in cluster structured extension.
But the use of CPred predicates limitation is also harsher：I.e. condition is sentenced on the premise of without control memory access write command of having ready conditions
The necessary isomorphism of instruction that disconnected isomorphism and condition perform, this limitation bar can be met by the method construct of loop unrolling
Part, the conditional branching parallel ability for making full use of CPred to provide.
The predicate of UVW predicates form and CPred predicate forms definition instruction is respectively：
Us [k]=Um cond Un
CPred [k]=Rm cond Rn
Wherein k scope is 0~7.
Implication：If comparative result is true, just Us registers or CPred kth position are entered as 1.Two kinds of forms
Predicate control instruction and implication are as shown in table 1, table 2：
Table 1UVW predicates
Table 2CpTed controls predicate form
The shown two kind predicate form of Tables 1 and 2 is similar, but substantially has very big difference.UVW predicates form can be controlled
The most instructions of system, including access instruction, it is the way of realization of total predicate.And CPred predicate register files CPred is actually
It is four registers, respectively in four X clusters, Y clusters, Z clusters, T clusters clusters, the instruction of respective cluster is belonged on respective control instruction row
Perform, access instruction can not be controlled.And the CPred condition judgments positioned at four clusters are true and false sometimes not consistent, so four
The implementation status instructed on cluster is sometimes not consistent.So CPred predicates are partial predicates cluster structured a kind of efficiently real
Existing mode, it has X clusters, Y clusters, Z clusters, the executive capability of four clusters of T clusters.
In general predicate supporting frame is as shown in Fig. 2 mainly include four-stage：
First, basic block selection：Hyperblock is built, which basic block composition hyperblock should be determined first.
A kind of simple pattern is to assign all basic blocks of innermost loop as the part of super block, it is likely that reduction is procedural
Energy.Typically investigated using execution frequency, size and instruction features of the heuristic function to basic block, select suitable path
Form super block.First, exclude to perform the less basic block of frequency, the basic block larger for performing frequency, it optimizes and scheduling
Free space can be larger；Secondly, exclude the larger basic block of size of code, due to they are easier to cause resource shortage and shadow
Ring ILP raising；Finally, the basic block with side effect instruction such as subprocedure call, internal storage access is excluded, these instructions
In the presence of the performance that may reduce super block.
Second, structure super block (Hyperblock), the basic block of selection builds super block, it is necessary to meet：
(1) entrance basic block there are the controlling stream come from outside region, other basic blocks are all not present such
Controlling stream, this can meet the condition by tail reproduction technology；
(2) these basic blocks do not contain the interior loop of nesting, and the basic block of interior loop meets the condition, outer loop
Basic block need to meet the condition by recirculation gas stripper (loop peeling) technology.
3rd, If are changed：If conversions are selectively to eliminate bar in super block by the way that control dependence is converted into data dependence
The process of part jump instruction.Branch's jump instruction in super block can be divided into three types, and forward direction is redirected, redirects backward, exited
Redirect, wherein, forward direction redirect branch instruction jump in super block except enter basic block in addition to other basic blocks；Redirect branch backward
The entrance basic block of super block is jumped in instruction；Exit and redirect the basic block that branch instruction is jumped to outside super block.Here if conversions are only
To redirecting before conversion, do not change that backward to redirect and exit and redirect be because changing them additionally introduces useless predicate instruction, meeting
Cause the decline of performance.
There are many algorithms for If transfer processes, more famous is RK algorithms.If transfer processes typically have two substantially
Task.First, predicate is distributed to basic block, second, placing predicate definition instruction.The core of RK algorithms is R function and K functions, R letters
Number is responsible for distribution predicate, and K functions are responsible for placing predicate defining operation.RK algorithms can be divided into several stages：Calculate basic block
Set is dominated afterwards；Calculate the control Dependency Set of basic block；The control for decomposing each basic block relies on set, obtains R and K；According to
Function R is that basic block distributes predicate, and predicate definition is inserted into corresponding basic block according to function R；Delete it is all before to redirecting
Instruction, the instruction of super block is converted to predicate instruction.
4th, code building：The rear end ranks such as register distribution, Code schedule are carried out for the predicate intermediate code of formation
Section, form predicate assembly code.
In general predicate transfer process agreement predicate form be:
(1) predicate defines instruction type：P1P0=Rm cond Rn
Implication：If comparison condition is true, P1 is entered as 1, P0 and is entered as 0；If comparison condition is false, P1 is entered as 0,
P1 is entered as 1；
(2) predicate control instruction form：Rs=P1op Rm Rn
Implication：If P1 value is 1, normal perform is instructed；If P1 value is 0, the instruction is cancelled.
This agreement is very big with UVW predicates form and CPred predicate form difference, and to expression, both predicates are brought for this
Challenge.
The predicate model form that UVW predicates and CPred predicates are taken is：
(1) predicate abstraction model：CPred number of predicate register file is 16, totally 32 CPred pairs of complementary predicate registers
(P0, P1), (P2, P3) ..., (P14, P15), 0~7 of CPred or address predicate register file CPred (UVW) is corresponded to respectively；
(2) predicate intermediate representation：The predicate using general predicate section is taken to enter during the overwhelming majority of compiler back-end
Row intermediate representation；
(3) optimization limitation：In view of the predicate form of UVW predicates and CPred predicates, is closed excellent on the software flow of predicate
Change；
(4) when carrying out predicate register file CPred distribution, complementary predicate virtual register is posted in complementary physics predicate distributing
Storage CPred is to upper；
(5) before assembly code output, general predicate form is carried out to UVW predicates form or CPred predicate forms
The conversion stage.
The conditional parallel executive capability that actually CPred predicates provide is stronger than UVW predicate, and it can better profit from four
The calculation resources of cluster, although it can not control access instruction.If it can relax the scope of application of CPred instructions, more
The cyclical patterns of polymorphic type, which is converted to, can use CPred predicate mechanism forms, in theory, the property of program can be substantially improved
Energy.
As shown in figure 3, in compiling, its step is as follows：(1) in Compiler Optimization rear end, for containing control of having ready conditions
Intermediate code caused by circulation, carry out basic block selection course；(2) detect whether loop body containing have ready conditions control writes memory access,
If judged result is no, into the 3rd step, otherwise, continue to judge that can what be controlled by program transformation conditions to release writes visit
Deposit, if can eliminate, into the 3rd step, otherwise, into the 4th step；(3) carry out loop unrolling and build super block, carry out part meaning
The if conversions of word and code building, finally produce the efficient assembly code of cluster structured partial predicate；(4) super block is built, is carried out
The if conversions of general predicate and code building, finally produce the assembly code of cluster structured general predicate.
The if conversions of the partial predicate comprise the following steps：
(1) basic block distribution portion predicate is given, predicate instruction type is if CPred [Mask]==C do | | inst ...,
Meaning is：When numerical value is equal to C corresponding to the masked bits Mask of predicate register file CPred on four clusters, then normal execute instruction
OK, the instruction of ELSE instruction row is cancelled；The predicate register file CPred of four clusters value and corresponding predicated execution is not required for one
Cause；
(2) branch's jump instruction is deleted；
(3) placement part predicate definition instruction, it is as predicate defines instruction type：CPred [0]=r1cond r2, meaning
For：When r1cond r2 on four clusters are true, assignment 1 gives CPred [0], and otherwise assignment 0 gives CPred [1], the predicate of four clusters
Register CPred assignment can be different.
The if conversions of the general predicate comprise the following steps：
(1) general predicate, using general predicate form, general predicate register file U1 masked bits Mask are distributed to basic block
When corresponding numerical value is equal to C, then normal execute instruction row, the instruction of ELSE instruction row is cancelled；
(2) branch's jump instruction is deleted；
(3) general predicate definition instruction is placed.
In summary, the realization of partial predicate of the invention on cluster structured, each cluster that calculates possess independent progress
The ability of conditional operation, and the condition field each calculated on cluster is not required for being true and false entirely, enhances conditional parallel execution
Ability；In addition, the realization of general predicate then supplements cluster structured predicate mechanism, the spirit of cluster structured predicate mechanism is improved
Activity and versatility.
Claims (3)
1. a kind of cluster structured partial predicate is realized and compiling optimization method, it is characterised in that：Including by data/address bus with
Each upper internal memory carries out calculating cluster X clusters, Y clusters, Z clusters and the T clusters of both-way communication, and upper interior with each by address bus
Address cluster U clusters, V clusters and the W clusters of row both-way communication are deposited into, predicate register file is set respectively on X clusters, Y clusters, Z clusters and T clusters
CPred, each predicate register file CPred calculated on cluster control the predicated execution of each calculating cluster respectively；
In compiling, its step is as follows：
(1) in Compiler Optimization rear end, for containing intermediate code caused by the circulation of control of having ready conditions, carrying out basic block and selecting
Journey；
(2) detect whether loop body containing have ready conditions control writes memory access, if judged result is no, into the 3rd step, otherwise, after
What can continuous judgement be controlled by program transformation conditions to release writes memory access, if can eliminate, into the 3rd step, otherwise, into
Four steps；
(3) carry out loop unrolling and build super block, carry out if conversions and the code building of partial predicate, finally produce cluster structured
The efficient assembly code of partial predicate；
(4) super block is built, carries out if conversions and the code building of general predicate, finally produces the compilation of cluster structured general predicate
Code.
2. cluster structured partial predicate according to claim 1 is realized and compiling optimization method, it is characterised in that：It is described
The if conversions of partial predicate comprise the following steps：
(1) basic block distribution portion predicate, number corresponding to four masked bits Mask for calculating the predicate register file CPred on cluster are given
When value is equal to C, then normal execute instruction row, the instruction of ELSE instruction row is cancelled；
(2) branch's jump instruction is deleted；
(3) placement part predicate definition instruction, when four r1 cond r2 calculated on cluster are true, assignment 1 gives CPred [0], no
Then assignment 0 gives CPred [1].
3. cluster structured partial predicate according to claim 1 is realized and compiling optimization method, it is characterised in that：It is described
The if conversions of general predicate comprise the following steps：
(1) general predicate is distributed to basic block, using general predicate form, general predicate register file U1 masked bits Mask is corresponding
Numerical value when being equal to C, then normal execute instruction row, the instruction of ELSE instruction row is cancelled；
(2) branch's jump instruction is deleted；
(3) general predicate definition instruction is placed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510475324.5A CN105045646B (en) | 2015-08-06 | 2015-08-06 | A kind of cluster structured partial predicate is realized and compiling optimization method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510475324.5A CN105045646B (en) | 2015-08-06 | 2015-08-06 | A kind of cluster structured partial predicate is realized and compiling optimization method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105045646A CN105045646A (en) | 2015-11-11 |
| CN105045646B true CN105045646B (en) | 2018-04-03 |
Family
ID=54452210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510475324.5A Active CN105045646B (en) | 2015-08-06 | 2015-08-06 | A kind of cluster structured partial predicate is realized and compiling optimization method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105045646B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107239260B (en) * | 2017-05-11 | 2020-07-24 | 中国电子科技集团公司第三十八研究所 | Multi-predicate control and compiling optimization method for digital signal processor |
| CN109240701B (en) * | 2018-08-13 | 2022-06-28 | 湖南科技大学 | Predicate execution high-performance DSP-oriented instruction dependency analysis method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101382950A (en) * | 2008-09-26 | 2009-03-11 | 中山大学 | Body correlation method based on SWRL-Bridge-Peer model |
| CN102819569A (en) * | 2012-07-18 | 2012-12-12 | 中国科学院软件研究所 | Matching method for data in distributed interactive simulation system |
-
2015
- 2015-08-06 CN CN201510475324.5A patent/CN105045646B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101382950A (en) * | 2008-09-26 | 2009-03-11 | 中山大学 | Body correlation method based on SWRL-Bridge-Peer model |
| CN102819569A (en) * | 2012-07-18 | 2012-12-12 | 中国科学院软件研究所 | Matching method for data in distributed interactive simulation system |
Non-Patent Citations (2)
| Title |
|---|
| 《一种基于谓词执行优化技术的寄存器分配算法》;王凤芹，胡定磊，刘春林;<计算机研究与发展>;20060830;全文 * |
| 《谓词相关编译技术和深层代码优化》;芦运照;《中国博士学位论文全文数据库》;20070228;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105045646A (en) | 2015-11-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104820613B (en) | A kind of Compilation Method of heterogeneous polynuclear program | |
| CN104965761A (en) | Flow program multi-granularity division and scheduling method based on GPU/CPU hybrid architecture | |
| CN101655783B (en) | Forward-looking multithreading partitioning method | |
| CN105045646B (en) | A kind of cluster structured partial predicate is realized and compiling optimization method | |
| CN103559069B (en) | A kind of optimization method across between file processes based on algebra system | |
| Yin et al. | DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach | |
| CN101840329B (en) | Data parallel processing method based on graph topological structure | |
| CN103617049B (en) | code moving method based on complementary predicate | |
| CN112558977B (en) | Polyhedron optimization method oriented to heterogeneous many-core rear end based cost model | |
| Huynh et al. | Efficient custom instructions generation for system-level design | |
| Aldinucci et al. | Targeting heterogeneous architectures via macro data flow | |
| CN112527393A (en) | Instruction scheduling optimization device and method for master-slave fusion architecture processor | |
| CN109597619A (en) | A kind of adaptive compiled frame towards heterogeneous polynuclear framework | |
| CN110675088B (en) | Efficient division method for complex tasks of digital twin system | |
| Dai et al. | WideSA: A High Array Utilization Mapping Scheme for Uniform Recurrences on ACAP | |
| CN112783503A (en) | NumPy operation accelerated optimization method based on Arm framework | |
| Nourani et al. | Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems | |
| Ismail et al. | A parallel and concurrent implementation of Lin-Kernighan heuristic (LKH-2) for solving traveling salesman problem for multi-core processors using SPC 3 programming model | |
| Weiss et al. | Architectural improvements for a data-driven VLSI processing array | |
| Gupta et al. | Compilation techniques for a reconfigurable LIW architecture | |
| Pan et al. | Mobile Agents—The Right Vehicle for Distributed Sequential Computing | |
| Brezany et al. | Parallelization of irregular codes including out-of-core data and index arrays | |
| Dai et al. | WideSA: A High Array Utilization Mapping Scheme for Uniform Recurrences on the Versal ACAP Architecture | |
| Chen et al. | Branch merging for effective exploitation of instruction-level parallelism | |
| Jou et al. | PASS: A package for automatic scheduling and sharing pipelined data paths |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20191106 Address after: 5 / F, airborne center, 38 new area, No. 199, Xiangzhang Avenue, hi tech Zone, Hefei City, Anhui Province 230000 Patentee after: Anhui core Century Technology Co., Ltd. Address before: 230088, 199, camphor Road, hi tech Zone, Anhui, Hefei Patentee before: No.38 Inst., China Electronic Sci. & Tech. Group Co. |