CN105044607A - Battery module multichannel synchronous detection device - Google Patents
Battery module multichannel synchronous detection device Download PDFInfo
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- CN105044607A CN105044607A CN201510379556.0A CN201510379556A CN105044607A CN 105044607 A CN105044607 A CN 105044607A CN 201510379556 A CN201510379556 A CN 201510379556A CN 105044607 A CN105044607 A CN 105044607A
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Abstract
The invention provides a battery module multichannel synchronous detection device, which comprises a main controller, a signal detection module, an external communication interface module and a clock control system, wherein the main controller is connected with the battery module and the clock control system via the signal detection module and the external communication interface module respectively; and under effects of the clock control system, the main controller controls the signal detection module to synchronously detect parameters of each battery in the battery module. The detection device provided by the invention has a strong anti-interference ability; synchronous detection of multiple battery module parameters and synchronous and real-time detection of multiple parameters for each battery in the battery module can be realized; the channel number of the detection device is improved; and the device can be used by a user in a large-scaled synchronous detection situation.
Description
Technical field
The present invention relates to a kind of pick-up unit, specifically relating to a kind of isoparametric device of voltage, electric current and temperature for synchronously detecting each battery in battery modules.
Background technology
For current battery energy storage system, due to monomer battery voltage and appearance quantitative limitation, the series-parallel mode of usual employing cell forms battery modules, for guaranteeing that battery modules is functional and extending its serviceable life, need to manage electric battery and control, its prerequisite is must state parameter that is accurate and acquisition battery reliably.The voltage of battery, temperature and electric current are closely-related parameter with battery status, and therefore the test of the battery parameter such as the voltage of accurate cell, temperature and electric current has important effect for the assessment of battery status and safe early warning.
The measuring method of common battery modules monomer battery voltage has mechanical relay method, resistive voltage point platen press, photoelectric relay method and difference isolated amplifier method etc.Mechanical relay method is withstand voltage height, cost are low, but due to limited and low-response in mechanical relay serviceable life, are not suitable for testing fast for a long time; The cost of voltage method is low, measuring speed fast, but in multiple batteries cascade system, the more difficult adjustment of dividing ratios, have impact on measuring accuracy; Photoelectric relay method overcomes the shortcoming of traditional mechanical relay, but needs the timesharing of each road to measure during test, can not synchro measure; These method of testings, due to the shortcoming in real-time and synchronism, can not realize the assessment of electric battery string performance and state real-time and accurately.
Summary of the invention
In order to solve above-mentioned deficiency existing in prior art, the invention provides a kind of battery modules multi-channel synchronous pick-up unit, this device can realize under the effect of same trigger pip, multiple signal detection module synchronous working, all parameters of all battery modules of synchronous detection, improve detection synchronism and the real-time of battery modules parameter.
Technical scheme provided by the invention is: a kind of battery modules multi-channel synchronous pick-up unit, and its improvements are: described device comprises master controller, signal detection module, external communication interface module and clock control system; Described master controller is connected with described clock control system with described battery modules with described external communication interface module respectively by described signal detection module; Described master controller controls the parameter that described signal detection module synchronously detects each battery in described battery modules under the effect of described clock control system.
Preferably, described master controller connects two or more signal detection modules simultaneously, and each signal detection module is responsible for the Parametric Detection of all cells of a battery modules; Described parameter comprises voltage, electric current and temperature.
Further, described signal detection module comprises analog signal processing circuit, A/D convertor circuit, data processing circuit, synchronous conversion logic control circuit and clock circuit; The input end of described analog signal processing circuit is connected with described battery modules by sensor, and its output terminal is connected with the input end of A/D convertor circuit, and the output terminal of described A/D convertor circuit is connected with the input end of data processing circuit; Described master controller is bi-directionally connected with described data processing circuit and described clock circuit respectively, described clock circuit is bi-directionally connected with described synchronous conversion logic control circuit, and the output terminal of described synchronous conversion logic control circuit is connected with the control end of described A/D convertor circuit.
Further, described sensor comprises the voltage sensor of voltage, electric current and the temperature gathering cell respectively, current sensor and temperature sensor;
Described analog signal processing circuit comprises the voltage signal processing circuit, current signal treatment circuit and the processes temperature signal circuit that process voltage, electric current and temperature respectively;
Described sensor gathers the voltage of cell in described battery modules, temperature and current signal, and the signal collected is exported to analog signal processing circuit; A/D convertor circuit is exported to after described analog signal processing circuit processes to the received signal; The simulating signal received is converted to digital signal and exports to data processing circuit by described A/D convertor circuit; Described data processing circuit exports to master controller after recombinating to the data received according to communication protocol; The data of described master controller Received signal strength detection module are also uploaded to clock control system after recombinating to data and store;
Described synchronous conversion logic control circuit controls all A/D convertor circuit synchronous workings of individual signals detection module under the effect of described master controller;
Described master controller obtains the system clock of described clock control system by external communication interface module, and controls all signal detection module synchronous workings by described clock circuit.
Further, described analog signal processing circuit comprises the prime symmetric difference amplifying circuit, low-pass filter circuit, isolating amplifier circuit and the rear class differential amplifier circuit that connect successively; Described prime symmetric difference amplifying circuit receives the simulating signal that described sensor exports, suppress the undesired signal in described simulating signal, and export low-pass filter circuit to after described simulating signal being amplified, described isolating amplifier circuit is exported to after described low-pass filter circuit filtering, described isolating amplifier circuit is isolated described prime symmetric difference amplifying circuit and described rear class differential amplifier circuit, and gives described rear class differential amplifier circuit by the analog signal output that receives; Described rear class differential amplifier circuit in the input range of described A/D convertor circuit, and exports the range-adjusting of simulating signal that receives to described A/D convertor circuit.
Further, described prime symmetric difference amplifying circuit comprises resistance R
1, R
2, R
3, R
4, R
5, R
6, R
7, electric capacity C
1and C
2, clamp diode D
1, D
2, D
3, D
4with operational amplifier U
1;
One end of described resistance R1 is connected with one end of electric capacity C1 and one end of resistance R2 respectively, and its other end is connected with one end of described electric capacity C2 and one end of described resistance R4 respectively; The other end of described electric capacity C1 is connected rear ground connection with the other end of described electric capacity C2; The other end of described resistance R2 connects the negative electrode of one end of described resistance R3, the anode of described clamp diode D1 and described clamp diode D2 respectively; The negative electrode of described clamp diode D1 connects positive source, and the anode of described clamp diode D2 connects power cathode; The other end of described resistance R4 connects the negative electrode of one end of described resistance R5, the anode of described clamp diode D3 and described clamp diode D4 respectively; The negative electrode of described clamp diode D3 connects positive source, and the anode of described clamp diode D4 connects power cathode;
Described operational amplifier U
1in-phase input end connect the other end of described resistance R5 and one end of described resistance R7 respectively; Its inverting input connects the other end of described resistance R3 and one end of described resistance R6 respectively, and its output terminal connects the other end of described resistance R6, the other end ground connection of described resistance R7;
The two ends of described resistance R1 and described operational amplifier U
1output terminal be respectively input end and the output terminal of described prime symmetric difference amplifying circuit.
Further, described low-pass filter circuit comprises resistance R8 and electric capacity C3, one end of described resistance R8 is connected with the output terminal of described prime symmetric difference amplifying circuit, its other end is connected with one end of described electric capacity C3 and the input end of described isolating amplifier circuit respectively, the other end ground connection of described electric capacity C3.
Further, described isolating amplifier circuit comprises isolated amplifier U2, described isolated amplifier U2 comprises the electrode input end connecting described low-pass filter circuit output terminal, the negative input of ground connection and connect cathode output end and the cathode output end of described rear class differential amplifier circuit.
Further, described rear class differential amplifier circuit comprises resistance R
9, R
10, R
11, R
12, electric capacity C
4with operational amplifier U
3;
One end of described resistance R9 is connected with the cathode output end of described isolating amplifier circuit, and its other end is connected with the inverting input of described operational amplifier U3 with one end of described resistance R11, one end of described electric capacity C4 respectively; One end of described resistance R10 is connected with the negative input of described isolating amplifier circuit, and its other end is connected with the in-phase input end of described operational amplifier U3 with one end of described resistance R12 respectively; The output terminal of described operational amplifier connects the other end of described resistance R11 and the other end of described electric capacity C4 respectively; Another termination reference voltage source of described resistance R12.
Preferably, described master controller is on-site programmable gate array FPGA; Described clock control system is gps system or upper system, and described upper system is PC.
Compared with immediate technical scheme, the present invention has following marked improvement:
1) master controller is connected with clock control system with battery modules with external communication interface module respectively by signal detection module, can realize under same trigger pip, and the synchronous detection of multiple battery modules expands the detection scale of system.
2) each signal detection module is provided with synchronous conversion logic control circuit, the control of synchronous conversion logic control circuit main controller programmable gate array FPGA, the parallel logic computation performance of programmable gate array FPGA can be relied on, realize the synchronous detection of all parameters of all cells of a battery modules;
3) synchronous conversion logic control circuit is connected with master controller programmable gate array FPGA by clock circuit, signal detection module is made to obtain system clock by external communication interface module, ensure that individual signals detection module work clock is consistent with system clock, improve the accuracy of individual signals detection module work clock and the synchronism of all signal detection module work clocks;
4) setting of prime symmetric difference amplifying circuit improves the antijamming capability of analog signal processing circuit, improves the operating accuracy of signal detection module;
5) setting of isolating amplifier circuit improves the common-mode rejection ratio of analog signal processing circuit, protects data acquisition equipment simultaneously, ensure that personal safety.
Accompanying drawing explanation
Fig. 1 is the hardware block diagram of battery modules multi-channel synchronous pick-up unit;
Fig. 2 is the hardware block diagram of signal detection module;
Fig. 3 is the circuit theory diagrams of analog signal processing circuit.
Embodiment
Below in conjunction with Figure of description and example, content of the present invention is described further for a better understanding of the present invention.
A kind of battery modules multi-channel synchronous pick-up unit provided by the invention is as shown in Figure 1: comprise master controller, signal detection module, external communication interface module and clock control system; Described master controller is connected with described clock control system with described battery modules with described external communication interface module respectively by described signal detection module;
Signal detection module is by unified main controller controls, the time unification of the clock circuit of master controller primary responsibility signal detection module, to ensure the synchronism of all signal detection modules, and be uploaded to clock control system and store after the data gathered are recombinated;
Clock control system is gps system or upper system, and upper system refers to the server of PC or similar functions, and clock control system when data processing, each Frame identifies all if having time, so that the management of data.
Each signal detection module is responsible for the Parametric Detection of all cells in a battery modules, the hardware block diagram of signal detection module as shown in Figure 2: comprise analog signal processing circuit, A/D convertor circuit, data processing circuit, synchronous conversion logic control circuit and clock circuit; The input end of described analog signal processing circuit is connected with battery modules by sensor, and its output terminal is connected with the input end of A/D convertor circuit, and the output terminal of described A/D convertor circuit is connected with the input end of data processing circuit; Described master controller is bi-directionally connected with described data processing circuit and described clock circuit respectively, described clock circuit is bi-directionally connected with described synchronous conversion logic control circuit, and the output terminal of described synchronous conversion logic control circuit is connected with the control end of described A/D convertor circuit.
Described sensor comprises the voltage sensor of voltage, electric current and the temperature gathering cell respectively, current sensor and temperature sensor;
Described analog signal processing circuit comprises the voltage signal processing circuit, current signal treatment circuit and the processes temperature signal circuit that process voltage, electric current and temperature respectively;
Described sensor gathers the voltage of cell in described battery modules, temperature and current signal, and the signal collected is exported to analog signal processing circuit; A/D convertor circuit is exported to after described analog signal processing circuit processes to the received signal; The simulating signal received is converted to digital signal and exports to data processing circuit by described A/D convertor circuit; Described data processing circuit exports to master controller after recombinating to the data received according to communication protocol; Described master controller receives the data of all signal detection modules and is uploaded to clock control system after recombinating to data and stores;
Described synchronous conversion logic control circuit controls all A/D convertor circuit synchronous workings of individual signals detection module under the effect of described master controller, thus realizes real-time synchronization and detect the parameters such as the voltage of all cells in battery modules, electric current and temperature.
The good common mode interference that can realize analog signal processing circuit suppresses and differential mode interference suppresses, and lower to the susceptibility in simulating signal interference source; Its circuit theory diagrams as shown in Figure 3, comprise the prime symmetric difference amplifying circuit, low-pass filter circuit, isolating amplifier circuit and the rear class differential amplifier circuit that connect successively;
In Fig. 3, prime symmetric difference amplifying circuit carries out the process of signal prime by amplified analog signal, reduces the impact of undesired signal, improves the operating accuracy of whole circuit; Prime symmetric difference amplifying circuit is by resistance R
1, R
2, R
3, R
4, R
5, R
6, R
7, electric capacity C
1and C
2, clamp diode D
1, D
2, D
3, D
4with operational amplifier U
1composition.
Resistance R
1resistance selects 10k Ω, can reduce the susceptibility of whole circuit to undesired signal;
At the electric capacity C of operational amplifier homophase with anti-phase indirect identical capacitance
1and C
2and the mode of capacitance series point ground connection, the common mode interference of high frequency both can have been suppressed also can to suppress the differential mode interference of high frequency; In order to solve the signal delay that the sequential sampling that adopts in existing checkout equipment causes, capacitance chooses below 100pF;
In order to make whole circuit have very strong anti-common mode interference ability and the symmetry of holding circuit, adopt the resistance of same resistance at the in-phase input end of operational amplifier and inverting input, i.e. R
2=R
3=R
4=R
5, meanwhile, R
6=R
7=2R
2good symmetry is kept to make whole circuit;
In order to positive voltage and the negative voltage overvoltage protection of realizing circuit, prevent superpotential in collection from damaging late-class circuit, two division resistance R of input end
2and R
3, R
4and R
5indirect Clamp-on position diode D
1, D
2, D
3and D
4; In order to prevent unexpected superpotential ， Clamp-on position diode D
1, D
2, D
3and D
4select the fast diode (HSMS2702 of such as Agilent) with low inverse current.
In Fig. 3, low-pass filter circuit is by resistance R
8with electric capacity C
3composition, for carrying out filtering to signal.
In Fig. 3, isolating amplifier circuit adopts the isolated amplifier U of photoelectric coupling
2(HCPL7800A of such as Hewlett-Packard) carries out signal isolation, realizes the weak-signal measurement under high common mode voltage environment, is isolated tested battery modules and data acquisition system (DAS), improves common-mode rejection ratio, simultaneously protected data collecting device and personal safety.
In Fig. 3, rear class differential amplifier circuit is by resistance R
9, R
10, R
11, R
12, electric capacity C
4with operational amplifier U
3composition, rear class differential amplifier circuit is responsible for the amplitude conditioning of signal, and the reference voltage of AD conversion circuit coordinates, by the input range of treated simulating signal range-adjusting to AD; Operational amplifier adopts integrating circuit simultaneously, suppresses disturbing pulse and useless pulse; Realize the amplitude conditioning of signal with the measurement range meeting AD.
Battery analog parameter signal, after analog signal processing circuit, enters A/D convertor circuit and carries out analog to digital conversion and send into data processing circuit, in data processing circuit, carry out data recombination, makes data meet the laggard Serial Communication of requirement of communication protocol.A/D convertor circuit is connected with master controller FPGA with clock circuit by synchronous logic control circuit, control by FPGA (FieldProgrammableGateArray), FPGA is concurrent operation, ignore difference between AD conversion, can ensure that AD conversion is carried out simultaneously, realizes the synchronized sampling of multiple acquisition channel like this.
Clock circuit is responsible for the Real Time Clock Synchronization of whole signal detection module, signal detection module is when starting power-up initializing, the clock value of auto-loading system acquiescence, but the clock value of the not necessarily current time accurately of clock value now, and when acquisition system is huge, can not ensure that the moment that powers on of all signal detection modules is consistent, in order to enable clock circuit obtains clock value accurately, must calibrate clock module, the calibrating mode now adopted is connected to upper system or gps system by the external communication interface module of master controller, external communication interface module adopts CAN communication, system clock is accurately obtained by CAN communication bus.
These are only embodiments of the invention, be not limited to the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all applying within the right of the present invention awaited the reply.
Claims (10)
1. a battery modules multi-channel synchronous pick-up unit, is characterized in that: described device comprises master controller, signal detection module, external communication interface module and clock control system; Described master controller is connected with described clock control system with described battery modules with described external communication interface module respectively by described signal detection module; Described master controller controls the parameter that described signal detection module synchronously detects each battery in described battery modules under the effect of described clock control system.
2. a kind of battery modules multi-channel synchronous pick-up unit as claimed in claim 1, is characterized in that:
Described master controller connects two or more signal detection modules simultaneously, and each signal detection module is responsible for the Parametric Detection of all cells of a battery modules; Described parameter comprises voltage, electric current and temperature.
3. a kind of battery modules multi-channel synchronous pick-up unit as claimed in claim 1 or 2, is characterized in that:
Described signal detection module comprises analog signal processing circuit, A/D convertor circuit, data processing circuit, synchronous conversion logic control circuit and clock circuit; The input end of described analog signal processing circuit is connected with described battery modules by sensor, and its output terminal is connected with the input end of A/D convertor circuit, and the output terminal of described A/D convertor circuit is connected with the input end of data processing circuit; Described master controller is bi-directionally connected with described data processing circuit and described clock circuit respectively, described clock circuit is bi-directionally connected with described synchronous conversion logic control circuit, and the output terminal of described synchronous conversion logic control circuit is connected with the control end of described A/D convertor circuit.
4. a kind of battery modules multi-channel synchronous pick-up unit as claimed in claim 3, is characterized in that:
Described sensor comprises the voltage sensor of voltage, electric current and the temperature gathering cell respectively, current sensor and temperature sensor;
Described analog signal processing circuit comprises the voltage signal processing circuit, current signal treatment circuit and the processes temperature signal circuit that process voltage, electric current and temperature respectively;
Described sensor gathers the voltage of cell in described battery modules, temperature and current signal, and the signal collected is exported to analog signal processing circuit; A/D convertor circuit is exported to after described analog signal processing circuit processes to the received signal; The simulating signal received is converted to digital signal and exports to data processing circuit by described A/D convertor circuit; Described data processing circuit exports to master controller after recombinating to the data received according to communication protocol; The data of described master controller Received signal strength detection module are also uploaded to clock control system after recombinating to data and store;
Described synchronous conversion logic control circuit controls all A/D convertor circuit synchronous workings of individual signals detection module under the effect of described master controller;
Described master controller obtains the system clock of described clock control system by external communication interface module, and controls all signal detection module synchronous workings by described clock circuit.
5. a kind of battery modules multi-channel synchronous pick-up unit as claimed in claim 3, is characterized in that:
Described analog signal processing circuit comprises the prime symmetric difference amplifying circuit, low-pass filter circuit, isolating amplifier circuit and the rear class differential amplifier circuit that connect successively; Described prime symmetric difference amplifying circuit receives the simulating signal that described sensor exports, suppress the undesired signal in described simulating signal, and export low-pass filter circuit to after described simulating signal being amplified, described isolating amplifier circuit is exported to after described low-pass filter circuit filtering, described isolating amplifier circuit is isolated described prime symmetric difference amplifying circuit and described rear class differential amplifier circuit, and gives described rear class differential amplifier circuit by the analog signal output that receives; Described rear class differential amplifier circuit in the input range of described A/D convertor circuit, and exports the range-adjusting of simulating signal that receives to described A/D convertor circuit.
6. a kind of battery modules multi-channel synchronous pick-up unit as claimed in claim 5, is characterized in that:
Described prime symmetric difference amplifying circuit comprises resistance R
1, R
2, R
3, R
4, R
5, R
6, R
7, electric capacity C
1and C
2, clamp diode D
1, D
2, D
3, D
4with operational amplifier U
1;
One end of described resistance R1 is connected with one end of electric capacity C1 and one end of resistance R2 respectively, and its other end is connected with one end of described electric capacity C2 and one end of described resistance R4 respectively; The other end of described electric capacity C1 is connected rear ground connection with the other end of described electric capacity C2; The other end of described resistance R2 connects the negative electrode of one end of described resistance R3, the anode of described clamp diode D1 and described clamp diode D2 respectively; The negative electrode of described clamp diode D1 connects positive source, and the anode of described clamp diode D2 connects power cathode; The other end of described resistance R4 connects the negative electrode of one end of described resistance R5, the anode of described clamp diode D3 and described clamp diode D4 respectively; The negative electrode of described clamp diode D3 connects positive source, and the anode of described clamp diode D4 connects power cathode;
Described operational amplifier U
1in-phase input end connect the other end of described resistance R5 and one end of described resistance R7 respectively; Its inverting input connects the other end of described resistance R3 and one end of described resistance R6 respectively, and its output terminal connects the other end of described resistance R6, the other end ground connection of described resistance R7;
The two ends of described resistance R1 and described operational amplifier U
1output terminal be respectively input end and the output terminal of described prime symmetric difference amplifying circuit.
7. a kind of battery modules multi-channel synchronous pick-up unit as claimed in claim 5, is characterized in that:
Described low-pass filter circuit comprises resistance R8 and electric capacity C3, one end of described resistance R8 is connected with the output terminal of described prime symmetric difference amplifying circuit, its other end is connected with one end of described electric capacity C3 and the input end of described isolating amplifier circuit respectively, the other end ground connection of described electric capacity C3.
8. a kind of battery modules multi-channel synchronous pick-up unit as claimed in claim 5, is characterized in that:
Described isolating amplifier circuit comprises isolated amplifier U2, described isolated amplifier U2 comprises the electrode input end connecting described low-pass filter circuit output terminal, the negative input of ground connection and connect cathode output end and the cathode output end of described rear class differential amplifier circuit.
9. a kind of battery modules multi-channel synchronous pick-up unit as claimed in claim 5, is characterized in that:
Described rear class differential amplifier circuit comprises resistance R
9, R
10, R
11, R
12, electric capacity C
4with operational amplifier U
3;
One end of described resistance R9 is connected with the cathode output end of described isolating amplifier circuit, and its other end is connected with the inverting input of described operational amplifier U3 with one end of described resistance R11, one end of described electric capacity C4 respectively; One end of described resistance R10 is connected with the negative input of described isolating amplifier circuit, and its other end is connected with the in-phase input end of described operational amplifier U3 with one end of described resistance R12 respectively; The output terminal of described operational amplifier connects the other end of described resistance R11 and the other end of described electric capacity C4 respectively; Another termination reference voltage source of described resistance R12.
10. a kind of battery modules multi-channel synchronous pick-up unit as claimed in claim 1, is characterized in that:
Described master controller is on-site programmable gate array FPGA; Described clock control system is gps system or upper system, and described upper system is PC.
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