CN105007075A - Method for adjusting frequency and phases of clock - Google Patents
Method for adjusting frequency and phases of clock Download PDFInfo
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- CN105007075A CN105007075A CN201510390536.3A CN201510390536A CN105007075A CN 105007075 A CN105007075 A CN 105007075A CN 201510390536 A CN201510390536 A CN 201510390536A CN 105007075 A CN105007075 A CN 105007075A
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Abstract
The invention discloses a method for adjusting the frequency and the phases of a clock. The method comprises the steps that: an upper computer edits a waveform, frequency and phase command set for FPGA output according to the need, and then sends a related operation command to an FPGA processor through a serial port; the FPGA processor analyzes the command after receiving the response of the upper computer; the response of a test chip is waited; and after a response signal is received, the FPGA processor is informed of the related signal, and a test is performed. Compared with conventional methods, the method needs quite smaller NMOS and PMOS areas to achieve a same ESD level. In this way, the circuit area is reduced by reuse of an ESD protector and a driving tube. When the method is used for testing the chip, the frequency and the phases of the clock can be adjusted according to the need, so that the chip test is performed quickly and accurately; the method is only achieved by controlling the flow, the automated test can be performed, the test cost of the chip can be greatly reduced, and test equipment is small in occupied space.
Description
Technical field
The invention belongs to the technical field of chip testing, particularly the method for adjustment of clock frequency.
Background technology
In Circuits System, no matter be that picture is applied to the supercomputer of national defence or the little modulus conversion chip to thumbnail, all be unable to do without clock system, and no matter be quartz oscillator, temperature compensated oscillator or voltage controlled crystal oscillator etc., in different temperatures, humidity, under the factors such as electromagnetic interference, its output clock can not accomplish that frequency and phase place are strictly constant, and in practical application Circuits System need can steady operation under circumstances, now just need the clock redundancy of proof scheme system in the lab, a huge system is normally built by countless chip, in order to convenient test, testing equipment business large is at present as Tyke, Agilent and Pu Yuan have the oscilloscope that can produce various frequency signal source, some also support PLC technology, but both support PLC technology, the oscilloscope possessing again more than 100MHZ bandwidth is usually all expensive, large then four or five ten ten thousand, also want at least more than 10,000, expensive.
In addition market also there are some easy signal generators, sinusoidal signal is produced as built circuit by 555 oscillators, by shaping circuit, sinusoidal signal is transformed to square-wave signal again, again triangular wave is become to square-wave signal, so also can generate sine wave, square wave and the triangular signal that can produce characteristic frequency, also simple signal source can be generated additionally by monolithic die IC8038 or the mode such as single-chip microcomputer and AD converter combination, but the simple signal source that these implementation methods generate or bandwidth is little, or can not phase modulation.Test many is generally needed during chip prototype test, to guard against particularity, testing equipment is required to take up space in addition the smaller the better, to facilitate test, so volume is little, bandwidth is high, low price, the programmable signal source equipment of support have large demand in chip testing field.
Summary of the invention
For solving the problem, the object of the present invention is to provide a kind of method for adjusting clock frequency and phase place, the method can adjust clock frequency and phase place as required, can carry out chip testing quickly and accurately, reduces chip testing cost.
Another object of the present invention is to provide a kind of method for adjusting clock frequency and phase place, and the method realizes only by control flow, and except FGPA, do not increase extra hardware, equipment occupation space is little.
Further object of the present invention is to provide a kind of method for adjusting clock frequency and phase place, and the method supports PLC technology, and conveniently debug at a distance, device hardware cost is low in addition, and bandwidth is high, greatly can improve chip testing efficiency.
For achieving the above object, technical scheme of the present invention is as follows.
For adjusting a method for clock frequency and phase place, it is characterized in that the method comprises the steps:
101, host computer is edited as required waveform, frequency and phase command collection that FPGA exports, then by serial ports, associative operation instruction is sent to FPGA processor;
102, after FPGA processor receives host computer response, order is resolved; Wait for the response of chip to be tested;
103, after receiving answer signal, tell FPGA processor corresponding signal, carry out parsing to corresponding data and send to host computer, host computer is analyzed the signal detected and set point, detects clock frequency and whether arrives set point;
104, clock frequency arrives set point, then test.
In 101 described steps, the output frequency of FPGA is produced by 200MHZ clock division, and the work clock of host computer and FPGA is 25MHZ.
Further, described envelope 25MHZ crystal oscillator frequency, IP kernel through FPGA carries out frequency multiplication generation, production method is: the relative crystal oscillator of locking phase is zero, when needs produce characteristic frequency, FPGA processor requires to converse divide ratio according to incoming frequency, and the execution of program modules of FPGA selects frequency division scheme to carry out frequency division according to the value of divide ratio, produces the frequency needed.
Further, in described 103 steps, phase adjusted is included further after carrying out frequency division, phase adjusted carries out phase deviation to signal, so-called phase deviation refer to real-time signal relative to front signal generation phase deviation, described host computer and FPGA do not need to have deposited Wave data in advance, when performing clock phase shift operation, host computer can turn to temporal delay the variable quantity of phase place, reduction formula is as follows: Tdealy=TS/360*phase, in formula, TS is present clock period, and phase is the phase value wanting phase shift.
The understanding of formula is very simple, and when the clock cycle is TS, full width phase place is 360 degree, and therefore the time delay values of the change correspondence of 1 degree occurs phase place is TS/360, needs mobile how many phase places, is just multiplied by corresponding coefficient with phase.When system carries out clock phase shift, before the delay value that phase place converses being added on the clock cycle, the divide ratio made new advances that converts carries out clock division.
Described phase adjusted, just performs new clock division scheme on the half period, after the cycle also by the work of coefficient frequency division scheme before.
Method provided by the present invention is when chip testing, can adjust clock frequency and phase place as required, so that chip testing can be carried out quickly and accurately, realize only by control flow, automatic test can be carried out, can greatly reduce chip testing cost, and testing equipment takes up room little.
And the method supports PLC technology, conveniently debug at a distance, device hardware cost is low in addition, and bandwidth is high, greatly can improve chip testing efficiency.
Accompanying drawing explanation
Fig. 1 is the hardware structure diagram that the present invention implements.
Fig. 2 is the software control flow chart that the present invention implements.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Shown in Fig. 1, for the hardware configuration platform that the present invention realizes, mainly include host computer and fpga chip, wherein, the elementary fpga chip of current altera all has processor IP nuclear NIOSII, during the work of this equipment, NIOSII is as master controller, NIOSII is by serial ports and the intercommunication of host computer Active Tcl software interconnections, Active Tcl is Tcl development environment, Active Tcl comprises many useful expanding packet, Tcl is a kind of very general script, and it almost can explain operation on all platforms.First on host computer ActiveTcl, the waveform, frequency and the phase command collection that need FPGA to export is editted as required during test, then by serial ports, associative operation instruction is sent to processor NIOSII, after processor receives host computer response, order is resolved, tell that FPGA execution of program modules performs associative operation, meanwhile FPGA detection module is waiting for the response of chip to be tested always.After detection module receives answer signal, corresponding signal is told the processor NIOSII of FPGA, NIOSII carries out parsing to corresponding data and sends to host computer, and host computer is analyzed the signal detected and desired value, determines that next step test still terminates test.
Concrete control flow is:
101, host computer is edited as required waveform, frequency and phase command collection that FPGA exports, then by serial ports, associative operation instruction is sent to FPGA processor.
102, after FPGA processor receives host computer response, order is resolved; Wait for the response of chip to be tested.
103, after receiving answer signal, tell FPGA processor corresponding signal, carry out parsing to corresponding data and send to host computer, host computer is analyzed the signal detected and set point, detects clock frequency and whether arrives set point.
104, judge whether to need to carry out phase adjusted, detect phase shift after phase adjusted further and whether reach set point.
105, clock frequency arrives set point, then test.
Application claims possesses generation clock and clock phase offset functions, during concrete enforcement, FPGA output frequency is produced by 200MHZ clock division, the work clock of whole system is 25MHZ, the production method of 200MHZ clock is that 25MHZ crystal oscillator frequency carries out frequency multiplication generation through the IP kernel PLL of FPGA, the relative crystal oscillator of locking phase is zero, when needs produce characteristic frequency, NIOSII requires to converse divide ratio according to incoming frequency, frequency division by odd integers is had in FPGA execution of program modules, even frequency division and fractional frequency division function items, execution of program modules selects optimum frequency division scheme according to the value of divide ratio.
Realizing phase adjusted is important composition part of the present invention, phase adjusted carries out phase deviation to signal, so-called phase deviation refer to real-time signal relative to front signal generation phase deviation, the method of generation phase shift known is at present the time zero changing signal, first depositing Wave data in systems in which, when phase operation message being detected, having conversed delay time value according to phase operation, postpone periodic waveform during the next repetition period and occur starting point, the phase shift operation of clock can be realized.The present invention does not need previously to have deposited Wave data, when performing clock phase offset operation, host computer can turn to temporal delay the variable quantity of phase place, and reduction formula is as follows: Tdealy=TS/360*phase, in formula, TS is present clock period, and phase is the phase value wanting phase shift.The understanding of formula is very simple, and when the clock cycle is TS, full width phase place is 360 degree, and therefore the time delay values of the change correspondence of 1 degree occurs phase place is TS/360, needs mobile how many phase places, is just multiplied by corresponding coefficient with phase.When the present invention carries out clock phase shift, before the delay value that phase place converses being added on the clock cycle, the divide ratio that makes new advances of converting carries out clock division, and upper guarantee of now design just performs new clock division scheme on the half period, after the cycle also work by coefficient frequency division scheme before.
In addition, the system of FPGA own can only produce square wave, also often needs to use triangular wave and sine wave in practical application, at this moment, by integrating circuit, square wave can be become triangular wave, by active filter, triangular wave is converted to sine wave, the signal controlling conversion is provided by FPGA.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1., for adjusting a method for clock frequency and phase place, it is characterized in that the method comprises the steps:
101, host computer is edited as required waveform, frequency and phase command collection that FPGA exports, then by serial ports, associative operation instruction is sent to FPGA processor;
102, after FPGA processor receives host computer response, order is resolved; Wait for the response of chip to be tested;
103, after receiving answer signal, tell FPGA processor corresponding signal, carry out parsing to corresponding data and send to host computer, host computer is analyzed the signal detected and set point, detects clock frequency and whether arrives set point;
104, clock frequency arrives set point, then test.
2. as claimed in claim 1 for adjusting the method for clock frequency and phase place, it is characterized in that, in 101 described steps, the output frequency of FPGA is produced by 200MHZ clock division, the work clock of host computer and FPGA is 25MHZ.
3. as claimed in claim 2 for adjusting the method for clock frequency and phase place, it is characterized in that described envelope 25MHZ crystal oscillator frequency, IP kernel through FPGA carries out frequency multiplication generation, production method is: the relative crystal oscillator of locking phase is zero, when needs produce characteristic frequency, FPGA processor requires to converse divide ratio according to incoming frequency, and the execution of program modules of FPGA selects frequency division scheme to carry out frequency division according to the value of divide ratio, produces the frequency needed.
4. as claimed in claim 3 for adjusting the method for clock frequency and phase place, it is characterized in that in described 103 steps, phase adjusted is included further after carrying out frequency division, phase adjusted carries out phase deviation to signal, so-called phase deviation refer to real-time signal relative to front signal generation phase deviation, when performing clock phase offset operation, host computer can turn to temporal delay the variable quantity of phase place, reduction formula is as follows: Tdealy=TS/360*phase, in formula, TS is present clock period, and phase is the phase value wanting phase shift.
5. as claimed in claim 4 for adjusting the method for clock frequency and phase place, it is characterized in that described phase adjusted, just on the half period, perform new clock division scheme, after the cycle also work by coefficient frequency division scheme before.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107765164A (en) * | 2017-09-28 | 2018-03-06 | 国营芜湖机械厂 | A kind of circuit board high-frequency signal method of adjustment |
| CN110690641A (en) * | 2019-10-11 | 2020-01-14 | 中国船舶重工集团公司第七0七研究所 | Reference frequency source device and method for cold atom interferometer laser output control |
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2015
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| US20020007428A1 (en) * | 1998-12-18 | 2002-01-17 | Kendell Alan Chilton | Data assembler/disassembler |
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| CN107765164A (en) * | 2017-09-28 | 2018-03-06 | 国营芜湖机械厂 | A kind of circuit board high-frequency signal method of adjustment |
| CN110690641A (en) * | 2019-10-11 | 2020-01-14 | 中国船舶重工集团公司第七0七研究所 | Reference frequency source device and method for cold atom interferometer laser output control |
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Application publication date: 20151028 |