CN105006495B - Method for producing selective nanometer textured silicon photocell - Google Patents
Method for producing selective nanometer textured silicon photocell Download PDFInfo
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- CN105006495B CN105006495B CN201510346116.5A CN201510346116A CN105006495B CN 105006495 B CN105006495 B CN 105006495B CN 201510346116 A CN201510346116 A CN 201510346116A CN 105006495 B CN105006495 B CN 105006495B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 176
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 172
- 239000010703 silicon Substances 0.000 title claims abstract description 172
- 238000004519 manufacturing process Methods 0.000 title abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 77
- AIYUHDOJVYHVIT-UHFFFAOYSA-M caesium chloride Chemical compound [Cl-].[Cs+] AIYUHDOJVYHVIT-UHFFFAOYSA-M 0.000 claims abstract description 49
- MZFIXCCGFYSQSS-UHFFFAOYSA-N silver titanium Chemical compound [Ti].[Ag] MZFIXCCGFYSQSS-UHFFFAOYSA-N 0.000 claims abstract description 23
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 claims abstract description 22
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 238000005530 etching Methods 0.000 claims abstract description 15
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000005245 sintering Methods 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 57
- 239000002184 metal Substances 0.000 claims description 57
- 238000005516 engineering process Methods 0.000 claims description 15
- 238000001771 vacuum deposition Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000001020 plasma etching Methods 0.000 claims description 13
- 239000010409 thin film Substances 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 10
- 238000002207 thermal evaporation Methods 0.000 claims description 10
- 239000007789 gas Substances 0.000 claims description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 8
- 238000001704 evaporation Methods 0.000 claims description 7
- 230000008020 evaporation Effects 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 230000000694 effects Effects 0.000 claims description 6
- 239000002253 acid Substances 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000008367 deionised water Substances 0.000 claims description 4
- 229910021641 deionized water Inorganic materials 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 238000011161 development Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 3
- 240000007594 Oryza sativa Species 0.000 claims description 2
- 235000007164 Oryza sativa Nutrition 0.000 claims description 2
- 229910003978 SiClx Inorganic materials 0.000 claims description 2
- 235000009566 rice Nutrition 0.000 claims description 2
- 230000003628 erosive effect Effects 0.000 claims 1
- 230000007423 decrease Effects 0.000 abstract description 9
- 230000008569 process Effects 0.000 abstract description 9
- 238000007796 conventional method Methods 0.000 abstract description 7
- 238000009776 industrial production Methods 0.000 abstract 1
- 238000007747 plating Methods 0.000 abstract 1
- 238000000233 ultraviolet lithography Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 31
- 229910052792 caesium Inorganic materials 0.000 description 3
- TVFDJXOCXUVLDH-UHFFFAOYSA-N caesium atom Chemical compound [Cs] TVFDJXOCXUVLDH-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005660 chlorination reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001338 self-assembly Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000005518 electrochemistry Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002061 nanopillar Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 125000004437 phosphorous atom Chemical group 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Sustainable Development (AREA)
- Sustainable Energy (AREA)
- Life Sciences & Earth Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Photovoltaic Devices (AREA)
Abstract
The invention discloses a method for producing a selective nanometer textured silicon photocell. The method comprises: performing phosphorus oxychloride diffusion on a silicon chip in order to form a P-N junction structure; removing the P-N junction structure on the back surface and the side surface of the silicon chip; vapor plating a titanium silver layer on the front surface of the silicon chip to form a metallic gate line electrode and forming an aluminum back electrode layer on the back surface of the silicon chip; forming a cesium chloride nanometer circular island structure on the metallic gate line electrode and the surface of the silicon chip uncovered with the metallic gate line electrode, etching the silicon chip by using the cesium chloride nanometer circular island structure as a mask, transferring the cesium chloride nanometer circular island structure to the surface of the silicon chip, removing the cesium chloride nanometer circular island structure, and obtaining a silicon nanometer cylindrical structure on the surface of the silicon chip uncovered with the metallic gate line electrode; performing high-temperature sintering in order that the metallic gate line electrode and the silicon chip form ohmic contact. Compared with a conventional method, the method eliminates steps of ultraviolet lithography and alignment, simplifies process programs, decreases cost, reduces process difficulty, and is more suitable for industrial production.
Description
Technical field
The invention belongs to micron/nano semiconductor microactuator processing technique field, particularly a kind of selectivity nano texture SiClx light
The manufacture method of battery.
Background technology
Nano-array is a kind of new surface texture, has huge industry to answer in the many such as solar cell, led fields
With nanotexturing have the excellent characteristic reducing visible reflectance and improving spectral response.The nanotexturing sun now
Battery progressively commercialization, the nanotexturing solar cell of routine, is all by front surface entirety texturing, gate line electrode covers
Cover on the surface of textured silicon, this electrode form can not form good Ohmic contact, to the light improving battery
Electric transformation efficiency is unfavorable.
In order to overcome the nanotexturing problem that can not form good Ohmic contact, research worker have invented selectivity
Nanotexturing silicon cell, only carries out in the region in addition to gate line electrode nanotexturing, and metal grid lines electrode covers
Lid under silicon chip remain intact silicon structure, do not etch nano column array [d.kumar, s.k.srivastava, p.k.singh,
M.husain, v.kumar, sol.energy mater.sol.cells 98,215 (2011) and j.liu, x.zhang,
m.ashmkhan,g.q.dong,y.liao,b.wang,t.c.zhang,f.t.yi,sol.energy 105,274(2014)].
This electrode structure is while making full use of the characteristic of nanotexturing reduction reflection it is thus also avoided that the whole nanometer of front surface is knitted
The drawbacks of Ohmic contact that structure brings is bad, reduces series resistance, increases Ohmic contact, improves the opto-electronic conversion of solar cell
Efficiency.
Normal practice for this selectivity nano texturing silicon cell is: first produces photoresist in silicon chip surface
Gate patterns and alignment mark figure, shield during nanotexturing；Then carry out nanotexturing, including use
Cesium chloride nano island self-assembling technique or electrochemistry wet etching etc.；Then, p-n junction is prepared using thermal diffusion or additive method
Structure；Finally, hollow out metal mask plate gate patterns are passed through alignment mark with the silicon gate figure on silicon chip, use vacuum
The method evaporation titanium of plated film and silver, make selectivity grid.This conventional method uses ultraviolet photolithographic and set lithography, a side
Face, technique is loaded down with trivial details, also can introduce the impurity such as photoresist during ultraviolet photolithographic, affects electrode efficiency；On the other hand, for
Not only thin but also long grid linear, accurate alignment also has great difficulty.
Content of the invention
(1) technical problem to be solved
In view of this, present invention is primarily targeted at providing a kind of making side of selectivity nano texturing silicon cell
Method, to reduce the step such as ultraviolet photolithographic and alignment in conventional method, simplifies preparation technology, reduces cost of manufacture.
(2) technical scheme
For reaching above-mentioned purpose, the invention provides a kind of method making selectivity nano texturing silicon cell, should
Selectivity nano texturing silicon cell be only except metal grid lines electrode nanotexturing with the silicon chip of exterior domain, in metal
Silicon chip under gate line electrode covers remains intact silicon structure, does not etch nano column array；The method includes:
Step 1: phosphorus oxychloride diffusion is carried out to silicon chip, forms p-n junction structure in front side of silicon wafer, the back side and side；
Step 2: remove the p-n junction structure of silicon chip back side and side, and remove the silicon dioxide layer of front side of silicon wafer；
Step 3: form metal grid lines electrode in front side of silicon wafer evaporation titanium silver layer, and form aluminum back electrode in silicon chip back side
Layer；
Step 4: grow cesium chloride thin film in the silicon chip surface being formed with metal grid lines electrode, in metal grid lines electricity after development
The silicon chip surface not covered on pole and by metal grid lines electrode forms cesium chloride nanometer and justifies island structure, then with cesium chloride nanometer
Circle island structure is mask etching silicon chip, cesium chloride nanometer circle island structure is transferred on silicon face, removes cesium chloride nanometer and justify island
Structure, obtains silicon nanometer column structure in the silicon chip surface not covered by metal grid lines electrode；
Step 5: high temperature sintering, make metal grid lines electrode form Ohmic contact with silicon chip.
In such scheme, described silicon chip adopts p-type silicon chip, thickness 0.2-0.5 millimeter, and resistivity is 1-3 ω cm, surface
For single-sided polishing, burnishing surface is front, and non-burnishing surface is the back side.
In such scheme, described in step 1, silicon chip is carried out with phosphorus oxychloride diffusion and is realized using the method for thermal diffusion, thermal expansion
Scattered condition is: in 850 degree of diffusion furnaces, it is passed through the nitrogen 100sccm carrying phosphorus oxychloride, spreads 13 minutes, form p-n junction,
Square resistance is 30 ω/, and junction depth is about 400 nanometers.
In such scheme, described in step 2, remove the p-n junction structure using plasma etching of silicon chip back side and side
Method is realized, and the described silicon dioxide layer removing front side of silicon wafer adopts Fluohydric acid. to realize.
In such scheme, it is deposited with titanium silver layer in front side of silicon wafer described in step 3 and adopts the method for vacuum coating to realize, described
Form aluminum back electrode layer in silicon chip back side to realize by the way of vacuum coating.
In such scheme, the described method realization adopting vacuum coating in front side of silicon wafer evaporation titanium silver layer, is to utilize hollow out
Metal mask coating technique prepares metal gates in front side of silicon wafer, covers the hollow out metal mask with electrode patterning structure first
Cover in front side of silicon wafer, then adopt the method for thermal evaporation to evaporate 1 micron of thick titanium silver layer as metal grid lines electricity in front side of silicon wafer
Pole.
In such scheme, described silicon chip back side formed aluminum back electrode layer realized by the way of vacuum coating, be in silicon
The piece back side adopts the method for thermal evaporation to prepare the aluminum back electrode layer of 200 nanometer thickness.
In such scheme, described step 4 includes: the silicon chip being formed with metal grid lines electrode is put into vacuum coating cavity
Interior, thermal evaporation cesium chloride thin film, 100 nanometers of thickness；Into cavity, after cesium chloride thin film has plated, it is passed through the gas of certain humidity,
In holding chamber body, relative humidity is 35%, 30 minutes, and cesium chloride is reunited under the effect of humidity gas, in metal grid lines electrode
On and the silicon chip surface that do not covered by metal grid lines electrode form the nanometer cesium chloride peninsular structure being similar to water droplet one by one, put down
All a diameter of 150 nanometers；With cesium chloride island structure as mask, etch silicon using plasma etching technology, by cesium chloride structure
Transfer on silicon face, etching condition is: sf6:c4f8: he=60:150:10sccm, operating pressure 4pa, exciting power 400
Watt, substrate bias power is 30 watts, etch period 30 seconds；After the completion of silicon face etching, sample is put in deionized water and soaks 2 points
Clock, remaining cesium chloride is dissolved, and obtains silicon nanometer column structure, silicon in the silicon chip surface not covered by metal grid lines electrode
Nanometer rod structure average diameter is 100 nanometers, highly for 300 nanometers.
In such scheme, high temperature sintering described in step 5, it is to keep 5 minutes at 700 degrees Celsius, make metal grid lines electrode
Form Ohmic contact with silicon chip.
(3) beneficial effect
The invention provides a kind of manufacture method of selectivity nano texturing silicon cell, the method prepares p-n first
Structure, then prepares metal electrode, finally prepares nano-array with cesium chloride nano island self-assembling technique, completes selectivity nano
The making of texturing silicon cell.Its manufacture method is using cesium chloride self assembly and plasma etching technology, vacuum coating
Technology completes., with respect to conventional method, that is, first ultraviolet photolithographic is pre- for the manufacture method of this selectivity nano texturing silicon cell
Stay gate patterns, then nanotexturing, then prepare p-n junction, the method that last alignment is deposited with gate line electrode, decrease ultraviolet
The step such as photoetching and alignment, process is simply a lot, and cost decreases, and technology difficulty also decreases, and is more suitable for work
Industry produces.
Brief description
Fig. 1 is the method flow diagram of the making selectivity nano texturing silicon cell that the present invention provides；
Fig. 2 to Fig. 6 is the process chart of the making selectivity nano texturing silicon cell according to the embodiment of the present invention；
Fig. 7 is to be about 100 nanometers according to the average diameter that the embodiment of the present invention makes, and height is about 300 nanometers of nanometer
The sem figure of post array.
Specific embodiment
For making the object, technical solutions and advantages of the present invention become more apparent, below in conjunction with specific embodiment, and reference
Accompanying drawing, the present invention is described in more detail.
The invention provides a kind of manufacture method of selectivity nano texturing silicon cell, the method prepares p-n first
Structure, then prepares metal electrode, finally prepares nano-array with cesium chloride nano island self-assembling technique, completes selectivity nano
The making of texturing silicon cell.Its manufacture method is using cesium chloride self assembly and plasma etching technology, vacuum coating
Technology completes.(i.e. first ultraviolet photolithographic is pre- with respect to conventional method for the manufacture method of this selectivity nano texturing silicon cell
Stay gate patterns, then nanotexturing, then prepare p-n junction, the method that last alignment is deposited with gate line electrode), decrease purple
The step such as outer photoetching and alignment, process is simply a lot, and cost decreases, and technology difficulty also decreases, and is more suitable for
Commercial production.
As shown in figure 1, the method flow diagram of the making selectivity nano texturing silicon cell that Fig. 1 is the present invention to be provided,
This selectivity nano texturing silicon cell refer to only except metal grid lines electrode (titanium silver layer) with the silicon chip of exterior domain by nanometer
Texturing, the silicon chip under metal grid lines electrode covers remains intact silicon structure, does not etch nano column array；Method include with
Lower step:
The first step, the method using thermal diffusion carries out phosphorus oxychloride diffusion to silicon chip, in front side of silicon wafer, the back side and side shape
Become p-n junction structure；
Second step, the method for using plasma etching removes the p-n junction structure of silicon chip back side and side, is gone with Fluohydric acid.
Silicon dioxide layer except front side of silicon wafer；
3rd step, forms metal grid lines electrode using hollow out metal mask coating technique in front side of silicon wafer evaporation titanium silver layer,
And in silicon chip back side, aluminum back electrode layer is evaporated using vacuum coating mode；
4th step, grows one layer of cesium chloride thin film in the silicon chip surface being formed with metal grid lines electrode, in metal after development
The silicon chip surface not covered on gate line electrode and by metal grid lines electrode forms cesium chloride nanometer and justifies island structure, then with chlorination
Caesium nanometer circle island structure is mask, using plasma etching technology etching silicon wafer, cesium chloride structure is transferred on silicon face,
The cesium chloride nanometer circle island of the silicon chip surface then removing on metal grid lines electrode and not covered by metal grid lines electrode is tied
Structure, obtains silicon nanometer column structure in the silicon chip surface not covered by metal grid lines electrode；
Finally, high temperature sintering, makes metal grid lines electrode and silicon chip form good Ohmic contact.
In the present invention, for the silicon chip preparing p-n junction structure, first prepare electrode layer with thermal evaporation, then use certainly
Assembling cesium chloride nano island technology to complete silicon face selectivity nano texturing with micro-machined plasma etching technology, this
(first ultraviolet photolithographic reserves gate patterns, then nanotexturing, then prepares p-n junction, and last alignment is deposited with grid with conventional method
The method of line electrode) it is distinct.That the method is achieved it is critical that cesium chloride nano island self-assembling technique with etc.
The method that plasma etching technology prepares silicon nano column array does not interfere with the titanium silver electrode layer having prepared.Subtract in this method
The steps such as ultraviolet photolithographic and alignment in conventional method are lacked, process is simply a lot, and cost decreases, technology difficulty
Decrease, be more suitable for commercial production.
Whole technological process is as shown in Figures 2 to 6.The silicon chip that silicon materials are used from semi-conductor industry, thickness 0.2-
0.5 millimeter, p-type, resistivity is 1-3 ω cm, and surface is single-sided polishing (burnishing surface is front, and non-burnishing surface is the back side).This
The manufacture method planting selectivity nano texturing silicon cell comprises the following steps:
First, p-n junction structure is made with the method for thermal diffusion, liquid phosphorus oxychloride is carried along into diffusion furnace furnace chamber by nitrogen
Interior, phosphorus atoms form p-n junction, such as Fig. 2 in front side of silicon wafer, the back side and side in high temperature because thermal diffusion is moved into silicon chip
Shown.Diffusion conditionses are: in 850 degree of diffusion furnaces, are passed through the nitrogen 100sccm carrying phosphorus oxychloride, spread 13 minutes, are formed
P-n junction, square resistance is 30 ω/, and junction depth is about 400 nanometers.
Second, the method for using plasma etching removes the p-n junction structure of silicon chip back side and side, is removed with Fluohydric acid.
The silicon dioxide layer of silicon chip front side of silicon wafer, as shown in Figure 3.
3rd, prepare metal gates using hollow out metal mask coating technique.By the hollow out gold with electrode patterning structure
Belong to mask to cover in silicon chip front surface, evaporate 1 micron of thick titanium silver layer as metal with the method for thermal evaporation in silicon chip front surface
Gate line electrode, silicon chip back side all prepares the aluminum back electrode layer of 200 nanometer thickness with the method for thermal evaporation, as shown in Figure 4.
4th, silicon chip is put in vacuum coating cavity, thermal evaporation cesium chloride thin film, 100 nanometers of thickness.Cesium chloride thin film plates
Into cavity, after complete, it is passed through the gas of certain humidity, in holding chamber body, relative humidity is 35%, and 30 minutes, cesium chloride was in humidity
Gas effect is lower to reunite, and is formed in silicon chip surface (exposed silicon and titanium silver electrode layer surface) and is similar to receiving of water droplet one by one
Rice cesium chloride peninsular structure, average diameter is 150 nanometers, as shown in Figure 5.With cesium chloride island structure as mask, using plasma
Body lithographic technique etches silicon, cesium chloride structure is transferred on silicon face, etching condition is: sf6:c4f8: he=60:150:
10sccm, operating pressure 4pa, 400 watts of exciting power, substrate bias power is 30 watts, etch period 30 seconds.Silicon face etching completes
Afterwards, sample is put in deionized water and soak 2 minutes, you can remaining cesium chloride is dissolved.Because etching gas can not be with
Titanium silver metal reacts, and etching process has no significant effect to titanium silver metal layer, and the covering of titanium silver layer serves guarantor to silicon
Shield effect is it is impossible to form nanometer rod structure, the region therefore only not having titanium silver layer in silicon chip surface prepares a nanometer column
Texturing, silicon nanometer rod structure average diameter is about 100 nanometers, and height is about 300 nanometers, and the no obvious shadow of titanium silver metal layer
Ring, as shown in Figure 6.
5th, high temperature sintering, 700 degree keep 5 minutes, make metal grid lines electrode and silicon chip form good Ohmic contact.
So far complete the making of selectivity nano texturing silicon cell, that is, gate line electrode (titanium silver layer) covers in smooth silicon face,
Do not etch nano column array, increase Ohmic contact, reduce lattice defect.It is prepared for nano-pillar battle array in the region in addition to grid line
Row, play absorption incident illumination, reduce the effect of reflection.
Fig. 7 is about 100 nanometers for average diameter, and height is about the sem figure of 300 nanometers of nano column array.
Embodiment
Step 1, the silicon chip of cleaning is placed in 850 degree of diffusion furnaces, is passed through the nitrogen 100sccm carrying phosphorus oxychloride, expands
Dissipate 13 minutes, form p-n junction, square resistance is 30 ω/, junction depth is about 400 nanometers.
Step 2, the method for the silicon chip plasma etching of step 1 is removed the p-n junction structure of the back side and side.Silicon chip
Upward, front is protected at the back side, and etching condition is sf6: he=120:10sccm, operating pressure 4pa, 500 watts of exciting power, partially
Pressure power is 30 watts, etch period 5 minutes.
Step 3, the Fluohydric acid. (mass fraction is 5%) of the silicon chip dilution of step 2 is soaked 5 minutes, removes silicon chip table
The silicon dioxide layer in face.
Step 4, the hollow out metal mask with electrode patterning structure is covered the front surface of the silicon chip in step 3, with heat
The method of evaporation evaporates 1 micron of thick titanium/silver electrode layer, the aluminium electrode of silicon chip back side evaporation preparation 200 nanometer thickness in front surface
Layer.
Step 5, the silicon chip of step 4 is put in vacuum coating cavity, thermal evaporation cesium chloride thin film, 100 nanometers of thickness.Chlorine
After change caesium thin film has plated, it is passed through the gas of certain humidity into cavity, in holding chamber body, relative humidity is 35%, 30 minutes,
Silicon chip surface (silicon and titanium silver electrode layer surface) forms the nanometer cesium chloride peninsular structure being similar to water droplet one by one, and average diameter is
150 nanometers.
Step 6, the surface of step 5 is had titanium silver electrode layer and the silicon chip of cesium chloride island structure to put into plasma etching machine
Etching cavity in, etch process parameters be pressure 4pa, etching gas sf6:c4f8: he=60:150:10sccm, exciting power
400 watts, substrate bias power is 30 watts, etch period 30 seconds.
Step 7, will put into after the silicon chip extracting of step 6 in deionized water, soaks 2 minutes, makes remaining chlorination on silicon chip
Caesium dissolves.The region not having titanium silver layer in silicon chip surface prepares a nanometer column texturing, silicon nanometer rod structure average diameter
It is about 100 nanometers, height is about 300 nanometers.
Step 8, high temperature sintering, 700 DEG C, 5 minutes, form good Ohmic contact.
Particular embodiments described above, has carried out detailed further to the purpose of the present invention, technical scheme and beneficial effect
Describe in detail bright, be should be understood that the specific embodiment that the foregoing is only the present invention, be not limited to the present invention, all
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvement done etc., should be included in the guarantor of the present invention
Within the scope of shield.
Claims (9)
1. a kind of method making selectivity nano texturing silicon cell is it is characterised in that this selectivity nano texture SiClx
Light cell be only except metal grid lines electrode nanotexturing with the silicon chip of exterior domain, metal grid lines electrode cover under silicon
Piece remains intact silicon structure, does not etch nano column array；The method includes:
Step 1: phosphorus oxychloride diffusion is carried out to silicon chip, forms p-n junction structure in front side of silicon wafer, the back side and side；
Step 2: remove the p-n junction structure of silicon chip back side and side, and remove the silicon dioxide layer of front side of silicon wafer；
Step 3: form metal grid lines electrode in front side of silicon wafer evaporation titanium silver layer, and form aluminum back electrode layer in silicon chip back side；
Step 4: be formed with metal grid lines electrode silicon chip surface grow cesium chloride thin film, after development metal grid lines electrode it
Silicon chip surface that is upper and not covered by metal grid lines electrode forms cesium chloride nanometer and justifies island structure, then justifies island with cesium chloride nanometer
Structure is mask etching silicon chip, cesium chloride nanometer circle island structure is transferred on silicon face, removes cesium chloride nanometer and justify island structure,
Obtain silicon nanometer column structure in the silicon chip surface not covered by metal grid lines electrode；
Step 5: high temperature sintering, make metal grid lines electrode form Ohmic contact with silicon chip.
2. the method making selectivity nano texturing silicon cell according to claim 1 is it is characterised in that described silicon
Piece adopts p-type silicon chip, thickness 0.2-0.5 millimeter, and resistivity is 1-3 ω cm, and surface is single-sided polishing, and burnishing surface is front,
Non- burnishing surface is the back side.
3. the method making selectivity nano texturing silicon cell according to claim 1 is it is characterised in that step 1
Described in silicon chip carried out with phosphorus oxychloride diffusion realized using the method for thermal diffusion, thermal diffusion condition is: spreads at 850 degrees Celsius
In stove, it is passed through the nitrogen 100sccm carrying phosphorus oxychloride, spreads 13 minutes, form p-n junction, square resistance is 30 ω/, knot
Deep about 400 nanometers.
4. the method making selectivity nano texturing silicon cell according to claim 1 is it is characterised in that step 2
Described in remove silicon chip back side and side the method for p-n junction structure using plasma etching realize, described removal silicon chip is just
The silicon dioxide layer in face adopts Fluohydric acid. to realize.
5. the method making selectivity nano texturing silicon cell according to claim 1 is it is characterised in that step 3
Described in front side of silicon wafer be deposited with titanium silver layer adopt vacuum coating method realize, described silicon chip back side formed aluminum back electrode layer
Realized by the way of vacuum coating.
6. according to claim 5 make selectivity nano texturing silicon cell method it is characterised in that described
Front side of silicon wafer is deposited with titanium silver layer and adopts the method for vacuum coating to realize, and is in front side of silicon wafer using hollow out metal mask coating technique
Prepare metal gates, cover the hollow out metal mask with electrode patterning structure in front side of silicon wafer first, then steamed using heat
The method sent out evaporates 1 micron of thick titanium silver layer as metal grid lines electrode in front side of silicon wafer.
7. according to claim 5 make selectivity nano texturing silicon cell method it is characterised in that described
Silicon chip back side is formed aluminum back electrode layer and is realized by the way of vacuum coating, is the method preparation adopting thermal evaporation in silicon chip back side
The aluminum back electrode layer of 200 nanometer thickness.
8. the method making selectivity nano texturing silicon cell according to claim 1 is it is characterised in that described step
Rapid 4 include:
The silicon chip being formed with metal grid lines electrode is put in vacuum coating cavity, thermal evaporation cesium chloride thin film, thickness 100 is received
Rice；Into cavity, after cesium chloride thin film has plated, it is passed through the gas of certain humidity, in holding chamber body, relative humidity is 35%, 30 points
Clock, cesium chloride is reunited under the effect of humidity gas, and is not covered by metal grid lines electrode on metal grid lines electrode
Silicon chip surface forms the nanometer cesium chloride peninsular structure being similar to water droplet one by one, and average diameter is 150 nanometers；With cesium chloride island knot
Structure is mask, etches silicon using plasma etching technology, cesium chloride structure is transferred on silicon face, etching condition is: sf6
For 60sccm, c4f8For 150sccm, he is 10sccm, operating pressure 4pa, 400 watts of exciting power, and substrate bias power is 30 watts, carves
30 seconds erosion time；After the completion of silicon face etching, sample is put in deionized water and soaks 2 minutes, by remaining cesium chloride dissolving
Fall, obtain silicon nanometer column structure in the silicon chip surface not covered by metal grid lines electrode, silicon nanometer rod structure average diameter is
100 nanometers, highly for 300 nanometers.
9. the method making selectivity nano texturing silicon cell according to claim 1 is it is characterised in that step 5
Described in high temperature sintering, be to keep 5 minutes at 700 degrees Celsius, make metal grid lines electrode and silicon chip form Ohmic contact.
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