CN104980323A

CN104980323A - Ethernet strip steel surface image data processing platform based on DSP

Info

Publication number: CN104980323A
Application number: CN201410143308.1A
Authority: CN
Inventors: 王奎越; 王晓慧; 王军生; 高冰; 宋宝宇; 王靖震; 杨东晓; 刘宝权; 宋君; 吴萌
Original assignee: Angang Steel Co Ltd
Current assignee: Angang Steel Co Ltd
Priority date: 2014-04-10
Filing date: 2014-04-10
Publication date: 2015-10-14

Abstract

The invention provides an Ethernet strip steel surface image data processing platform based on DSP, comprising a DSP chip, a PLL clock circuit, a program memory, a data memory, an Ethernet control circuit, a power module and a CCD camera. The DSP chip uses DSP chip DM648 of an IT company as a core processor of the processing platform. The DSP chip is connected with the program memory via an external memory interface of the chip; the data memory is connected with a dynamic memory special control interface of the DSP chip via data bus; the Ethernet control circuit is directly connected with an EMAC interface of the DSP chip. The processing platform of the invention could improve access speed of the DSP chip to image data, collect the image of the CCD camera with the Ethernet control circuit, and process the image with the DSP chip. The processing platform of the invention not only greatly improves the integration level of the system, but also reduces the system cost so as to be suitable for popularization and application.

Description

A kind of Ethernet band steel surface image data processing platform (DPP) based on DSP

Technical field

The invention belongs to ethernet data communication and the process field of embedded system, be specifically related to a kind of Ethernet band steel surface image data processing platform (DPP) based on DSP.

Background technology

Along with the continuous increase of iron and steel enterprise's competitive pressure, the requirement of strip surface quality is also constantly promoted, and strip surface quality detection system becomes raising strip quality, promote the requisite equipment of iron and steel enterprise's product competitiveness.In industrial data acquisition system field, each side for transfer of data requires all more and more higher, and Industrial Ethernet becomes the preferred manner of current industrial remote data communication system with its transfer of data at a high speed, reliable and stable technology and the advantage with telecommunication.

DSP flush bonding processor becomes the main flow embedded microcontroller of Ethernet data sampling and processing due to the handling property of its real time high-speed, complete ethernet communication interfacing and higher cost performance.The C6000 family chip of TI company is integrated with Ethernet interface on its sheet, not only on hardware by the network application cost reduction 50% of embedded product, and in conjunction with its release NDK Web development tool greatly can shorten software development cycle.

The strip surface quality detection system that current all kinds of production line uses is all the frame structures adopting ccd image acquisition module+server, as the HTS serial band-steel surface detecting system of German Parsytec company, the cold-strip steel that the iS-2000 automatic checkout system of Cognex company of the U.S. and University of Science & Technology, Beijing Xu Ke etc. develop and Surfaces of Hot Rolled Strip on-line detecting system etc., all the structures adopting every platform CCD camera to be equipped with a set of special image analog input card or image acquisition and processing server, system is huge, cost intensive.

Summary of the invention

The invention provides a kind of Ethernet band steel surface image data processing platform (DPP) based on DSP, its object is intended to the integrated level improving detection system, cost-saving, realizes the Ethernet transmission to surface of steel plate view data and processing capacity.

For this reason, the technical solution that the present invention takes is:

Based on an Ethernet band steel surface image data processing platform (DPP) of DSP, it is characterized in that, comprising: dsp chip, pll clock circuit, program storage, data storage, Ethernet control circuit, power module and CCD camera; Dsp chip is connected with program storage by the external memory interface of chip, and data storage is connected with the special control interface of the dynamic memory of dsp chip by data/address bus, and Ethernet control circuit is directly connected with the EMAC interface of dsp chip.

Described dsp chip adopts the core processor of dsp chip DM648 as processing platform of TI company, and chip has external memory interface, the special control interface of dynamic memory, EMAC interface, clock signal input interface, PLL power interface.

Described pll clock circuit is made up of crystal oscillator chip and noise filter, and being respectively used to provides the external clock input signal of dsp chip and realize PLL frequency multiplication of phase locked loop function.

Described program storage uses FLASH memory as the program storage of dsp chip, and the data terminal of dsp chip external memory interface and address end are connected to data terminal and the address end of FLASH memory respectively.

Described data storage uses two panels dynamic memory DDR2 chip, be connected with the special control interface of the dynamic memory of dsp chip respectively, high 16 of the FPDP of two panels dynamic memory control interface special with dynamic memory are respectively connected with low 16 bit data ports.

Described Ethernet control circuit is made up of 88E1111 ethernet control chip, hardware interface RJ45, the data that RJ45 gathers via the data input output ports of 88E1111 finally by the EMAC interface of dsp chip.

Beneficial effect of the present invention is:

The surface of steel plate view data collected is transferred to this platform by Ethernet control circuit by the CCD camera of platform exterior, is transferred to platform exterior system is again further processed after the preliminary treatment such as denoising, splicing of dsp chip by Ethernet control circuit.The jumbo data storage of processing platform is as the memory block of view data and system data, substantially increase the access speed of dsp chip to view data, achieve the collection utilizing Ethernet control circuit to CCD camera image, and the function that processes is carried out by the dsp chip of platform, not only greatly improve the integrated level of system, and can system cost be reduced, be conducive to applying.

Accompanying drawing explanation

Fig. 1 is band steel surface image data processing platform (DPP) structured flowchart;

Fig. 2 is processing platform pll clock circuit theory diagrams;

Fig. 3 is processing platform program storage interface schema;

Fig. 4 is processing platform data storage interface schema;

Fig. 5 is Ethernet control circuit schematic diagram;

Fig. 6 is power circuit principle figure.

Embodiment

Below in conjunction with accompanying drawing, the present invention is described in more detail:

Composition graphs 1, the Ethernet band steel surface image data processing platform (DPP) based on DSP consists of the following components: CCD camera, dsp chip, pll clock circuit, program storage, data storage, Ethernet control circuit and power module.Wherein, dsp chip adopts the core processor of dsp chip DM648 as processing platform of TI company, and chip has external memory interface, the special control interface of dynamic memory, EMAC interface, clock signal input interface, PLL power interface.Pll clock circuit provides the system clock of processing platform, dsp chip is connected with program storage by the external memory interface of chip, data storage is connected with the special control interface of the dynamic memory of dsp chip by data/address bus, and Ethernet control circuit is directly connected with the EMAC interface of dsp chip.

Composition graphs 2PLL clock circuit schematic diagram, pll clock circuit is primarily of 27MHz and 36MHz crystal oscillator, 1.8V power supply, two noise filter compositions, the signal output part of 27MHz and 36MHz crystal oscillator is directly connected to clock signal input interface CLKIN1 and the CLKIN2 of DM648, as the external clock source of chip; 1.8V power supply via two ports of PLL power interface PLLV1 and PLLV2 accessing DM648 after the filtering of two-way noise filter, in DM648 sheet, pll clock circuit provides required power supply.

Composition graphs 3 program storage interface principle figure, program storage adopts FLASH memory, data terminal DQ0 ~ the DQ15 of FLASH memory is connected to the data terminal AED00 ~ AED15 of dsp chip external memory interface successively, the address end A1 ~ A24 of FLASH memory is connected to the address end AEA00 ~ AEA23 of dsp chip external memory interface successively, the address end A0 of FLASH memory is then connected to the ABA1 port of dsp chip external memory interface, composition addressing space reaches 32M, and data width is the program storage of 16.

Composition graphs 4 data storage interface schema, the address end A0 ~ A13 of DDR2 data storage 1 and DDR2 data storage 2 is connected to DDR_A00 ~ DDR_A13 port of the special control interface of dynamic memory on DM648 sheet simultaneously, data terminal DQ0 ~ DQ15 that the data terminal DQ0 ~ DQ15 of DDR2 data storage 1 is connected to high 16 DDR_D00 ~ DDR_D15, DDR2 data storages 2 of dynamic memory special control interface FPDP on DM648 sheet is connected to low 16 DDR_D16 ~ DDR_D31 of dynamic memory special control interface FPDP on DM648 sheet.

Composition graphs 5 Ethernet control circuit schematic diagram, hardware interface RJ45 is directly connected with the transmission medium such as netting twine, receives the data that Ethernet transmission comes, ethernet control chip 88E1111 data-in port MDI [0]+, MDI [0]-, MDI [1]+, MDI [1]-, MDI [2]+, MDI [2]-, MDI [3]+, the T1+ of MDI [3]-be connected to successively RJ45, T1-, T2+, T2-, T3+, T3-, T4+, T4-pin, data-out port S_OUT+, S_OUT-is connected to SGMII0RXN and the SGMII0RXP port that EMAC on DM648 sheet is responsible for Ethernet data reception, the S_IN+ of 88E1111, S_IN-is connected to SGMII0TXN and the SGMII0TXP port that EMAC is responsible for data transmission.

Composition graphs 6, external 5V power supply is converted to 2.5V and 3.3V power supply respectively via two panels power supply chip TPS54331DR and exports, 2.5V power supply is mainly ethernet communication chip 88E1111 and provides required working power, and 3.3V power supply is mainly dynamic memory special control interface chip and provides required working power.

Claims

1. based on an Ethernet band steel surface image data processing platform (DPP) of DSP, it is characterized in that, comprising: dsp chip, pll clock circuit, program storage, data storage, Ethernet control circuit, power module and CCD camera; Dsp chip is connected with program storage by the external memory interface of chip, and data storage is connected with the special control interface of the dynamic memory of dsp chip by data/address bus, and Ethernet control circuit is directly connected with the EMAC interface of dsp chip;

Described dsp chip adopts the core processor of dsp chip DM648 as processing platform of TI company, and chip has external memory interface, the special control interface of dynamic memory, EMAC interface, clock signal input interface, PLL power interface;

Described pll clock circuit is made up of crystal oscillator chip and noise filter, and being respectively used to provides the external clock input signal of dsp chip and realize PLL frequency multiplication of phase locked loop function;

Described program storage uses FLASH memory as the program storage of dsp chip, and the data terminal of dsp chip external memory interface and address end are connected to data terminal and the address end of FLASH memory respectively;

Described data storage uses two panels dynamic memory DDR2 chip, be connected with the special control interface of the dynamic memory of dsp chip respectively, high 16 of the FPDP of two panels dynamic memory control interface special with dynamic memory are respectively connected with low 16 bit data ports;

Described Ethernet control circuit is made up of 88E1111 ethernet control chip, hardware interface RJ45, the data that RJ45 collects via the data input output ports of 88E1111 finally by the EMAC interface of dsp chip.